/ {
compatible = "rockchip,android", "rockchip,rk3399";
+ aliases {
+ lcdc0 = &vopb_rk_fb;
+ lcdc1 = &vopl_rk_fb;
+ };
+
chosen {
- bootargs = "earlycon=uart8250,mmio32,0xff1a0000";
+ bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
};
ramoops_mem: ramoops_mem {
- reg = <0x0 0x100000 0x0 0x100000>;
+ reg = <0x0 0x110000 0x0 0xf0000>;
reg-names = "ramoops_mem";
};
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
- ftrace-size = <0x0 0x10000>;
+ ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
size = <0x0 0x8000000>;
linux,cma-default;
};
+ /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
+ rockchip_logo: rockchip-logo@00000000 {
+ compatible = "rockchip,fb-logo";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
};
ion {
};
};
+ cdn_dp_fb: dp-fb@fec00000 {
+ status = "disabled";
+ compatible = "rockchip,rk3399-cdn-dp-fb";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>;
+ reset-names = "spdif", "dptx", "apb";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ cdn_dp_sound: cdn-dp-sound {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,cdn-dp-fb";
+ simple-audio-card,widgets = "Headphone", "Out Jack",
+ "Line", "In Jack";
+
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ mclk-fs = <256>;
+
+ cpu {
+ sound-dai = <&i2s2>;
+ };
+
+ codec {
+ sound-dai = <&cdn_dp_fb 0>;
+ };
+ };
+ };
+
vpu: vpu_service@ff650000 {
compatible = "rockchip,vpu_service";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
reg = <0x0 0xff650000 0x0 0x800>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "irq_dec", "irq_enc";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
power-domains = <&power RK3399_PD_VCODEC>;
name = "vpu_service";
dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
};
vpu_mmu: vpu_mmu {
dbgname = "vpu";
compatible = "rockchip,vpu_mmu";
reg = <0x0 0xff650800 0x0 0x40>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vpu_mmu";
};
rockchip,grf = <&grf>;
iommu_enabled = <1>;
reg = <0x0 0xff660000 0x0 0x400>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
power-domains = <&power RK3399_PD_VDU>;
dev_mode = <2>;
name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
};
vdec_mmu: vdec_mmu {
compatible = "rockchip,vdec_mmu";
reg = <0x0 0xff660480 0x0 0x40>,
<0x0 0xff6604c0 0x0 0x40>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdec_mmu";
};
compatible = "rockchip,iep";
iommu_enabled = <1>;
reg = <0x0 0xff670000 0x0 0x800>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk_iep", "hclk_iep";
power-domains = <&power RK3399_PD_IEP>;
dbgname = "iep";
compatible = "rockchip,iep_mmu";
reg = <0x0 0xff670800 0x0 0x40>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";
};
compatible = "rockchip,rga2";
dev_mode = <1>;
reg = <0x0 0xff680000 0x0 0x1000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
power-domains = <&power RK3399_PD_RGA>;
status = "okay";
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <DUAL>;
+ rockchip,uboot-logo-on = <1>;
+ memory-region = <&rockchip_logo>;
};
rk_screen: screen {
compatible = "rockchip,rk3399-lcdc";
rockchip,prop = <PRMRY>;
reg = <0x0 0xff900000 0x0 0x3efc>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <1>;
power-domains = <&power RK3399_PD_VOPB>;
+ devfreq = <&dmc>;
};
vopb_mmu_rk_fb: vopb-mmu {
dbgname = "vop";
compatible = "rockchip,vopb_mmu";
reg = <0x0 0xff903f00 0x0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
};
compatible = "rockchip,rk3399-lcdc";
rockchip,prop = <EXTEND>;
reg = <0x0 0xff8f0000 0x0 0x3efc>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <1>;
power-domains = <&power RK3399_PD_VOPL>;
+ devfreq = <&dmc>;
};
vopl_mmu_rk_fb: vopl-mmu {
dbgname = "vop";
compatible = "rockchip,vopl_mmu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
};
+ cif_isp0: cif_isp@ff910000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ rockchip,grf = <&grf>;
+ reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
+ reg-names = "register", "dsihost-register";
+ clocks =
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+ <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+ <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+ clock-names =
+ "clk_cif_out", "clk_cif_pll",
+ "pclk_dphytxrx", "pclk_dphy_ref",
+ "aclk_isp0_noc", "aclk_isp0_wrapper",
+ "hclk_isp0_noc", "hclk_isp0_wrapper",
+ "clk_isp0", "pclk_dphyrx";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "cif_isp10_irq";
+ power-domains = <&power RK3399_PD_ISP0>;
+ status = "disabled";
+ };
+
+ isp0: isp@ff910000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+ <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+ <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+ clock-names =
+ "clk_cif_out", "clk_cif_pll",
+ "pclk_dphytxrx", "pclk_dphy_ref",
+ "aclk_isp0_noc", "aclk_isp0_wrapper",
+ "hclk_isp0_noc", "hclk_isp0_wrapper",
+ "clk_isp0", "pclk_dphyrx";
+ pinctrl-names =
+ "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP0>;
+ status = "disabled";
+ };
+
+ isp0_mmu {
+ dbgname = "isp0";
+ compatible = "rockchip,isp0_mmu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp0_mmu";
+ };
+
+ isp1: isp@ff920000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff920000 0x0 0x10000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
+ <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
+ <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
+ <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_MIPIDPHY_CFG>;
+ clock-names =
+ "aclk_isp1_noc", "aclk_isp1_wrapper",
+ "hclk_isp1_noc", "hclk_isp1_wrapper",
+ "clk_isp1", "clk_cif_out",
+ "clk_cif_pll", "pclk_dphytxrx",
+ "pclk_dphy_ref", "pclk_isp1",
+ "pclk_dphyrx", "pclk_mipi_dsi",
+ "mipi_dphy_cfg";
+ pinctrl-names =
+ "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP1>;
+ status = "disabled";
+ };
+
+ isp1_mmu {
+ dbgname = "isp1";
+ compatible = "rockchip,isp1_mmu";
+ reg = <0x0 0xff924000 0x0 0x100>,
+ <0x0 0xff925000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp1_mmu";
+ };
+
hdmi_rk_fb: hdmi-rk-fb@ff940000 {
status = "disabled";
compatible = "rockchip,rk3399-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>,
<&cru HCLK_HDCP>,
<&cru SCLK_HDMI_CEC>,
rockchip,prop = <0>;
rockchip,grf = <&grf>;
reg = <0x0 0xff960000 0x0 0x8000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
power-domains = <&power RK3399_PD_VIO>;
rockchip,prop = <1>;
rockchip,grf = <&grf>;
reg = <0x0 0xff968000 0x0 0x8000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
power-domains = <&power RK3399_PD_VIO>;
compatible = "rockchip,rk3399-edp-fb";
reg = <0x0 0xff970000 0x0 0x8000>;
rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "pclk_edp";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+ clock-names = "clk_edp", "pclk_edp", "clk_grf";
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "edp_apb";
status = "disabled";
+ power-domains = <&power RK3399_PD_EDP>;
};
+};
- hdmi_sound: hdmi-sound {
- status = "disabled";
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "rockchip,hdmi";
- simple-audio-card,cpu {
- sound-dai = <&i2s2>;
+&pinctrl {
+ isp {
+ cif_clkout: cif-clkout {
+ rockchip,pins =
+ /*cif_clkout*/
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
};
- simple-audio-card,codec {
- sound-dai = <&dw_hdmi_audio>;
+
+ isp_dvp_d0d7: isp-dvp-d0d7 {
+ rockchip,pins =
+ /*cif_data0*/
+ <2 0 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data1*/
+ <2 1 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data2*/
+ <2 2 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data3*/
+ <2 3 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data4*/
+ <2 4 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data5*/
+ <2 5 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data6*/
+ <2 6 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data7*/
+ <2 7 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_sync*/
+ <2 8 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_href*/
+ <2 9 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_clkin*/
+ <2 10 RK_FUNC_3 &pcfg_pull_none>;
};
- };
- dw_hdmi_audio: dw-hdmi-audio {
- status = "disabled";
- compatible = "rockchip,dw-hdmi-audio";
- #sound-dai-cells = <0>;
- };
-};
+ isp_shutter: isp-shutter {
+ rockchip,pins =
+ /*SHUTTEREN*/
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,
+ /*SHUTTERTRIG*/
+ <1 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
-&i2s2 {
- #sound-dai-cells = <0>;
-};
+ isp_flash_trigger: isp-flash-trigger {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_prelight: isp-prelight {
+ /*ISP_PRELIGHTTRIG*/
+ rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
-&usbdrd_dwc3_0 {
- dr_mode = "peripheral";
+ isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cam_pins {
+ cam0_default_pins: cam0-default-pins {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ cam0_sleep_pins: cam0-sleep-pins {
+ rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
+ <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff