reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
- <&cru SCLK_SPDIF_REC_DPTX>;
- clock-names = "core-clk", "pclk", "spdif";
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
- resets = <&cru SRST_DPTX_SPDIF_REC>;
- reset-names = "spdif";
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>;
+ reset-names = "spdif", "dptx", "apb";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&power RK3399_PD_VCODEC>;
name = "vpu_service";
dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
};
vpu_mmu: vpu_mmu {
power-domains = <&power RK3399_PD_VDU>;
dev_mode = <2>;
name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <0>;
};
vdec_mmu: vdec_mmu {
interrupt-names = "vopl_mmu";
};
+ cif_isp0: cif_isp@ff910000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ rockchip,grf = <&grf>;
+ reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
+ reg-names = "register", "dsihost-register";
+ clocks =
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+ <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+ <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+ clock-names =
+ "clk_cif_out", "clk_cif_pll",
+ "pclk_dphytxrx", "pclk_dphy_ref",
+ "aclk_isp0_noc", "aclk_isp0_wrapper",
+ "hclk_isp0_noc", "hclk_isp0_wrapper",
+ "clk_isp0", "pclk_dphyrx";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "cif_isp10_irq";
+ power-domains = <&power RK3399_PD_ISP0>;
+ status = "disabled";
+ };
+
isp0: isp@ff910000 {
compatible = "rockchip,rk3399-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x10000>;
reg = <0x0 0xff970000 0x0 0x8000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "pclk_edp";
+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+ clock-names = "clk_edp", "pclk_edp", "clk_grf";
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "edp_apb";
status = "disabled";
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ cam_pins {
+ cam0_default_pins: cam0-default-pins {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ cam0_sleep_pins: cam0-sleep-pins {
+ rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
+ <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};