rockchip,adc_value = <450>;
};
};
-};
-&mipi_dsi {
- status = "okay";
- panel {
- compatible ="simple-panel-dsi";
- reg = <0>;
- backlight = <&backlight>;
- enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>;
- dsi,format = <MIPI_DSI_FMT_RGB888>;
- dsi,lanes = <4>;
- status = "okay";
+ vpu: vpu_service@ff650000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff650000 0x0 0x800>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VCODEC>;
+ name = "vpu_service";
+ dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <160000000>;
- hactive = <1200>;
- vactive = <1920>;
- hback-porch = <21>;
- hfront-porch = <120>;
- vback-porch = <18>;
- vfront-porch = <21>;
- hsync-len = <20>;
- vsync-len = <3>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <0>;
- pixelclk-active = <0>;
- };
- };
+ vpu_mmu: iommu@ff650800 {
+ dbgname = "vpu";
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ };
+
+ rkvdec: rkvdec@ff660000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff660000 0x0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VDU>;
+ dev_mode = <2>;
+ name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ dbgname = "vdec";
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ #iommu-cells = <0>;
+ };
+
+ isp0: isp@ff910000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x4000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+ <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+ <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+ clock-names =
+ "clk_cif_out", "clk_cif_pll",
+ "pclk_dphytxrx", "pclk_dphy_ref",
+ "aclk_isp0_noc", "aclk_isp0_wrapper",
+ "hclk_isp0_noc", "hclk_isp0_wrapper",
+ "clk_isp0", "pclk_dphyrx";
+ pinctrl-names =
+ "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP0>;
+ iommus = <&isp0_mmu>;
+ status = "disabled";
+ };
+
+ isp1: isp@ff920000 {
+ compatible = "rockchip,rk3399-isp", "rockchip,isp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks =
+ <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
+ <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
+ <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
+ <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
+ <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
+ <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_MIPIDPHY_CFG>;
+ clock-names =
+ "aclk_isp1_noc", "aclk_isp1_wrapper",
+ "hclk_isp1_noc", "hclk_isp1_wrapper",
+ "clk_isp1", "clk_cif_out",
+ "clk_cif_pll", "pclk_dphytxrx",
+ "pclk_dphy_ref", "pclk_isp1",
+ "pclk_dphyrx", "pclk_mipi_dsi",
+ "mipi_dphy_cfg";
+ pinctrl-names =
+ "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
+ "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+ "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&isp_dvp_d0d7>;
+ pinctrl-2 = <&cif_clkout>;
+ pinctrl-3 = <&isp_prelight>;
+ pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-5 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ power-domains = <&power RK3399_PD_ISP1>;
+ iommus = <&isp1_mmu>;
+ status = "disabled";
+ };
+
+ uboot-charge {
+ compatible = "rockchip,uboot-charge";
+ rockchip,uboot-charge-on = <1>;
+ rockchip,android-charge-on = <0>;
};
};
status = "okay";
};
+&rga {
+ status = "okay";
+};
+
&i2c3 {
status = "okay";
i2c-scl-rising-time-ns = <450>;
&display_subsystem {
status = "okay";
+ ports = <&vopb_out>, <&vopl_out>;
memory-region = <&drm_logo>;
route {
- route0 {
+ route_hdmi: route-hdmi {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
+ connect = <&vopl_out_hdmi>;
+ };
+
+ route_mipi: route-mipi {
+ status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
connect = <&vopb_out_mipi>;
};
- route1 {
+ route_edp: route-edp {
+ status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
- connect = <&vopl_out_hdmi>;
+ logo,mode = "fullscreen";
+ charge_logo,mode = "center";
+ connect = <&vopb_out_edp>;
};
};
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
+
+&pinctrl {
+ isp {
+ cif_clkout: cif-clkout {
+ rockchip,pins =
+ /*cif_clkout*/
+ <2 11 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ isp_dvp_d0d7: isp-dvp-d0d7 {
+ rockchip,pins =
+ /*cif_data0*/
+ <2 0 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data1*/
+ <2 1 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data2*/
+ <2 2 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data3*/
+ <2 3 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data4*/
+ <2 4 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data5*/
+ <2 5 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data6*/
+ <2 6 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_data7*/
+ <2 7 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_sync*/
+ <2 8 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_href*/
+ <2 9 RK_FUNC_3 &pcfg_pull_none>,
+ /*cif_clkin*/
+ <2 10 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ isp_shutter: isp-shutter {
+ rockchip,pins =
+ /*SHUTTEREN*/
+ <1 1 RK_FUNC_1 &pcfg_pull_none>,
+ /*SHUTTERTRIG*/
+ <1 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_flash_trigger: isp-flash-trigger {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_prelight: isp-prelight {
+ /*ISP_PRELIGHTTRIG*/
+ rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
+ /*ISP_FLASHTRIGOU*/
+ rockchip,pins =
+ <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
projects / firefly-linux-kernel-4.4.55.git / blobdiff