};
};
- iep: iep@ff670000 {
- compatible = "rockchip,iep";
- iommu_enabled = <1>;
- reg = <0x0 0xff670000 0x0 0x800>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- clock-names = "aclk_iep", "hclk_iep";
- power-domains = <&power RK3399_PD_IEP>;
- version = <2>;
- };
-
- iep_mmu: iep-mmu {
- dbgname = "iep";
- compatible = "rockchip,iep_mmu";
- reg = <0x0 0xff670800 0x0 0x40>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "iep_mmu";
- };
-
rga: rga@ff680000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
- rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
rockchip,isp,iommu-enable = <1>;
power-domains = <&power RK3399_PD_ISP0>;
status = "disabled";
rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
- rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
rockchip,isp,iommu-enable = <1>;
power-domains = <&power RK3399_PD_ISP1>;
status = "disabled";
compatible = "rockchip,vdec_mmu";
};
+&iep {
+ status = "okay";
+ allocator = <0>;
+};
+
+&iep_mmu {
+ compatible = "rockchip,iep_mmu";
+ status = "okay";
+};
+
&pinctrl {
isp {
cif_clkout: cif-clkout {
isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
/*ISP_FLASHTRIGOU*/
- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};