};
};
- idle-states {
- entry-method = "psci";
-
- cpu_sleep: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <0x3fffffff>;
- exit-latency-us = <0x40000000>;
- min-residency-us = <0xffffffff>;
- };
- };
-
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
};
cluster0_opp: opp_table0 {
#clock-cells = <0>;
};
- xin32k: xin32k {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- #clock-cells = <0>;
- };
-
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
nvmem-cell-names = "temp_adjust";
#thermal-sensor-cells = <1>;
hw-shut-temp = <95000>;
+ latency-bound = <50000>;
status = "disabled";
};
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_BUS>, <&cru ACLK_PERI>,
<&cru HCLK_BUS>, <&cru HCLK_PERI>,
- <&cru PCLK_BUS>, <&cru PCLK_PERI>;
+ <&cru PCLK_BUS>, <&cru PCLK_PERI>,
+ <&cru ACLK_CCI_PRE>;
assigned-clock-rates =
<576000000>, <400000000>,
<300000000>, <300000000>,
<150000000>, <150000000>,
- <75000000>, <75000000>;
+ <75000000>, <75000000>,
+ <576000000>;
};
grf: syscon@ff770000 {
status = "disabled";
};
+ iep: iep@ff900000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3368_PD_VIO>;
+ allocator = <1>;
+ version = <2>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
isp: isp@ff910000 {
compatible = "rockchip,rk3368-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk";
+ resets = <&cru SRST_MIPIDSI0>;
+ reset-names = "apb";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
rockchip,grf = <&grf>;
#size-cells = <0>;
status = "disabled";
- ports@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- mipi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_vop: endpoint@0 {
- reg = <0>;
+ ports {
+ port {
+ mipi_in_vop: endpoint {
remote-endpoint = <&vop_out_mipi>;
};
};
#phy-cells = <0>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
+ resets = <&cru SRST_MIPIDPHYTX>;
+ reset-names = "apb";
status = "disabled";
};