arm64: dts: rockchip: add L2 cache node for rk3368

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 209ff0e1b792b8c942a672ee3ff63723b434b055..57bd06f0c1f6c796a166ebbd5f49e73cd9fad0fc 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -112,25 +112,13 @@
                        };
                };
 
-               idle-states {
-                       entry-method = "psci";
-
-                       cpu_sleep: cpu-sleep-0 {
-                               compatible = "arm,idle-state";
-                               arm,psci-suspend-param = <0x1010000>;
-                               entry-latency-us = <0x3fffffff>;
-                               exit-latency-us = <0x40000000>;
-                               min-residency-us = <0xffffffff>;
-                       };
-               };
-
                cpu_l0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
+                       next-level-cache = <&cluster0_l2>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
                        #cooling-cells = <2>; /* min followed by max */
@@ -141,9 +129,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
+                       next-level-cache = <&cluster0_l2>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
                };
@@ -152,9 +140,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x2>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
+                       next-level-cache = <&cluster0_l2>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
                };
@@ -163,9 +151,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x3>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKL>;
+                       next-level-cache = <&cluster0_l2>;
                        operating-points-v2 = <&cluster0_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
                };
@@ -174,9 +162,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x100>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKB>;
+                       next-level-cache = <&cluster1_l2>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
                        #cooling-cells = <2>; /* min followed by max */
@@ -187,9 +175,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x101>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKB>;
+                       next-level-cache = <&cluster1_l2>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
                };
@@ -198,9 +186,9 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x102>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKB>;
+                       next-level-cache = <&cluster1_l2>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
                };
@@ -209,12 +197,20 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x103>;
-                       cpu-idle-states = <&cpu_sleep>;
                        enable-method = "psci";
                        clocks = <&cru ARMCLKB>;
+                       next-level-cache = <&cluster1_l2>;
                        operating-points-v2 = <&cluster1_opp>;
                        sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
                };
+
+               cluster0_l2: l2-cache0 {
+                       compatible = "cache";
+               };
+
+               cluster1_l2: l2-cache1 {
+                       compatible = "cache";
+               };
        };
 
        cluster0_opp: opp_table0 {
@@ -473,13 +469,6 @@
                #clock-cells = <0>;
        };
 
-       xin32k: xin32k {
-               compatible = "fixed-clock";
-               clock-frequency = <32768>;
-               clock-output-names = "xin32k";
-               #clock-cells = <0>;
-       };
-
        sdmmc: dwmmc@ff0c0000 {
                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -747,6 +736,7 @@
                nvmem-cell-names = "temp_adjust";
                #thermal-sensor-cells = <1>;
                hw-shut-temp = <95000>;
+               latency-bound = <50000>;
                status = "disabled";
        };