enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <149>;
};
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
cpu_l2: cpu@2 {
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
cpu_l3: cpu@3 {
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
cpu_b0: cpu@100 {
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <160>;
};
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
cpu_b2: cpu@102 {
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
cpu_b3: cpu@103 {
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
+ sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
};
};
};
+ energy-costs {
+ RK3368_CPU_COST_0: rk3368-core-cost0 {
+ busy-cost-data = <
+ 146 44 /* 216M */
+ 276 72 /* 408M */
+ 406 99 /* 600M */
+ 552 147 /* 816M */
+ 682 200 /* 1008M */
+ 812 255 /* 1200M */
+ >;
+ idle-cost-data = <
+ 6
+ 6
+ 0
+ >;
+ };
+
+ RK3368_CPU_COST_1: rk3368-core-cost1 {
+ busy-cost-data = <
+ 146 53 /* 216M */
+ 276 86 /* 408M */
+ 406 118 /* 600M */
+ 552 166 /* 816M */
+ 682 226 /* 1008M */
+ 812 309 /* 1200M */
+ 878 371 /* 1200M */
+ 959 446 /* 1416M */
+ 1024 513 /* 1512M */
+ >;
+ idle-cost-data = <
+ 6
+ 6
+ 0
+ >;
+ };
+
+ RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
+ busy-cost-data = <
+ 146 9 /* 216M */
+ 276 14 /* 408M */
+ 406 20 /* 600M */
+ 552 29 /* 816M */
+ 682 40 /* 1008M */
+ 812 51 /* 1200M */
+ >;
+ idle-cost-data = <
+ 56
+ 56
+ 56
+ >;
+ };
+
+ RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
+ busy-cost-data = <
+ 146 11 /* 216M */
+ 276 17 /* 408M */
+ 406 24 /* 600M */
+ 552 33 /* 816M */
+ 682 45 /* 1008M */
+ 812 62 /* 1200M */
+ 878 74 /* 1200M */
+ 959 89 /* 1416M */
+ 1024 103 /* 1512M */
+ >;
+ idle-cost-data = <
+ 56
+ 56
+ 56
+ >;
+ };
+ };
+
cpu_avs: cpu-avs {
cluster0-avs {
cluster-id = <0>;
nvmem-cell-names = "temp_adjust";
#thermal-sensor-cells = <1>;
hw-shut-temp = <95000>;
+ latency-bound = <50000>;
status = "disabled";
};
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_BUS>, <&cru ACLK_PERI>,
<&cru HCLK_BUS>, <&cru HCLK_PERI>,
- <&cru PCLK_BUS>, <&cru PCLK_PERI>;
+ <&cru PCLK_BUS>, <&cru PCLK_PERI>,
+ <&cru ACLK_CCI_PRE>;
assigned-clock-rates =
<576000000>, <400000000>,
<300000000>, <300000000>,
<150000000>, <150000000>,
- <75000000>, <75000000>;
+ <75000000>, <75000000>,
+ <576000000>;
};
grf: syscon@ff770000 {
status = "disabled";
};
+ iep: iep@ff900000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3368_PD_VIO>;
+ allocator = <1>;
+ version = <2>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
isp: isp@ff910000 {
compatible = "rockchip,rk3368-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk";
+ resets = <&cru SRST_MIPIDSI0>;
+ reset-names = "apb";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
rockchip,grf = <&grf>;
#size-cells = <0>;
status = "disabled";
- ports@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- mipi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_vop: endpoint@0 {
- reg = <0>;
+ ports {
+ port {
+ mipi_in_vop: endpoint {
remote-endpoint = <&vop_out_mipi>;
};
};
#phy-cells = <0>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
+ resets = <&cru SRST_MIPIDPHYTX>;
+ reset-names = "apb";
status = "disabled";
};