cpu-map {
cluster0 {
core0 {
- cpu = <&cpu_b0>;
+ cpu = <&cpu_l0>;
};
core1 {
- cpu = <&cpu_b1>;
+ cpu = <&cpu_l1>;
};
core2 {
- cpu = <&cpu_b2>;
+ cpu = <&cpu_l2>;
};
core3 {
- cpu = <&cpu_b3>;
+ cpu = <&cpu_l3>;
};
};
cluster1 {
core0 {
- cpu = <&cpu_l0>;
+ cpu = <&cpu_b0>;
};
core1 {
- cpu = <&cpu_l1>;
+ cpu = <&cpu_b1>;
};
core2 {
- cpu = <&cpu_l2>;
+ cpu = <&cpu_b2>;
};
core3 {
- cpu = <&cpu_l3>;
+ cpu = <&cpu_b3>;
};
};
};
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
};
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1025000 1025000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1125000 1125000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
};
};
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <975000 975000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1050000 1050000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000 1150000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1300000 1300000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cpu_avs: cpu-avs {
+ cluster0-avs {
+ cluster-id = <0>;
+ min-volt = <950000>; /* uV */
+ min-freq = <216000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+ };
+ cluster1-avs {
+ cluster-id = <1>;
+ min-volt = <950000>; /* uV */
+ min-freq = <216000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
};
};
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0x0 0xff500000 0x0 0x100>;
+ reg = <0x0 0xff500000 0x0 0x20000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>;
- clock-names = "usbhost";
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff520000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff520000 0x0 0x20000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
status = "disabled";
};
clocks = <&cru PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox: mailbox@ff6b0000 {
+ compatible = "rockchip,rk3368-mbox-legacy";
+ reg = <0x0 0xff6b0000 0x0 0x1000>,
+ <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox_scpi: mailbox-scpi {
+ compatible = "rockchip,rk3368-scpi-legacy";
+ mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
+ chan-nums = <3>;
+ status = "disabled";
};
pmu: power-management@ff730000 {
grf: syscon@ff770000 {
compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk3368-io-voltage-domain";
status = "disabled";
};
+
+ u2phy: usb2-phy@700 {
+ compatible = "rockchip,rk3368-usb2phy";
+ reg = <0x700 0x2c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usbotg_out";
+ assigned-clocks = <&cru SCLK_USBPHY480M>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
};
wdt: watchdog@ff800000 {
status = "disabled";
};
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vop: vop@ff930000 {
+ compatible = "rockchip,rk3368-vop";
+ reg = <0x0 0xff930000 0x0 0x2fc>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu@ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x100>,
+ <0x0 0xff9a0480 0x0 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
"sclk_gpu_core",
"aclk_gpu_mem",
"aclk_gpu_cfg";
- operating-points = <
- /* KHz uV */
- 200000 1100000
- 288000 1100000
- 400000 1150000
- 576000 1200000
- >;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rogue-g6110-irq";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_opp_table: gpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <1200000>;
+ };
+ };
+
+ efuse: efuse@ffb00000 {
+ compatible = "rockchip,rk3368-efuse";
+ reg = <0x0 0xffb00000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ temp_adjust: temp-adjust@1f {
+ reg = <0x1f 0x1>;
+ };
};
pinctrl: pinctrl {
projects / firefly-linux-kernel-4.4.55.git / blobdiff