#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/display/rk_fb.h>
-#include <dt-bindings/display/mipi_dsi.h>
#include <dt-bindings/power/rk3368-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3368";
#size-cells = <2>;
aliases {
+ ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
- lcdc = &lcdc;
};
cpus {
cpu-map {
cluster0 {
core0 {
- cpu = <&cpu_b0>;
+ cpu = <&cpu_l0>;
};
core1 {
- cpu = <&cpu_b1>;
+ cpu = <&cpu_l1>;
};
core2 {
- cpu = <&cpu_b2>;
+ cpu = <&cpu_l2>;
};
core3 {
- cpu = <&cpu_b3>;
+ cpu = <&cpu_l3>;
};
};
cluster1 {
core0 {
- cpu = <&cpu_l0>;
+ cpu = <&cpu_b0>;
};
core1 {
- cpu = <&cpu_l1>;
+ cpu = <&cpu_b1>;
};
core2 {
- cpu = <&cpu_l2>;
+ cpu = <&cpu_b2>;
};
core3 {
- cpu = <&cpu_l3>;
+ cpu = <&cpu_b3>;
};
};
};
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l1: cpu@1 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
- operating-points-v2 = <&cluster1_opp>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b1: cpu@101 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
- operating-points-v2 = <&cluster0_opp>;
+ operating-points-v2 = <&cluster1_opp>;
};
};
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1025000 1025000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1125000 1125000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
};
};
compatible = "operating-points-v2";
opp-shared;
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
opp@408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
clock-latency-ns = <40000>;
- opp-suspend;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <950000 950000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <975000 975000 1350000>;
+ clock-latency-ns = <40000>;
};
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000>;
+ opp-microvolt = <1050000 1050000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000 1150000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1225000 1225000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1300000 1300000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cpu_avs: cpu-avs {
+ cluster0-avs {
+ cluster-id = <0>;
+ min-volt = <950000>; /* uV */
+ min-freq = <216000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+ };
+ cluster1-avs {
+ cluster-id = <1>;
+ min-volt = <950000>; /* uV */
+ min-freq = <216000>; /* KHz */
+ leakage-adjust-volt = <
+ /* mA mA uV */
+ 0 254 0
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
};
};
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
status = "disabled";
};
+ thermal-zones {
+ cpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <115000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ tsadc: tsadc@ff280000 {
+ compatible = "rockchip,rk3368-tsadc";
+ reg = <0x0 0xff280000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <95000>;
+ status = "disabled";
+ };
+
gmac: ethernet@ff290000 {
compatible = "rockchip,rk3368-gmac";
reg = <0x0 0xff290000 0x0 0x10000>;
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0x0 0xff500000 0x0 0x100>;
+ reg = <0x0 0xff500000 0x0 0x20000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>;
- clock-names = "usbhost";
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff520000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff520000 0x0 0x20000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy>;
+ clock-names = "usbhost", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
status = "disabled";
};
status = "disabled";
};
+ mbox: mbox@ff6b0000 {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox: mailbox@ff6b0000 {
+ compatible = "rockchip,rk3368-mbox-legacy";
+ reg = <0x0 0xff6b0000 0x0 0x1000>,
+ <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox_scpi: mailbox-scpi {
+ compatible = "rockchip,rk3368-scpi-legacy";
+ mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
+ chan-nums = <3>;
+ status = "disabled";
+ };
+
pmu: power-management@ff730000 {
compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff730000 0x0 0x1000>;
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rk3368-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_LOADER>;
-
+ mode-loader = <BOOT_BL_DOWNLOAD>;
};
};
};
grf: syscon@ff770000 {
- compatible = "rockchip,rk3368-grf", "syscon";
+ compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3368-io-voltage-domain";
+ status = "disabled";
+ };
+
+ u2phy: usb2-phy@700 {
+ compatible = "rockchip,rk3368-usb2phy";
+ reg = <0x700 0x2c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usbotg_out";
+ assigned-clocks = <&cru SCLK_USBPHY480M>;
+ assigned-clock-parents = <&u2phy>;
+ status = "disabled";
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
};
wdt: watchdog@ff800000 {
status = "disabled";
};
+ timer@ff810000 {
+ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xff810000 0x0 0x20>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2s_2ch: i2s-2ch@ff890000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff890000 0x0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
+ status = "disabled";
+ };
+
+ i2s_8ch: i2s-8ch@ff898000 {
+ compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_bus>;
+ status = "disabled";
+ };
+
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>,
+ <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vop: vop@ff930000 {
+ compatible = "rockchip,rk3368-vop";
+ reg = <0x0 0xff930000 0x0 0x2fc>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+ reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
+ vop_mmu: iommu@ff930300 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff930300 0x0 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ hevc_mmu: iommu@ff9a0440 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0440 0x0 0x100>,
+ <0x0 0xff9a0480 0x0 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3368_PD_VIDEO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
#address-cells = <0>;
reg = <0x0 0xffb71000 0x0 0x1000>,
- <0x0 0xffb72000 0x0 0x1000>,
+ <0x0 0xffb72000 0x0 0x2000>,
<0x0 0xffb74000 0x0 0x2000>,
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9
"sclk_gpu_core",
"aclk_gpu_mem",
"aclk_gpu_cfg";
- operating-points = <
- /* KHz uV */
- 200000 1100000
- 288000 1100000
- 400000 1150000
- 576000 1200000
- >;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rogue-g6110-irq";
+ operating-points-v2 = <&gpu_opp_table>;
};
- i2s_2ch: i2s-2ch@ff890000 {
- compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff890000 0x0 0x1000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac_bus 6>, <&dmac_bus 7>;
- dma-names = "tx", "rx";
- clock-names = "i2s_clk", "i2s_hclk";
- clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
- status = "disabled";
- };
+ gpu_opp_table: gpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
- i2s_8ch: i2s-8ch@ff898000 {
- compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
- reg = <0x0 0xff898000 0x0 0x1000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac_bus 0>, <&dmac_bus 1>;
- dma-names = "tx", "rx";
- clock-names = "i2s_clk", "i2s_hclk";
- clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s_8ch_bus>;
- status = "disabled";
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@288000000 {
+ opp-hz = /bits/ 64 <288000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <1200000>;
+ };
};
- isp: isp@ff910000 {
- compatible = "rockchip,rk3368-isp", "rockchip,isp";
- reg = <0x0 0xff910000 0x0 0x10000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- /*power-domains = <&power PD_VIO>;*/
- clocks =
- <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
- <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
- <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
- <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
- clock-names =
- "aclk_isp", "hclk_isp", "clk_isp",
- "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
- "clk_cif_pll", "hclk_mipiphy1",
- "pclk_dphyrx", "clk_vio0_noc";
- pinctrl-names =
- "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
- "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
- "isp_mipi_fl_prefl", "isp_flash_as_gpio",
- "isp_flash_as_trigger_out";
- pinctrl-0 = <&cif_clkout>;
- pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
- pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
- pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
- pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
- pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
- pinctrl-6 = <&cif_clkout>;
- pinctrl-7 = <&cif_clkout &isp_prelight>;
- pinctrl-8 = <&isp_flash_trigger_as_gpio>;
- pinctrl-9 = <&isp_flash_trigger>;
- rockchip,isp,mipiphy = <2>;
- rockchip,isp,cifphy = <1>;
- rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
- rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
- rockchip,grf = <&grf>;
- rockchip,cru = <&cru>;
- rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- rockchip,isp,iommu_enable = <1>;
- status = "disabled";
- };
+ efuse: efuse@ffb00000 {
+ compatible = "rockchip,rk3368-efuse";
+ reg = <0x0 0xffb00000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
- rga: rga@ff920000 {
- compatible = "rockchip,rga2";
- dev_mode = <1>;
- reg = <0x0 0xff920000 0x0 0x1000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
- clock-names = "aclk_rga", "hclk_rga", "clk_rga";
- status = "disabled";
+ /* Data cells */
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ temp_adjust: temp-adjust@1f {
+ reg = <0x1f 0x1>;
+ };
};
pinctrl: pinctrl {
};
};
- hdmi_i2c {
- hdmii2c_xfer: hdmii2c-xfer {
- rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
- <3 27 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- hdmi_pin {
- hdmi_cec: hdmi-cec {
- rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
<3 27 RK_FUNC_2 &pcfg_pull_none>;
};
- i2c5_gpio: i2c5-gpio {
- rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
- <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
i2s {
};
};
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ vop_pwm_pin: vop-pwm {
+ rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
};
- sdmmc_cd: sdmcc-cd {
+ sdmmc_cd: sdmmc-cd {
rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
};
};
};
+ tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
};
};
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- vop_pwm_pin: vop-pwm {
- rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- pwm3_pin: pwm3-pin {
- rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
-
- lcdc {
- lcdc_lcdc: lcdc-lcdc {
- rockchip,pins =
- <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
- <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
- <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
- <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
- <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
- <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
- <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
- <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
- <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
- <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
- <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
- <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
- <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
- <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
- <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
- <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
- <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
- <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
- };
-
- lcdc_gpio: lcdc-gpio {
- rockchip,pins =
- <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
- <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
- <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
- <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
- <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
- <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
- <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
- <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
- <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
- <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
- <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
- <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
- <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
- <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
- <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
- <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
- <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
- <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
- };
- };
-
- isp {
- cif_clkout: cif-clkout {
- rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
- };
-
- isp_dvp_d2d9: isp-dvp-d2d9 {
- rockchip,pins =
- <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
- <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
- <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
- <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
- <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
- <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
- <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
- <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
- <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
- <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
- <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
- <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
- };
-
- isp_dvp_d0d1: isp-dvp-d0d1 {
- rockchip,pins =
- <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
- <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
- };
-
- isp_dvp_d10d11:isp_d10d11 {
- rockchip,pins =
- <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
- <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
- };
-
- isp_dvp_d0d7: isp-dvp-d0d7 {
- rockchip,pins =
- <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
- <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
- <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
- <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
- <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
- <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
- <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
- <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
- };
-
- isp_dvp_d4d11: isp-dvp-d4d11 {
- rockchip,pins =
- <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
- <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
- <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
- <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
- <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
- <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
- <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
- <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
- };
-
- isp_shutter: isp-shutter {
- rockchip,pins =
- <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
- <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
- };
-
- isp_flash_trigger: isp-flash-trigger {
- rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
- };
-
- isp_prelight: isp-prelight {
- rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
- };
-
- isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
- rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
- };
- };
- };
-
- fb: fb {
- compatible = "rockchip,rk-fb";
- rockchip,disp-mode = <NO_DUAL>;
- status = "disabled";
- };
-
- rk_screen: screen {
- compatible = "rockchip,screen";
- status = "disabled";
- };
-
- lcdc: lcdc@ff930000 {
- compatible = "rockchip,rk3368-lcdc";
- rockchip,grf = <&grf>;
- rockchip,pmugrf = <&pmugrf>;
- rockchip,cru = <&cru>;
- rockchip,prop = <PRMRY>;
- rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- reg = <0x0 0xff930000 0x0 0x10000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- /*power-domains = <&power PD_VIO>;*/
- resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
- reset-names = "axi", "ahb", "dclk";
- status = "disabled";
- };
-
- mipi: mipi@ff960000 {
- compatible = "rockchip,rk3368-dsi";
- rockchip,prop = <0>;
- reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
- reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
- /*power-domains = <&power PD_VIO>;*/
- status = "disabled";
- };
-
- lvds: lvds@ff968000 {
- compatible = "rockchip,rk3368-lvds";
- rockchip,grf = <&grf>;
- reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
- reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
- clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
- clock-names = "pclk_lvds", "pclk_lvds_ctl";
- /*power-domains = <&power PD_VIO>;*/
- status = "disabled";
- };
-
- edp: edp@ff970000 {
- compatible = "rockchip,rk32-edp";
- reg = <0x0 0xff970000 0x0 0x4000>;
- rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
- /*power-domains = <&power PD_VIO>;*/
- resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
- reset-names = "edp_24m", "edp_apb";
- status = "disabled";
- };
-
- hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3368-hdmi";
- reg = <0x0 0xff980000 0x0 0x20000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>,
- <&cru SCLK_HDMI_HDCP>,
- <&cru SCLK_HDMI_CEC>;
- clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
- /*power-domains = <&power PD_VIO>;*/
- resets = <&cru SRST_HDMI>;
- reset-names = "hdmi";
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
- pinctrl-1 = <&i2c5_gpio>;
- status = "disabled";
- };
-
- iep_mmu: iep-mmu {
- dbgname = "iep";
- compatible = "rockchip,iep_mmu";
- reg = <0x0 0xff900800 0x0 0x100>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
- status = "disabled";
- };
-
- vip_mmu: vip-mmu {
- dbgname = "vip";
- compatible = "rockchip,vip_mmu";
- reg = <0x0 0xff950800 0x0 0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vip_mmu";
- status = "disabled";
- };
-
- vopb_mmu: vopb-mmu {
- dbgname = "vop";
- compatible = "rockchip,vopb_mmu";
- reg = <0x0 0xff930300 0x0 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
- status = "disabled";
- };
-
- isp_mmu: isp-mmu {
- dbgname = "isp_mmu";
- compatible = "rockchip,isp_mmu";
- reg = <0x0 0xff914000 0x0 0x100>,
- <0x0 0xff915000 0x0 0x100>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_mmu";
- status = "disabled";
- };
-
- hdcp_mmu: hdcp-mmu {
- dbgname = "hdcp_mmu";
- compatible = "rockchip,hdcp_mmu";
- reg = <0x0 0xff940000 0x0 0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hdcp_mmu";
- status = "disabled";
- };
-
- hevc_mmu: hevc-mmu {
- dbgname = "hevc";
- compatible = "rockchip,hevc_mmu";
- reg = <0x0 0xff9a0440 0x0 0x40>,
- <0x0 0xff9a0480 0x0 0x40>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hevc_mmu";
- status = "disabled";
- };
-
- vpu_mmu: vpu-mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x0 0xff9a0800 0x0 0x100>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vepu_mmu", "vdpu_mmu";
- status = "disabled";
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff