arm64: dts: rk3368-android: enable iep default

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3368-android.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
index b60df08aba508321c298392eab13b105fb363803..a654d095d67b4f807e88d18bf7a042dfd54c1825 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
@@ -42,18 +42,18 @@
 
 / {
        chosen {
-               bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
+               bootargs = "earlycon=uart8250,mmio32,0xff1b0000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
        };
 
        fiq_debugger: fiq-debugger {
                compatible = "rockchip,fiq-debugger";
-               rockchip,serial-id = <2>;
+               rockchip,serial-id = <3>;
                rockchip,signal-irq = <186>;
                rockchip,wake-irq = <0>;
                rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
                rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
                pinctrl-names = "default";
-               pinctrl-0 = <&uart2_xfer>;
+               pinctrl-0 = <&uart3_xfer>;
        };
 
        reserved-memory {
@@ -73,12 +73,6 @@
                        size = <0x0 0x8000000>;
                        linux,cma-default;
                };
-
-               /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
-               rockchip_logo: rockchip-logo@00000000 {
-                       compatible = "rockchip,drm-logo";
-                       reg = <0x0 0x0 0x0 0x0>;
-               };
        };
 
        ion {
@@ -94,47 +88,6 @@
                };
        };
 
-       isp: isp@ff910000 {
-               compatible = "rockchip,rk3368-isp", "rockchip,isp";
-               reg = <0x0 0xff910000 0x0 0x10000>;
-               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-               power-domains = <&power RK3368_PD_VIO>;
-               clocks =
-                       <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
-                       <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
-                       <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
-                       <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
-               clock-names =
-                       "aclk_isp", "hclk_isp", "clk_isp",
-                       "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
-                       "clk_cif_pll", "hclk_mipiphy1",
-                       "pclk_dphyrx", "clk_vio0_noc";
-               pinctrl-names =
-                       "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
-                       "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
-                       "isp_mipi_fl_prefl", "isp_flash_as_gpio",
-                       "isp_flash_as_trigger_out";
-               pinctrl-0 = <&cif_clkout>;
-               pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
-               pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
-               pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
-               pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
-               pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
-               pinctrl-6 = <&cif_clkout>;
-               pinctrl-7 = <&cif_clkout &isp_prelight>;
-               pinctrl-8 = <&isp_flash_trigger_as_gpio>;
-               pinctrl-9 = <&isp_flash_trigger>;
-               rockchip,isp,mipiphy = <2>;
-               rockchip,isp,cifphy = <1>;
-               rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
-               rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
-               rockchip,grf = <&grf>;
-               rockchip,cru = <&cru>;
-               rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
-               rockchip,isp,iommu_enable = <1>;
-               status = "disabled";
-       };
-
        rga@ff920000 {
                compatible = "rockchip,rga2";
                dev_mode = <1>;
@@ -160,7 +113,7 @@
                pinctrl-names = "default", "gpio";
                pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
                pinctrl-1 = <&i2c5_gpio>;
-               status = "okay";
+               status = "disabled";
        };
 
        dwc_control_usb: dwc-control-usb {
@@ -213,9 +166,42 @@
                        charge_logo,mode = "center";
                        connect = <&vop_out_mipi>;
                };
+
+               route_edp: route-edp {
+                       status = "disabled";
+                       logo,uboot = "logo.bmp";
+                       logo,kernel = "logo_kernel.bmp";
+                       logo,mode = "center";
+                       charge_logo,mode = "center";
+                       connect = <&vop_out_edp>;
+               };
        };
 };
 
+&uart3 {
+       status = "okay";
+};
+
+&iep {
+       status = "okay";
+};
+
+&iep_mmu {
+       status = "okay";
+};
+
+&vpu_combo {
+       status = "okay";
+};
+
+&vpu_mmu {
+       status = "okay";
+};
+
+&hevc_mmu {
+       status = "okay";
+};
+
 &vop {
        status = "okay";
 };
@@ -224,6 +210,14 @@
        status = "okay";
 };
 
+&isp {
+       status = "okay";
+};
+
+&isp_mmu {
+       status = "okay";
+};
+
 &usb_otg {
        status = "okay";
        clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;