#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/rk_fb.h>
+#include <dt-bindings/power/rk3366-power.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
/ {
compatible = "rockchip,rk3366";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1200000>;
};
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <
- GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
xin24m: xin24m {
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
- <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
status = "disabled";
};
+ usb_host0_echi: usb@ff480000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff480000 0x0 0x20000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+ clock-names = "sclk_otgphy0", "hclk_host0";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff4a0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff4a0000 0x0 0x20000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+ clock-names = "sclk_otgphy0", "hclk_host0";
+ status = "disabled";
+ };
+
+ usb_otg: usb@ff4c0000 {
+ compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff4c0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
+ g-use-dma;
+ status = "disabled";
+ };
+
i2c1: i2c@ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
status = "disabled";
};
+ pmu: power-management@ff730000 {
+ compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff730000 0x0 0x1000>;
+
+ power: power-controller {
+ status = "disabled";
+ compatible = "rockchip,rk3366-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Note: Although SCLK_* are the working clocks
+ * of device without including on the NOC, needed for
+ * synchronous reset.
+ *
+ * The clocks on the which NOC:
+ * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+ * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
+ * ACLK_ISP is on ACLK_ISP_NIU.
+ * ACLK_HDCP is on ACLK_HDCP_NIU.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ *
+ * Which clock are device clocks:
+ * clocks devices
+ * *_IEP IEP:Image Enhancement Processor
+ * *_ISP ISP:Image Signal Processing
+ * *_VOP* VOP:Visual Output Processor
+ * *_RGA RGA
+ * *_DPHY* LVDS
+ * *_HDMI HDMI
+ * *_MIPI_* MIPI
+ */
+ pd_vio {
+ reg = <RK3366_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_HDCP>,
+ <&cru ACLK_VOP_FULL>,
+ <&cru ACLK_VOP_LITE>,
+ <&cru ACLK_VOP_IEP>,
+ <&cru DCLK_VOP_FULL>,
+ <&cru DCLK_VOP_LITE>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VOP_FULL>,
+ <&cru HCLK_VOP_LITE>,
+ <&cru HCLK_VIO_HDCPMMU>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_HDCP>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_VOP_FULL_PWM>,
+ <&cru SCLK_HDCP>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>,
+ <&cru SCLK_HDMI_CEC>,
+ <&cru SCLK_HDMI_HDCP>;
+ };
+
+ /*
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+ * (video endecoder & decoder) clocks that on the
+ * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ */
+ pd_vpu {
+ reg = <RK3366_PD_VPU>;
+ clocks = <&cru ACLK_VIDEO>,
+ <&cru HCLK_VIDEO>;
+ };
+
+ /*
+ * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
+ * (video decoder) clocks that on the
+ * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
+ */
+ pd_rkvdec {
+ reg = <RK3366_PD_RKVDEC>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>;
+ };
+
+ pd_video {
+ reg = <RK3366_PD_VIDEO>;
+ clocks = <&cru ACLK_VIDEO>,
+ <&cru ACLK_RKVDEC>,
+ <&cru HCLK_VIDEO>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ };
+
+ /*
+ * Note: ACLK_GPU is the GPU clock,
+ * and on the ACLK_GPU_NIU (NOC).
+ */
+ pd_gpu {
+ reg = <RK3366_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+ };
+
pmugrf: syscon@ff738000 {
- compatible = "rockchip,rk3366-pmugrf", "syscon";
+ compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_LOADER>;
+ };
};
amba {
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks =
+ <&cru PLL_CPLL>, <&cru PLL_GPLL>,
+ <&cru PLL_NPLL>, <&cru PLL_MPLL>,
+ <&cru PLL_WPLL>, <&cru PLL_BPLL>,
+ <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
+ <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
+ assigned-clock-rates =
+ <750000000>, <576000000>,
+ <594000000>, <594000000>,
+ <480000000>, <520000000>,
+ <375000000>, <288000000>,
+ <100000000>, <100000000>;
};
grf: syscon@ff770000 {
reg = <0x0 0xff770000 0x0 0x1000>;
};
+ wdt: watchdog@ff800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xff800000 0x0 0x100>;
+ clocks = <&cru PCLK_WDT>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spdif: spdif@ff880000 {
+ compatible = "rockchip,rk3366-spdif";
+ reg = <0x0 0xff880000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 3>;
+ dma-names = "tx";
+ clock-names = "hclk", "mclk";
+ clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_bus>;
+ status = "disabled";
+ };
+
+ i2s_2ch: i2s-2ch@ff890000 {
+ compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff890000 0x0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+ status = "disabled";
+ };
+
+ i2s_8ch: i2s-8ch@ff898000 {
+ compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff898000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_bus>;
+ status = "disabled";
+ };
+
fb: fb {
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <DUAL>;
status = "disabled";
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rga2";
+ dev_mode = <1>;
+ reg = <0x0 0xff920000 0x0 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+ status = "disabled";
+ };
+
vop_big: vop@ff930000 {
compatible = "rockchip,rk3366-lcdc-big";
rockchip,grf = <&grf>;
<5 15 RK_FUNC_2 &pcfg_pull_none>,
<5 16 RK_FUNC_2 &pcfg_pull_none>;
};
+
+ i2c2_gpio: i2c2-gpio {
+ rockchip,pins =
+ <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
+ <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
i2c3 {
<5 8 RK_FUNC_1 &pcfg_pull_none>,
<5 9 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ i2c4_gpio: i2c4-gpio {
+ rockchip,pins =
+ <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
+ <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
i2c5 {
};
};
+ spdif {
+ spdif_bus: spdif-bus {
+ rockchip,pins =
+ <5 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
/* mac_rxd2 */
<2 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
- <2 5 RK_FUNC_1 &pcfg_pull_none>,
+ <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd2 */
- <2 4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_rxd1 */
<2 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<2 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
- <2 1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd0 */
<2 0 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txclkout */
+ <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_crs */
/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxclkin */
/* mac_mdio */
<2 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
- <2 12 RK_FUNC_1 &pcfg_pull_none>,
+ <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_clk */
<2 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
eth_phy {
eth_phy_pwr: eth-phy-pwr {
rockchip,pins =
- <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff