arm64: dts: rockchip: add efuse device node for rk3328

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index ba0e1b75d18c715d8b1eb021d6d80664396a1de9..fd76037e75c4b9a8e5fc44456647a569bb74359a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -532,6 +532,27 @@
                };
        };
 
+       efuse: efuse@ff260000 {
+               compatible = "rockchip,rk3328-efuse";
+               reg = <0x0 0xff260000 0x0 0x50>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               clocks = <&cru SCLK_EFUSE>;
+               clock-names = "pclk_efuse";
+               rockchip,efuse-size = <0x20>;
+
+               /* Data cells */
+               efuse_id: id@7 {
+                       reg = <0x07 0x10>;
+               };
+               cpu_leakage: cpu-leakage@17 {
+                       reg = <0x17 0x1>;
+               };
+               logic_leakage: logic-leakage@19 {
+                       reg = <0x19 0x1>;
+               };
+       };
+
        saradc: saradc@ff280000 {
                compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
                reg = <0x0 0xff280000 0x0 0x100>;
@@ -544,6 +565,52 @@
                status = "disabled";
        };
 
+       gpu: gpu@ff300000 {
+               compatible = "arm,mali-450";
+               /* first item of 'reg' is dummy, to fit src code. */
+               reg = <0x0 0xff300000 0x0 0x40000>,
+                     <0x0 0xff300000 0x0 0x40000>;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "Mali_GP_IRQ",
+                                 "Mali_GP_MMU_IRQ",
+                                 "IRQPP",
+                                 "Mali_PP0_IRQ",
+                                 "Mali_PP0_MMU_IRQ",
+                                 "Mali_PP1_IRQ",
+                                 "Mali_PP1_MMU_IRQ";
+               clocks = <&cru ACLK_GPU>;
+               clock-names = "clk_mali";
+               operating-points-v2 = <&gpu_opp_table>;
+               status = "disabled";
+       };
+
+       gpu_opp_table: opp-table2 {
+               compatible = "operating-points-v2";
+
+               opp@200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp@500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <1100000>;
+               };
+       };
+
        vop: vop@ff370000 {
                compatible = "rockchip,rk3328-vop";
                reg = <0x0 0xff370000 0x0 0x3efc>;
@@ -1548,8 +1615,8 @@
 
                        sdmmc1_bus4: sdmmc1-bus4 {
                                rockchip,pins =
-                                       <1 RK_PB4 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                                       <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                                       <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                                       <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
                                        <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
                                        <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
                        };