status = "disabled";
};
+ pdm: pdm@ff040000 {
+ compatible = "rockchip,pdm";
+ reg = <0x0 0xff040000 0x0 0x1000>;
+ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 16>;
+ #dma-cells = <1>;
+ dma-names = "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_fsync
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-1 = <&pdmm0_sleep>;
+ status = "disabled";
+ };
+
grf: syscon@ff100000 {
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
};
};
+ efuse: efuse@ff260000 {
+ compatible = "rockchip,rk3328-efuse";
+ reg = <0x0 0xff260000 0x0 0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru SCLK_EFUSE>;
+ clock-names = "pclk_efuse";
+ rockchip,efuse-size = <0x20>;
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ logic_leakage: logic-leakage@19 {
+ reg = <0x19 0x1>;
+ };
+ };
+
saradc: saradc@ff280000 {
- compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
+ compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
status = "disabled";
};
+ gpu: gpu@ff300000 {
+ compatible = "arm,mali-450";
+ /* first item of 'reg' is dummy, to fit src code. */
+ reg = <0x0 0xff300000 0x0 0x40000>,
+ <0x0 0xff300000 0x0 0x40000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "Mali_GP_IRQ",
+ "Mali_GP_MMU_IRQ",
+ "IRQPP",
+ "Mali_PP0_IRQ",
+ "Mali_PP0_MMU_IRQ",
+ "Mali_PP1_IRQ",
+ "Mali_PP1_MMU_IRQ";
+ clocks = <&cru ACLK_GPU>;
+ clock-names = "clk_mali";
+ operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+
vop: vop@ff370000 {
compatible = "rockchip,rk3328-vop";
reg = <0x0 0xff370000 0x0 0x3efc>;
};
};
+ pdm-0 {
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins =
+ <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_fsync: pdmm0-fsync {
+ rockchip,pins =
+ <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins =
+ <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins =
+ <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins =
+ <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins =
+ <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sleep: pdmm0-sleep {
+ rockchip,pins =
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
i2s1 {
i2s1_mclk: i2s1-mclk {
rockchip,pins =
sdmmc1_bus4: sdmmc1-bus4 {
rockchip,pins =
- <1 RK_PB4 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>,
+ <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
+ <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
<1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
<1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
};
};
};
- gmac-0 {
- rgmiim0_pins: rgmiim0-pins {
- rockchip,pins =
- /* mac_txclk */
- <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_rxclk */
- <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdio */
- <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txen */
- <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_clk */
- <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxdv */
- <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdc */
- <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd1 */
- <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_rxd3 */
- <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd2 */
- <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd3 */
- <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd2 */
- <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none_12ma>;
- };
-
- rmiim0_pins: rmiim0-pins {
- rockchip,pins =
- /* mac_mdio */
- <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txen */
- <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_clk */
- <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxer */
- <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxdv */
- <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_mdc */
- <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd1 */
- <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_rxd0 */
- <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
- /* mac_txd1 */
- <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none_12ma>;
- };
- };
-
gmac-1 {
rgmiim1_pins: rgmiim1-pins {
rockchip,pins =