#address-cells = <2>;
#size-cells = <0>;
- big0: cpu@100 {
+ idle-states {
+ entry-method = "arm,psci";
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <0x3fffffff>;
+ exit-latency-us = <0x40000000>;
+ min-residency-us = <0xffffffff>;
+ };
+ };
+
+ little0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x100>;
+ reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- big1: cpu@101 {
+ little1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x101>;
+ reg = <0x0 0x1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- big2: cpu@102 {
+ little2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x102>;
+ reg = <0x0 0x2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- big3: cpu@103 {
+ little3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x103>;
+ reg = <0x0 0x3>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- little0: cpu@0 {
+ big0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x0>;
+ reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- little1: cpu@1 {
+ big1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x1>;
+ reg = <0x0 0x101>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- little2: cpu@2 {
+ big2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x2>;
+ reg = <0x0 0x102>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- little3: cpu@3 {
+ big3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x3>;
+ reg = <0x0 0x103>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu-map {
};
psci {
- compatible = "arm,psci";
+ compatible = "arm,psci-0.2";
method = "smc";
- cpu_on = <0xC4000003>;
};
gic: interrupt-controller@ffb70000 {
<0x0 0xffb72000 0 0x1000>;
};
- pmu_grf: syscon@ff738000 {
- compatible = "rockchip,rk3388-pmu-grf", "syscon";
- reg = <0x0 0xff738000 0x0 0x100>;
+ ddrpctl: syscon@ff610000 {
+ compatible = "rockchip,rk3368-ddrpctl", "syscon";
+ reg = <0x0 0xff610000 0x0 0x400>;
+ };
+
+ pmu: syscon@ff730000 {
+ compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
+ reg = <0x0 0xff730000 0x0 0x1000>;
+ };
+
+ pmugrf: syscon@ff738000 {
+ compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
+ reg = <0x0 0xff738000 0x0 0x1000>;
};
sgrf: syscon@ff740000 {
- compatible = "rockchip,rk3388-sgrf", "syscon";
+ compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
reg = <0x0 0xff740000 0x0 0x1000>;
};
+ cru: syscon@ff760000 {
+ compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
+ reg = <0x0 0xff760000 0x0 0x1000>;
+ };
+
grf: syscon@ff770000 {
- compatible = "rockchip,rk3388-grf", "syscon";
+ compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
reg = <0x0 0xff770000 0x0 0x1000>;
};
+ msch: syscon@ffac0000 {
+ compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x3000>;
+ };
+
arm-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
crypto {
reg = <0x0 0xffa80080 0x0 0x20>;
};
+ tsp {
+ reg = <0x0 0xffa80280 0x0 0x20>;
+ };
bus_cpup {
reg = <0x0 0xffa90000 0x0 0x20>;
};
};
peri {
reg = <0x0 0xffab0000 0x0 0x20>;
+ rockchip,priority = <2 2>;
};
iep {
reg = <0x0 0xffad0000 0x0 0x20>;
reg = <0x0 0xffae0000 0x0 0x20>;
};
vpu_r {
- reg = <0x0 0xffae0080 0x0 0x20>;
+ reg = <0x0 0xffae0100 0x0 0x20>;
};
vpu_w {
- reg = <0x0 0xffae0100 0x0 0x20>;
+ reg = <0x0 0xffae0180 0x0 0x20>;
+ };
+ gpu {
+ reg = <0x0 0xffaf0000 0x0 0x20>;
};
};
sram: sram@ff8c0000 {
compatible = "mmio-sram";
- reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
+ reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
map-exec;
};
pdma0: pdma@ff600000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff600000 0x0 0x4000>;
+ clocks = <&clk_gates12 11>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
+
};
pdma1: pdma@ff250000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff250000 0x0 0x4000>;
+ clocks = <&clk_gates19 3>;
+ clock-names = "apb_pclk";
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
emmc: rksdmmc@ff0f0000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
+ compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clk_emmc>, <&clk_gates21 2>;
- clock-names = "clk_mmc", "hclk_mmc";
+ clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
+ clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
+ rockchip,grf = <&grf>;
num-slots = <1>;
fifo-depth = <0x100>;
bus-width = <8>;
};
sdmmc: rksdmmc@ff0c0000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
+ compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "idle";
+ pinctrl-names = "default", "idle", "udbg";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
pinctrl-1 = <&sdmmc_gpio>;
+ pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
- clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
- clock-names = "clk_mmc", "hclk_mmc";
+ clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
+ clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
+ rockchip,grf = <&grf>;
num-slots = <1>;
fifo-depth = <0x100>;
bus-width = <4>;
};
sdio: rksdmmc@ff0d0000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
+ compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
reg = <0x0 0xff0d0000 0x0 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
pinctrl-names = "default","idle";
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
pinctrl-1 = <&sdio0_gpio>;
- clocks = <&clk_sdio0>, <&clk_gates21 1>;
- clock-names = "clk_mmc", "hclk_mmc";
+ clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
+ clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
+ rockchip,grf = <&grf>;
num-slots = <1>;
fifo-depth = <0x100>;
bus-width = <4>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+ pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
rockchip,spi-src-clk = <1>;
- num-cs = <1>;
+ num-cs = <2>;
clocks = <&clk_spi1>, <&clk_gates19 5>;
clock-names = "spi", "pclk_spi1";
//dmas = <&pdma1 13>, <&pdma1 14>;
status = "disabled";
};
+ mbox: mbox@ff6b0000 {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b0000 0x0 0x1000>,
+ <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates12 1>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ };
+
+ mbox_scpi: mbox-scpi {
+ compatible = "rockchip,mbox-scpi";
+ mboxes = <&mbox 0 &mbox 1>;
+ };
+
+ ddr {
+ compatible = "rockchip,rk3368-ddr";
+ status = "okay";
+ rockchip,ddrpctl = <&ddrpctl>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&msch>;
+ };
+
rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
<&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
<&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
- <&clk_cs &clk_gpll>;
+ <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
rockchip,clocks-init-rate =
<&clk_gpll 576000000>, <&clk_core_b 792000000>,
<&clk_core_l 600000000>, <&clk_cpll 400000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
<&clk_cs 300000000>, <&clkin_trace 300000000>,
- <&aclk_cci 600000000>, <&clk_mac 50000000>,
+ <&aclk_cci 600000000>, <&clk_mac 125000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
rockchip_clocks_enable: clocks-enable {
compatible = "rockchip,clocks-enable";
clocks =
+ <&pd_vio>,
+ <&pd_video>,
+ <&pd_gpu_0>,
+ <&pd_gpu_1>,
+
/*PLL*/
<&clk_apllb>,
<&clk_aplll>,
/*PD_CORE*/
<&clk_cs>,
<&clkin_trace>,
+ <&aclk_cci>,
/*PD_BUS*/
<&aclk_bus>,
<&clk_gates12 5>,/*aclk_intmem0*/
<&clk_gates12 4>,/*aclk_intmem*/
<&clk_gates13 9>,/*aclk_gic400*/
+ <&clk_gates12 9>,/*hclk_rom*/
/*PD_ALIVE*/
<&clk_gates22 13>,/*pclk_timer1*/
<&clk_gates21 4>,/*aclk_peri_mmu*/
<&clk_gates19 0>,/*hclk_peri_axi_matrix*/
<&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
- <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
+ <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
+
+ <&fclk_mcu>,
+ <&stclk_mcu>,
+ <&clk_gates7 0>;/*clk_jtag*/
};
/* I2C_PMU */
};
dsihost0: mipi@ff960000{
- compatible = "rockchip,rk33x-dsi";
+ compatible = "rockchip,rk3368-dsi";
rockchip,prop = <0>;
- reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
+ reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
- status = "okay";
+ clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
+ status = "disabled";
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
rockchip,grf = <&grf>;
- reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
+ reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
- clocks = <&clk_gates22 10>, <&clk_gates17 3>;
- clock-names = "pclk_lvds", "pclk_lvds_ctl";
+ clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
+ clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
status = "disabled";
};
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3368-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
+ rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
lcdc: lcdc@ff930000 {
compatible = "rockchip,rk3368-lcdc";
rockchip,grf = <&grf>;
- rockchip,pmu = <&pmu_grf>;
+ rockchip,pmugrf = <&pmugrf>;
+ rockchip,cru = <&cru>;
rockchip,prop = <PRMRY>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <0>;
*pinctrl-1 = <&lcdc_gpio>;
*/
status = "disabled";
- clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
+ clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
+ clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
};
adc: adc@ff100000 {
status = "disabled";
};
+ remotectl: pwm@ff680030 {
+ compatible = "rockchip,remotectl-pwm";
+ reg = <0x0 0xff680030 0x0 0x50>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&clk_gates13 6>;
+ clock-names = "pclk_pwm";
+ dmas = <&pdma0 2>;
+ #dma-cells = <2>;
+ dma-names = "rx";
+ remote_pwm_id = <3>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
voppwm: pwm@ff9301a0 {
compatible = "rockchip,vop-pwm";
reg = <0x0 0xff9301a0 0x0 0x10>;
status = "disabled";
};
+ pvtm {
+ compatible = "rockchip,rk3368-pvtm";
+ rockchip,grf = <&grf>;
+ rockchip,pmugrf = <&pmugrf>;
+ rockchip,pvtm-clk-out = <1>;
+ };
+
+ cpufreq {
+ compatible = "rockchip,rk3368-cpufreq";
+ rockchip,grf = <&grf>;
+ };
+
dvfs {
vd_arm: vd_arm {
regulator_name = "vdd_arm";
suspend_volt = <1000>; //mV
pd_core {
- clk_core_dvfs_table: clk_core {
+ clk_core_b_dvfs_table: clk_core_b {
operating-points = <
/* KHz uV */
- 312000 1100000
- 504000 1100000
- 816000 1100000
- 1008000 1100000
+ 312000 1200000
+ 504000 1200000
+ 816000 1200000
+ 1008000 1200000
>;
- channel = <0>;
- temp-limit-enable = <0>;
+ status = "okay";
+ temp-limit-enable = <1>;
target-temp = <80>;
+ min_temp_limit = <216>;
normal-temp-limit = <
/*delta-temp delta-freq*/
3 96000
/*temp freq*/
100 816000
>;
+ };
+ clk_core_l_dvfs_table: clk_core_l {
+ operating-points = <
+ /* KHz uV */
+ 312000 1200000
+ 504000 1200000
+ 816000 1200000
+ 1008000 1200000
+ >;
status = "okay";
- regu-mode-table = <
- /*freq mode*/
- 1008000 4
- 0 3
- >;
- regu-mode-en = <0>;
+ temp-limit-enable = <1>;
+ target-temp = <80>;
+ min_temp_limit = <216>;
+ normal-temp-limit = <
+ /*delta-temp delta-freq*/
+ 3 96000
+ 6 144000
+ 9 192000
+ 15 384000
+ >;
+ performance-temp-limit = <
+ /*temp freq*/
+ 100 816000
+ >;
};
};
};
};
};
- pd_vio {
- aclk_vio1_dvfs_table: aclk_vio1 {
- operating-points = <
- /* KHz uV */
- 100000 1100000
- 500000 1100000
- >;
- status = "okay";
- };
- };
- };
-
- vd_gpu: vd_gpu {
- regulator_name = "vdd_gpu";
- suspend_volt = <1000>; //mV
pd_gpu {
clk_gpu_dvfs_table: clk_gpu {
operating-points = <
#address-cells = <1>;
#size-cells = <0>;
- ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
+ ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <1>;
- reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
+ rockchip,ion_heap = <4>;
+ reg = <0x00000000 0x08000000>; /* 512MB */
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
+ rockchip,ion-heap@0 { /* VMALLOC HEAP */
compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <3>;
+ rockchip,ion_heap = <0>;
};
};
- vpu: vpu_service@ff9a0000 {
- compatible = "vpu_service";
+ vpu: vpu_service {
+ compatible = "rockchip,vpu_sub";
iommu_enabled = <0>;
- reg = <0x0 0xff9a0000 0x0 0x800>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
- /*
- clocks = <&clk_vdpu>, <&hclk_vdpu>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- */
+ dev_mode = <0>;
name = "vpu_service";
- /* status = "disabled"; */
+ };
+
+ hevc: hevc_service {
+ compatible = "rockchip,hevc_sub";
+ iommu_enabled = <0>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ dev_mode = <1>;
+ name = "hevc_service";
+ };
+
+ vpu_combo: vpu_combo@ff9a0000 {
+ compatible = "rockchip,vpu_combo";
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ rockchip,grf = <&grf>;
+ subcnt = <2>;
+ rockchip,sub = <&vpu>, <&hevc>;
+ clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
+ mode_bit = <12>;
+ mode_ctrl = <0x418>;
+ name = "vpu_combo";
+ status = "okay";
};
iep: iep@ff900000 {
iommu_enabled = <0>;
reg = <0x0 0xff900000 0x0 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates15 2>, <&clk_gates15 3>;
+ clocks = <&clk_gates16 2>, <&clk_gates16 3>;
clock-names = "aclk_iep", "hclk_iep";
status = "okay";
};
gmac: eth@ff290000 {
compatible = "rockchip,rk3368-gmac";
reg = <0x0 0xff290000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
interrupt-names = "macirq";
- clocks = <&clk_mac>, <&clk_gates5 0>,
- <&clk_gates5 1>, <&clk_gates5 2>,
- <&clk_gates5 3>, <&clk_gates8 0>,
- <&clk_gates8 1>;
+ clocks = <&clk_mac>, <&clk_gates7 4>,
+ <&clk_gates7 5>, <&clk_gates7 6>,
+ <&clk_gates7 7>, <&clk_gates20 13>,
+ <&clk_gates20 14>;
clock-names = "clk_mac", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
phy-mode = "rgmii";
pinctrl-names = "default";
- pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
+ pinctrl-0 = <&rgmii_pins>;
+ status = "disabled";
};
gpu {
vop_mmu {
dbgname = "vop";
- compatible = "rockchip,vop_mmu";
+ compatible = "rockchip,vopb_mmu";
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
hevc_mmu {
dbgname = "hevc";
compatible = "rockchip,hevc_mmu";
- reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
- <0x0 0xff9c0480 0x0 0x40>;
+ reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
+ <0x0 0xff9a0480 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
interrupt-names = "hevc_mmu";
};
compatible = "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
- clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
+ clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
pinctrl-0 = <&cif_clkout>;
pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
rockchip,isp,mipiphy = <2>;
rockchip,isp,cifphy = <1>;
rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
+ rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
- rockchip,isp,iommu_enable = <1>;
+ rockchip,isp,iommu_enable = <0>;
+ status = "okay";
+ };
+
+ cif: cif@ff950000 {
+ compatible = "rockchip,cif";
+ reg = <0x0 0xff950000 0x0 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
+ clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
+ clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
+ pinctrl-names = "cif_pin_all";
+ pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
status = "okay";
};
+/*
+ thermal-zones {
+ #include "rk3368-thermal.dtsi"
+ };
+*/
+
tsadc: tsadc@ff280000 {
- compatible = "rockchip,tsadc";
+ compatible = "rockchip,rk3368-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- clock-frequency = <10000>;
clocks = <&clk_tsadc>, <&clk_gates20 0>;
- clock-names = "tsadc", "pclk_tsadc";
- pinctrl-names = "default", "tsadc_int";
- pinctrl-0 = <&tsadc_gpio>;
- pinctrl-1 = <&tsadc_int>;
- tsadc-ht-temp = <120>;
- tsadc-ht-reset-cru = <1>;
- tsadc-ht-pull-gpio = <0>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,pmu = <&pmu>;
+ clock-names = "tsadc", "apb_pclk";
+ clock-frequency = <32000>;
+ resets = <&reset RK3368_SRST_TSADC_P>;
+ reset-names = "tsadc-apb";
+ //pinctrl-names = "default";
+ //pinctrl-0 = <&tsadc_int>;
+ #thermal-sensor-cells = <1>;
+ hw-shut-temp = <120000>;
status = "disabled";
};
status = "okay";
};
+ dwc_control_usb: dwc-control-usb {
+ compatible = "rockchip,rk3368-dwc-control-usb";
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg_id", "otg_bvalid",
+ "otg_linestate", "host0_linestate";
+ clocks = <&clk_gates20 6>, <&usbphy_480m>;
+ clock-names = "hclk_usb_peri", "usbphy_480m";
+ //resets = <&reset RK3128_RST_USBPOR>;
+ //reset-names = "usbphy_por";
+ usb_bc{
+ compatible = "inno,phy";
+ regbase = &dwc_control_usb;
+ rk_usb,bvalid = <0x4bc 23 1>;
+ rk_usb,iddig = <0x4bc 26 1>;
+ rk_usb,vdmsrcen = <0x718 12 1>;
+ rk_usb,vdpsrcen = <0x718 11 1>;
+ rk_usb,rdmpden = <0x718 10 1>;
+ rk_usb,idpsrcen = <0x718 9 1>;
+ rk_usb,idmsinken = <0x718 8 1>;
+ rk_usb,idpsinken = <0x718 7 1>;
+ rk_usb,dpattach = <0x4b8 31 1>;
+ rk_usb,cpdet = <0x4b8 30 1>;
+ rk_usb,dcpattach = <0x4b8 29 1>;
+ };
+ };
+
+ usb0: usb@ff580000 {
+ compatible = "rockchip,rk3368_usb20_otg";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 1>, <&clk_gates20 1>;
+ clock-names = "clk_usbphy0", "hclk_otg";
+ resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
+ <&reset RK3368_SRST_USBOTGC0>;
+ reset-names = "otg_ahb", "otg_phy", "otg_controller";
+ /*0 - Normal, 1 - Force Host, 2 - Force Device*/
+ rockchip,usb-mode = <0>;
+ };
+
+ usb_ehci: usb@ff500000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff500000 0x0 0x20000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 1>, <&clk_gates20 3>;
+ clock-names = "clk_usbphy0", "hclk_ehci";
+ //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
+ // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
+ //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
+ };
+
+ usb_ohci: usb@ff520000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff520000 0x0 0x20000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 1>, <&clk_gates20 3>;
+ clock-names = "clk_usbphy0", "hclk_ohci";
+ };
+
+ usb_hsic: usb@ff5c0000 {
+ compatible = "rockchip,rk3288_rk_hsic_host";
+ reg = <0x0 0xff5c0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+/*
+ clocks = <&hsicphy_480m>, <&clk_gates7 8>,
+ <&hsicphy_12m>, <&usbphy_480m>,
+ <&otgphy1_480m>, <&otgphy2_480m>;
+ clock-names = "hsicphy_480m", "hclk_hsic",
+ "hsicphy_12m", "usbphy_480m",
+ "hsic_usbphy1", "hsic_usbphy2";
+ resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
+ <&reset RK3288_SOFT_RST_HSICPHY>;
+ reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
+*/
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3368-pinctrl";
rockchip,grf = <&grf>;
- rockchip,pmu = <&pmu_grf>;
+ rockchip,pmugrf = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
drive-strength = <8>;
};
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
spi1_tx: spi1-tx {
rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
};
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
+ };
};
spi2 {
};
gmac {
- mac_clk: mac-clk {
- rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- mac_txpins: mac-txpins {
- rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
- <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
- <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
- <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
- <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
- <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
- };
-
- mac_rxpins: mac-rxpins {
- rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
+ <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
+ <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
+ <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
+ <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
+ <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
+ <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
+ <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
+ <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
+ <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
<3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
<3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
<3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
- <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
- <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
<3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
- <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
- };
-
- mac_crs: mac-crs {
- rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
+ <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
};
- mac_mdpins: mac-mdpins {
- rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
- <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
+ rmii_pins: rmii-pins {
+ rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
+ <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
+ <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
+ <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
+ <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
+ <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
+ <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
+ <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
+ <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
+ <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
};
};
<3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+ cpu_jtag {
+ cpu_jtag: cpu-jtag {
+ rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
+ <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+ };
+
+ reboot {
+ compatible = "rockchip,rk3368-reboot";
+ rockchip,cru = <&cru>;
+ rockchip,pmugrf = <&pmugrf>;
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff