Merge tag 'omap-late-cleanups' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / dpll3xxx.c

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index bebd7eda6f71414b08c2cd6dc342f02e531579bb..0a02aab5df677db9bc5577093f5f6091d4c86ff8 100644 (file)
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -291,16 +291,13 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 
 /*
  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
+ * @clk:       struct clk * of DPLL to set
+ * @freqsel:   FREQSEL value to set
  *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock..  Returns -EINVAL upon error, or 0 upon success.
+ * Program the DPLL with the last M, N values calculated, and wait for
+ * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
  */
-static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
-                                     u16 freqsel)
+static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 {
        struct dpll_data *dd = clk->dpll_data;
        u8 dco, sd_div;
@@ -323,23 +320,45 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
        /* Set DPLL multiplier, divider */
        v = __raw_readl(dd->mult_div1_reg);
        v &= ~(dd->mult_mask | dd->div1_mask);
-       v |= m << __ffs(dd->mult_mask);
-       v |= (n - 1) << __ffs(dd->div1_mask);
+       v |= dd->last_rounded_m << __ffs(dd->mult_mask);
+       v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
 
        /* Configure dco and sd_div for dplls that have these fields */
        if (dd->dco_mask) {
-               _lookup_dco(clk, &dco, m, n);
+               _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
                v &= ~(dd->dco_mask);
                v |= dco << __ffs(dd->dco_mask);
        }
        if (dd->sddiv_mask) {
-               _lookup_sddiv(clk, &sd_div, m, n);
+               _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
+                             dd->last_rounded_n);
                v &= ~(dd->sddiv_mask);
                v |= sd_div << __ffs(dd->sddiv_mask);
        }
 
        __raw_writel(v, dd->mult_div1_reg);
 
+       /* Set 4X multiplier and low-power mode */
+       if (dd->m4xen_mask || dd->lpmode_mask) {
+               v = __raw_readl(dd->control_reg);
+
+               if (dd->m4xen_mask) {
+                       if (dd->last_rounded_m4xen)
+                               v |= dd->m4xen_mask;
+                       else
+                               v &= ~dd->m4xen_mask;
+               }
+
+               if (dd->lpmode_mask) {
+                       if (dd->last_rounded_lpmode)
+                               v |= dd->lpmode_mask;
+                       else
+                               v &= ~dd->lpmode_mask;
+               }
+
+               __raw_writel(v, dd->control_reg);
+       }
+
        /* We let the clock framework set the other output dividers later */
 
        /* REVISIT: Set ramp-up delay? */
@@ -491,8 +510,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                pr_debug("%s: %s: set rate: locking rate to %lu.\n",
                         __func__, __clk_get_name(hw->clk), rate);
 
-               ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-                                               dd->last_rounded_n, freqsel);
+               ret = omap3_noncore_dpll_program(clk, freqsel);
                if (!ret)
                        new_parent = dd->clk_ref;
        }