arm64: dts: rockchip: add tsadc's working clock rate for rk3288

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk3288.dtsi

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index e13c9febae2c04248ce71feb4b7eb34843f27350..f7601f4f7bedd88d4a763e751c6366b719ccf435 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/power/rk3288-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
 #include "skeleton.dtsi"
 
 / {
@@ -398,6 +399,19 @@
                status = "disabled";
        };
 
+       i2c0: i2c@ff650000 {
+               compatible = "rockchip,rk3288-i2c";
+               reg = <0xff650000 0x1000>;
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c0_xfer>;
+               status = "disabled";
+       };
+
        i2c1: i2c@ff140000 {
                compatible = "rockchip,rk3288-i2c";
                reg = <0xff140000 0x1000>;
@@ -596,6 +610,8 @@
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
                clock-names = "tsadc", "apb_pclk";
+               assigned-clocks = <&cru SCLK_TSADC>;
+               assigned-clock-rates = <10000>;
                resets = <&cru SRST_TSADC>;
                reset-names = "tsadc-apb";
                pinctrl-names = "init", "default", "sleep";
@@ -624,7 +640,6 @@
                        "aclk_mac", "pclk_mac";
                resets = <&cru SRST_MAC>;
                reset-names = "stmmaceth";
-               max-speed = <100>;
                status = "disabled";
        };
 
@@ -700,19 +715,6 @@
                              "arm_clk", "aclk_dmac1";
        };
 
-       i2c0: i2c@ff650000 {
-               compatible = "rockchip,rk3288-i2c";
-               reg = <0xff650000 0x1000>;
-               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               clock-names = "i2c";
-               clocks = <&cru PCLK_I2C0>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&i2c0_xfer>;
-               status = "disabled";
-       };
-
        i2c2: i2c@ff660000 {
                compatible = "rockchip,rk3288-i2c";
                reg = <0xff660000 0x1000>;
@@ -1129,6 +1131,7 @@
                power-domains = <&power RK3288_PD_VIO>;
                resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
                reset-names = "core", "axi", "ahb";
+               dma-coherent;
                status = "disabled";
        };
 
@@ -1175,6 +1178,8 @@
                reg = <0xff930300 0x100>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopb_mmu";
+               clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+               clock-names = "aclk", "hclk";
                power-domains = <&power RK3288_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
@@ -1224,6 +1229,8 @@
                reg = <0xff940300 0x100>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopl_mmu";
+               clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+               clock-names = "aclk", "hclk";
                power-domains = <&power RK3288_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
@@ -1331,6 +1338,8 @@
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
                clock-names = "iahb", "isfr";
+               pinctrl-names = "default";
+               pinctrl-0 = <&hdmi_ddc>;
                power-domains = <&power RK3288_PD_VIO>;
                status = "disabled";
 
@@ -1390,6 +1399,8 @@
                reg = <0xff9a0800 0x100>;
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+               clock-names = "aclk", "hclk";
                power-domains = <&power RK3288_PD_VIDEO>;
                #iommu-cells = <0>;
        };
@@ -1431,6 +1442,11 @@
                reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "hevc_mmu";
+               clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+                       <&cru SCLK_HEVC_CORE>,
+                       <&cru SCLK_HEVC_CABAC>;
+               clock-names = "aclk", "hclk", "clk_core",
+                       "clk_cabac";
                power-domains = <&power RK3288_PD_HEVC>;
                #iommu-cells = <0>;
        };
@@ -1452,6 +1468,9 @@
                power-domains = <&power RK3288_PD_GPU>;
                status = "disabled";
 
+               upthreshold = <75>;
+               downdifferential = <10>;
+
                gpu_power_model: power_model {
                        compatible = "arm,mali-simple-power-model";
                        voltage = <950>;