+
+ nandc0: nandc@ff400000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x0 0xff400000 0x0 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ nandc_id = <0>;
+ clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
+ clock-names = "clk_nandc", "hclk_nandc";
+ status = "disabled";
+ };
+};
+
+&edp_panel {
+ backlight = <&backlight>;
+};
+
+&cpu0 {
+ enable-method = "psci";
+};
+
+&cpu1 {
+ enable-method = "psci";
+};
+
+&cpu2 {
+ enable-method = "psci";
+};
+
+&cpu3 {
+ enable-method = "psci";
+};
+
+&dmac_bus_s {
+ /* change to non-secure dmac */
+ reg = <0xff600000 0x4000>;
+};
+
+&efuse {
+ compatible = "rockchip,rk3288-secure-efuse";
+};
+
+&rga {
+ compatible = "rockchip,rga2";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";