+#include <dt-bindings/clock/ddr.h>
+#include <dt-bindings/rkfb/rk_fb.h>
+#include <dt-bindings/suspend/rockchip-pm.h>
+#include <dt-bindings/sensor-dev.h>
#include "skeleton.dtsi"
#include "rk3188-pinctrl.dtsi"
-#include <dt-bindings/rkfb/rk_fb.h>
-#include "rk3188_io_vol_domain.dtsi"
-
-#include <dt-bindings/sensor-dev.h>
+#include "rk3188-clocks.dtsi"
/ {
compatible = "rockchip,rk3188";
rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
};
- cpu_axi_bus: cpu_axi_bus@10128000 {
+ cpu_axi_bus: cpu_axi_bus {
compatible = "rockchip,cpu_axi_bus";
- reg = <0x10128000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
qos {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
dmac {
- rockchip,offset = <0x1000>;
+ reg = <0x10129000 0x20>;
rockchip,priority = <0 0>;
};
cpu0 {
- rockchip,offset = <0x2000>;
+ reg = <0x1012a000 0x20>;
rockchip,priority = <0 0>;
};
- cpu1r {
- rockchip,offset = <0x2080>;
+ cpu1_r {
+ reg = <0x1012a080 0x20>;
rockchip,priority = <0 0>;
};
- cpu1w {
- rockchip,offset = <0x2100>;
+ cpu1_w {
+ reg = <0x1012a100 0x20>;
rockchip,priority = <0 0>;
};
peri {
- rockchip,offset = <0x4000>;
+ reg = <0x1012c000 0x20>;
rockchip,priority = <2 2>;
};
gpu {
- rockchip,offset = <0x5000>;
+ reg = <0x1012d000 0x20>;
rockchip,priority = <2 1>;
};
vpu {
- rockchip,offset = <0x6000>;
+ reg = <0x1012e000 0x20>;
};
vop0 {
- rockchip,offset = <0x7000>;
+ reg = <0x1012f000 0x20>;
rockchip,priority = <3 3>;
};
cif0 {
- rockchip,offset = <0x7080>;
+ reg = <0x1012f080 0x20>;
};
ipp {
- rockchip,offset = <0x7100>;
+ reg = <0x1012f100 0x20>;
};
vop1 {
- rockchip,offset = <0x7180>;
+ reg = <0x1012f180 0x20>;
rockchip,priority = <3 3>;
};
cif1 {
- rockchip,offset = <0x7200>;
+ reg = <0x1012f200 0x20>;
};
rga {
- rockchip,offset = <0x7280>;
+ reg = <0x1012f280 0x20>;
+ };
+ };
+ msch {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ msch {
+ reg = <0x10128000 0x18>;
+ rockchip,read-latency = <0x3f>;
};
};
};
};
};
+ emmc: rksdmmc@1021C000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x1021C000 0x4000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;/*irq=57*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ //pinctrl-names = "default",,"suspend";
+ //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
+ clocks = <&clk_gates2 14>;
+ num-slots = <1>;
+
+ fifo-depth = <0x80>;
+ bus-width = <4>;
+ };
+
+ sdmmc: rksdmmc@10214000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x10214000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; /*irq=55*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default","suspend";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
+ pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
+ clocks = <&clk_gates2 11>;
+ num-slots = <1>;
+
+ fifo-depth = <0x100>;
+ bus-width = <4>;
+ };
+
+ sdio: rksdmmc@10218000 {
+ compatible = "rockchip,rk_mmc";
+ reg = <0x10218000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default","suspend";
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
+ clocks = <&clk_gates2 13>;
+ num-slots = <1>;
+
+ fifo-depth = <0x100>;
+ bus-width = <4>;
+ };
uart0: serial@10124000 {
compatible = "rockchip,serial";
clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
- <&clk_core &clk_apll>, <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
- <&aclk_peri_mux &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
+ <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
+ <&aclk_peri &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
<&clk_uart_pll_mux &clk_gpll>;
rockchip,clocks-init-rate =
<&clk_core 792000000>, <&clk_gpll 768000000>,
<&aclk_lcdc1 300000000>;
};
+ rockchip_suspend: rockchip_suspend {
+ //compatible = "rockchip,rkpm_suspend";
+ // define value is in dt-bindint/suspend/rockchip-pm.h
+ rockchip,ctrbits = <
+ (
+ RKPM_CTR_PWR_DMNS
+ |RKPM_CTR_GTCLKS
+ |RKPM_CTR_PLLS
+ |RKPM_CTR_SYSCLK_DIV
+ )
+ >;
+ rockchip,pmic-gpios=<
+ RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
+ RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
+ >;
+ };
+
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <DUAL>;
};
+ rk_screen: rk_screen{
+ compatible = "rockchip,screen";
+ };
+
nandc: nandc {
compatible = "rockchip,rk-nandc";
reg = <0x10050000 0x4000>;
pinctrl-0 = <&lcdc1_lcdc>;
pinctrl-1 = <&lcdc1_gpio>;
status = "disabled";
- };
- rga@10114000 {
+ };
+
+ rga@10114000 {
compatible = "rockchip,rga";
reg = <0x10114000 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates6 10>, <&clk_gates6 11>;
- clock-names = "hclk_rga", "aclk_rga";
- };
-
- adc: adc@2006c000 {
- compatible = "rockchip,saradc";
- reg = <0x2006c000 0x100>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- rockchip,adc-vref = <1800>;
- clock-frequency = <1000000>;
- clocks = <&clk_saradc>, <&clk_gates7 14>;
- clock-names = "saradc", "pclk_saradc";
- status = "disabled";
- };
+ clock-names = "hclk_rga", "aclk_rga";
+ };
+
+ adc: adc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ rockchip,adc-vref = <1800>;
+ clock-frequency = <1000000>;
+ clocks = <&clk_saradc>, <&clk_gates7 14>;
+ clock-names = "saradc", "pclk_saradc";
+ status = "disabled";
+ };
spdif: rockchip-spdif@0x1011e000 {
compatible = "rockchip-spdif";
pwm0: pwm@20030000{
compatible = "rockchip,pwm";
- reg = <0x20030000 0x10>;
+ reg = <0x20030000 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
+ clocks = <&clk_gates7 10>;
+ clock-names = "pclk_pwm";
status = "disabled";
};
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
+ clocks = <&clk_gates7 10>;
+ clock-names = "pclk_pwm";
status = "disabled";
};
reg = <0x20050020 0x10>; /*0x20030000*/
#pwm-cells = <2>;
pinctrl-names = "default";
+ clock-names = "pclk_pwm";
+ clocks = <&clk_gates7 11>;
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
+ clocks = <&clk_gates7 11>;
+ clock-names = "pclk_pwm";
status = "disabled";
};
dvfs {
- vd_cpu:
- vd_cpu {
+ vd_arm:
+ vd_arm {
regulator_name="vdd_arm";
suspend_volt=<1000>; //mV
pd_a9 {
1416000 1300000
1608000 1350000
>;
+ status = "okay";
};
};
};
- vd_core:
- vd_core {
+ vd_logic:
+ vd_logic {
regulator_name="vdd_logic";
suspend_volt=<1000>; //mV
300000 1200000
400000 1200000
>;
+ status = "okay";
};
};
300000 1200000
400000 1200000
>;
+ status = "disable";
};
};
};
};
- ion: ion{
+ ion{
compatible = "rockchip,ion";
#address-cells = <1>;
#size-cells = <0>;
<0x2000812c 0x8>,
<0x20008138 0x8>;
reg-names = "GRF_SOC_STATUS0",
- "GRF_UOC0_BASE",
- "GRF_UOC1_BASE",
- "GRF_UOC2_BASE",
- "GRF_UOC3_BASE";
+ "GRF_UOC0_BASE",
+ "GRF_UOC1_BASE",
+ "GRF_UOC2_BASE",
+ "GRF_UOC3_BASE";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "bvalid";
+ interrupt-names = "otg_bvalid";
gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
clocks = <&clk_gates4 5>;
clock-names = "hclk_usb_peri";
+ rockchip,remote_wakeup;
+ rockchip,usb_irq_wakeup;
+
+ usb_bc{
+ compatible = "rockchip,ctrl";
+ rk_usb,bvalid = <0xac 10 1>;
+ rk_usb,iddig = <0xac 13 1>;
+ rk_usb,line = <0xac 11 2>;
+ rk_usb,softctrl = <0x114 2 1>;
+ rk_usb,opmode = <0x118 1 2>;
+ rk_usb,xcvrsel = <0x118 3 2>;
+ rk_usb,termsel = <0x118 5 1>;
+ };
};
+
- usb@10180000 {
+ usb0: usb@10180000 {
compatible = "rockchip,rk3188_usb20_otg";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
- clock-names = "otgphy0", "hclk_otg0";
+ clocks = <&clk_gates1 5>, <&clk_gates5 13>;
+ clock-names = "clk_usbphy0", "hclk_usb0";
+ /*0 - Normal, 1 - Force Host, 2 - Force Device*/
+ rockchip,usb-mode = <0>;
};
- usb@101c0000 {
+ usb1: usb@101c0000 {
compatible = "rockchip,rk3188_usb20_host";
reg = <0x101c0000 0x40000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
- clock-names = "otgphy1", "hclk_otg1";
+ clocks = <&clk_gates1 6>, <&clk_gates7 3>;
+ clock-names = "clk_usbphy1", "hclk_usb1";
};
- hsic@10240000 {
- compatible = "rockchip,rk3188_rk_hsic_host";
+ usb2: usb@10240000 {
+ compatible = "rockchip,rk3188_rk_ehci_host";
reg = <0x10240000 0x40000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
- <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
- clock-names = "hsicphy480m", "hclk_hsic",
- "hsicphy12m", "hsic_otgphy1";
+ clocks = <&clk_ehci1phy480m>, <&clk_gates7 4>,
+ <&clk_ehci1phy12m>, <&otgphy1_480m>;
+ clock-names = "ehci1phy_480m", "hclk_ehci1",
+ "ehci1phy_12m", "ehci1_usbphy1";
};
vmac@10204000 {
pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
};
+
+ ap0_vcc_domain: ap0-vcc-domain {
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&ap0_vcc >;
+ pinctrl-1 = <&ap0_vcc_18>;
+ pinctrl-2 = <&ap0_vcc_33>;
+ };
+ ap1_vcc_domain: ap1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&ap1_vcc >;
+ pinctrl-1 = <&ap1_vcc_18>;
+ pinctrl-2 = <&ap1_vcc_33>;
+ };
+ cif_vcc_domain: cif-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&cif_vcc>;
+ pinctrl-1 = <&cif_vcc_18>;
+ pinctrl-2 = <&cif_vcc_33>;
+ };
+ flash_vcc_domain: flash-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&flash_vcc>;
+ pinctrl-1 = <&flash_vcc_18>;
+ pinctrl-2 = <&flash_vcc_33>;
+ };
+ vccio0_vcc_domain: vccio0-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&vccio0_vcc>;
+ pinctrl-1 = <&vccio0_vcc_18>;
+ pinctrl-2 = <&vccio0_vcc_33>;
+ };
+ vccio1_vcc_domain: vccio1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&vccio1_vcc>;
+ pinctrl-1 = <&vccio1_vcc_18>;
+ pinctrl-2 = <&vccio1_vcc_33>;
+ };
+ lcdc0_vcc_domain: lcdc0-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&lcdc0_vcc>;
+ pinctrl-1 = <&lcdc0_vcc_18>;
+ pinctrl-2 = <&lcdc0_vcc_33>;
+ };
+ lcdc1_vcc_domain: lcdc1-vcc-domain{
+ compatible = "rockchip,io_vol_domain";
+ pinctrl-names = "default", "1.8V", "3.3V";
+ pinctrl-0 = <&lcdc1_vcc>;
+ pinctrl-1 = <&lcdc1_vcc_18>;
+ pinctrl-2 = <&lcdc1_vcc_33>;
+ };
+
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff