+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3036-cru.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
#include "skeleton.dtsi"
-#include "rk3036-clocks.dtsi"
-#include "rk3036-pinctrl.dtsi"
-#include <dt-bindings/suspend/rockchip-pm.h>
/ {
compatible = "rockchip,rk3036";
- rockchip,sram = <&sram>;
+
interrupt-parent = <&gic>;
aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
- spi0 = &spi0;
+ mshc0 = &emmc;
+ mshc1 = &sdmmc;
+ mshc2 = &sdio;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ spi = &spi;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "rockchip,rk3036-smp";
- cpu@0 {
+ cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ resets = <&cru SRST_CORE0>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
};
- cpu@1 {
+
+ cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
+ resets = <&cru SRST_CORE1>;
};
};
- gic: interrupt-controller@10139000 {
- compatible = "arm,cortex-a15-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>;
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ peripherals-req-type-burst;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
};
- cpu_axi_bus: cpu_axi_bus {
- compatible = "rockchip,cpu_axi_bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- qos {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- core {
- reg = <0x1012a000 0x20>;
- rockchip,priority = <3 2>;
- };
- peri {
- reg = <0x1012c000 0x20>;
- };
- gpu {
- reg = <0x1012d000 0x20>;
- };
- vpu {
- reg = <0x1012e000 0x20>;
- };
- hevc {
- reg = <0x1012e080 0x20>;
- };
- vio {
- reg = <0x1012f000 0x20>;
- rockchip,priority = <3 3>;
- };
- };
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
- msch {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
- msch@10128000 {
- reg = <0x10128000 0x40>;
- rockchip,read-latency = <0x80>;
- };
- };
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
};
- sram: sram@10080000 {
+ bus_intmem@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
- map-exec;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+
+ smp-sram@0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x00 0x10>;
+ };
};
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
+ gpu: gpu@10090000 {
+ compatible = "arm,mali400";
+
+ reg = <0x10091000 0x200>,
+ <0x10090000 0x100>,
+ <0x10093000 0x100>,
+ <0x10098000 0x1100>,
+ <0x10094000 0x100>;
+
+ reg-names = "Mali_L2",
+ "Mali_GP",
+ "Mali_GP_MMU",
+ "Mali_PP0",
+ "Mali_PP0_MMU";
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "Mali_GP_IRQ",
+ "Mali_GP_MMU_IRQ",
+ "Mali_PP0_IRQ",
+ "Mali_PP0_MMU_IRQ";
+
+ clocks = <&cru SCLK_GPU>;
+ clock-names = "clk_mali";
+
+ status = "disabled";
};
- timer@20044000 {
- compatible = "rockchip,timer";
- reg = <0x20044000 0x20>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,broadcast = <1>;
- };
-
- watchdog: wdt@2004c000 {
- compatible = "rockchip,watch dog";
- reg = <0x2004c000 0x100>;
- clocks = <&clk_gates7 15>;
- clock-names = "pclk_wdt";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,irq = <1>;
- rockchip,timeout = <60>;
- rockchip,atboot = <1>;
- rockchip,debug = <0>;
+ vpu: video-codec@10108000 {
+ compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
+ reg = <0x10108000 0x800>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ /*
+ * 3036's vpu could not run higher than 300M
+ */
+ assigned-clocks = <&cru ACLK_VCODEC>;
+ assigned-clock-rates = <297000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>;
status = "disabled";
};
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus";
- interrupt-parent = <&gic>;
- ranges;
+ vpu_mmu: iommu@10108800 {
+ compatible = "rockchip,iommu";
+ reg = <0x10108800 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ };
- pdma: pdma@20078000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x20078000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
+ vop: vop@10118000 {
+ compatible = "rockchip,rk3036-vop";
+ reg = <0x10118000 0x19c>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
};
};
- reset: reset@20000110{
- compatible = "rockchip,reset";
- reg = <0x20000110 0x24>;
- rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
- #reset-cells = <1>;
+ vop_mmu: iommu@10118300 {
+ compatible = "rockchip,iommu";
+ reg = <0x10118300 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@10139000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x10139000 0x1000>,
+ <0x1013a000 0x1000>,
+ <0x1013c000 0x2000>,
+ <0x1013e000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
- nandc: nandc@10500000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x10500000 0x4000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- //pinctrl-names = "default";
- //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
- nandc_id = <0>;
- clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
- clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
+ usb_otg: usb@10180000 {
+ compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG0>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
+ g-use-dma;
+ status = "disabled";
};
- nandc0reg: nandc0@10500000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x10500000 0x4000>;
+ usb_host: usb@101c0000 {
+ compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x101c0000 0x40000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG1>;
+ clock-names = "otg";
+ dr_mode = "host";
+ status = "disabled";
};
- spi0: spi@20074000 {
- compatible = "rockchip,rockchip-spi";
- reg = <0x20074000 0x1000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ emac: ethernet@10200000 {
+ compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+ reg = <0x10200000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
- rockchip,spi-src-clk = <0>;
- num-cs = <2>;
- clocks =<&clk_spi0>, <&clk_gates2 9>;
- clock-names = "spi","pclk_spi0";
- dmas = <&pdma 8>, <&pdma 9>;
- #dma-cells = <2>;
- dma-names = "tx", "rx";
+ rockchip,grf = <&grf>;
+ clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+ clock-names = "hclk", "macref", "macclk";
+ /*
+ * Fix the emac parent clock is DPLL instead of APLL.
+ * since that will cause some unstable things if the cpufreq
+ * is working. (e.g: the accurate 50MHz what mac_ref need)
+ */
+ assigned-clocks = <&cru SCLK_MACPLL>;
+ assigned-clock-parents = <&cru PLL_DPLL>;
+ max-speed = <100>;
+ phy-mode = "rmii";
status = "disabled";
};
- uart0: serial@20060000 {
- compatible = "rockchip,serial";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart0>, <&clk_gates8 0>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 2>, <&pdma 3>;
- #dma-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ sdmmc: dwmmc@10214000 {
+ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10214000 0x4000>;
+ clock-frequency = <37500000>;
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart1: serial@20064000 {
- compatible = "rockchip,serial";
- reg = <0x20064000 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart1>, <&clk_gates8 1>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 4>, <&pdma 5>;
- #dma-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
+ sdio: dwmmc@10218000 {
+ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10218000 0x4000>;
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart2: serial@20068000 {
- compatible = "rockchip,serial";
- reg = <0x20068000 0x100>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <24000000>;
- clocks = <&clk_uart2>, <&clk_gates8 2>;
- clock-names = "sclk_uart", "pclk_uart";
- reg-shift = <2>;
- reg-io-width = <4>;
- dmas = <&pdma 6>, <&pdma 7>;
- #dma-cells = <2>;
+ emmc: dwmmc@1021c000 {
+ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x1021c000 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <37500000>;
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ default-sample-phase = <158>;
+ disable-wp;
+ dmas = <&pdma 12>;
+ dma-names = "rx-tx";
+ fifo-depth = <0x100>;
+ mmc-ddr-1_8v;
+ non-removable;
+ num-slots = <1>;
+ supports-emmc;
pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "disabled";
};
- fiq-debugger {
- compatible = "rockchip,fiq-debugger";
- rockchip,serial-id = <2>;
- rockchip,signal-irq = <106>;
- rockchip,wake-irq = <0>;
+ i2s: i2s@10220000 {
+ compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
+ reg = <0x10220000 0x4000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_bus>;
status = "disabled";
};
- clocks-init{
- compatible = "rockchip,clocks-init";
- rockchip,clocks-init-parent =
- <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
- <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
- <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
- <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
- <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
- rockchip,clocks-init-rate =
- <&clk_core 1200000000>, <&clk_gpll 1188000000>,
- <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
- <&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
- <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
- <&clk_gpu 400000000>, <&aclk_vio_pre 300000000>,
- <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
- <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
- <&clk_mac_ref_div 25000000>;
- /* rockchip,clocks-uboot-has-init =
- <&aclk_vio1>;*/
- };
-
- clocks-enable {
- compatible = "rockchip,clocks-enable";
- clocks =
- /*PD_CORE*/
- <&clk_gates0 0>, <&clk_gates0 7>,
-
- /*PD_CPU*/
- <&clk_gates0 3>, <&clk_gates0 4>,
- <&clk_gates0 5>,
-
- /*TIMER*/
- <&clk_gates1 0>, <&clk_gates1 1>,
- <&clk_gates2 4>, <&clk_gates2 5>,
-
- /*PD_PERI*/
- <&clk_gates2 0>, <&hclk_peri_pre>,
- <&pclk_peri_pre>, <&clk_gates2 1>,
-
- /*aclk_cpu_pre*/
- <&clk_gates4 12>,/*aclk_intmem*/
- <&clk_gates4 10>,/*aclk_strc_sys*/
-
- /*hclk_cpu_pre*/
- <&clk_gates5 6>,/*hclk_rom*/
-
- /*pclk_cpu_pre*/
- <&clk_gates5 4>,/*pclk_grf*/
- <&clk_gates5 7>,/*pclk_ddrupctl*/
- <&clk_gates5 14>,/*pclk_acodec*/
- <&clk_gates3 8>,/*pclk_hdmi*/
-
- /*aclk_peri_pre*/
- <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
- <&clk_gates5 1>,/*aclk_dmac2*/
- <&clk_gates9 15>,/*aclk_peri_niu*/
- <&clk_gates4 2>,/*aclk_cpu_peri*/
-
- /*hclk_peri_pre*/
- <&clk_gates4 0>,/*hclk_peri_matrix*/
- <&clk_gates9 13>,/*hclk_usb_peri*/
- <&clk_gates9 14>,/*hclk_peri_arbi*/
-
- /*pclk_peri_pre*/
- <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
-
- /*hclk_vio_pre*/
- <&clk_gates6 12>,/*hclk_vio_bus*/
- <&clk_gates9 5>,/*hclk_lcdc*/
-
- /*aclk_vio_pre*/
- <&clk_gates6 13>,/*aclk_vio*/
- <&clk_gates9 6>,/*aclk_lcdc*/
-
- /*UART*/
- <&clk_gates1 12>,
- <&clk_gates1 13>,
- <&clk_gates8 2>,/*pclk_uart2*/
-
- <&clk_gpu>,
-
- /*jtag*/
- <&clk_gates1 3>;/*clk_jtag*/
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ grf: syscon@20008000 {
+ compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
+ reg = <0x20008000 0x1000>;
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x1d8>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-ums = <BOOT_UMS>;
+ };
};
- i2c0: i2c@20072000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x20072000 0x1000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_sda &i2c0_scl>;
- pinctrl-1 = <&i2c0_gpio>;
- gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 4>;
- rockchip,check-idle = <1>;
+ acodec: acodec-ana@20030000 {
+ compatible = "rk3036-codec";
+ reg = <0x20030000 0x4000>;
+ rockchip,grf = <&grf>;
+ clock-names = "acodec_pclk";
+ clocks = <&cru PCLK_ACODEC>;
status = "disabled";
};
- i2c1: i2c@20056000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x20056000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ hdmi: hdmi@20034000 {
+ compatible = "rockchip,rk3036-inno-hdmi";
+ reg = <0x20034000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>;
+ clock-names = "pclk";
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ctl>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_sda &i2c1_scl>;
- pinctrl-1 = <&i2c1_gpio>;
- gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 5>;
- rockchip,check-idle = <1>;
+ #sound-dai-cells = <0>;
status = "disabled";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
};
- i2c2: i2c@2005a000 {
- compatible = "rockchip,rk30-i2c";
- reg = <0x2005a000 0x1000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_sda &i2c2_scl>;
- pinctrl-1 = <&i2c2_gpio>;
- gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
- clocks = <&clk_gates8 6>;
- rockchip,check-idle = <1>;
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,hdmi";
+ simple-audio-card,widgets = "Headphone", "Out Jack",
+ "Line", "In Jack";
status = "disabled";
- };
- i2s: i2s@10220000 {
- compatible = "rockchip-i2s";
- reg = <0x10220000 0x1000>;
- i2s-id = <0>;
- clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
- clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma 0>, <&pdma 1>;
- //#dma-cells = <2>;
- dma-names = "tx", "rx";
- //pinctrl-names = "default", "sleep";
- //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
- //pinctrl-1 = <&i2s_gpio>;
+ simple-audio-card,dai-link {
+ format = "i2s";
+ mclk-fs = <256>;
+ cpu {
+ sound-dai = <&i2s>;
+ };
+ codec {
+ sound-dai = <&hdmi>;
+ };
+ };
};
- codec: codec@20030000 {
- compatible = "rk3036-codec";
- reg = <0x20030000 0x1000>;
- spk_ctl_io = <&gpio1 GPIO_A0 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_gpio>;
-
- boot_depop = <1>;
- pa_enable_time = <1000>;
- clocks = <&clk_gates5 14>;
- clock-names = "g_pclk_acodec";
- };
-
- spdif: spdif@10204000 {
- compatible = "rockchip-spdif";
- reg = <0x10204000 0x1000>;
- clocks = <&clk_spdif>;
- clock-names = "spdif_mclk";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&pdma 13>;
- //#dma-cells = <1>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx>;
+ timer: timer@20044000 {
+ compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
+ reg = <0x20044000 0x20>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>, <&cru PCLK_TIMER>;
+ clock-names = "timer", "pclk";
};
pwm0: pwm@20050000 {
- compatible = "rockchip,rk-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050000 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
status = "disabled";
};
pwm1: pwm@20050010 {
- compatible = "rockchip,rk-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050010 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
status = "disabled";
};
pwm2: pwm@20050020 {
- compatible = "rockchip,rk-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050020 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
status = "disabled";
};
pwm3: pwm@20050030 {
- compatible = "rockchip,rk-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
status = "disabled";
};
- remotectl: pwm@20050030 {
- compatible = "rockchip,remotectl-pwm";
- reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
+ i2c1: i2c@20056000 {
+ compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- clocks = <&clk_gates7 10>;
- clock-names = "pclk_pwm";
- remote_pwm_id = <3>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
};
- emmc: rksdmmc@1021c000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x1021c000 0x4000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ i2c2: i2c@2005a000 {
+ compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005a000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- //pinctrl-names = "default",,"suspend";
- //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
- clocks = <&clk_emmc>, <&clk_gates7 0>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 12>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <8>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial@20060000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20060000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
};
+ uart1: serial@20064000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20064000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
- sdmmc: rksdmmc@10214000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x10214000 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ uart2: serial@20068000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@20072000 {
+ compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
+ reg = <0x20072000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default", "idle", "udbg";
- pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
- pinctrl-1 = <&sdmmc0_gpio>;
- pinctrl-2 = <&uart2_xfer>;
- cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
- clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 10>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <4>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ status = "disabled";
};
- sdio: rksdmmc@10218000 {
- compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
- reg = <0x10218000 0x4000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ spi: spi@20074000 {
+ compatible = "rockchip,rockchip-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
+ clock-names = "apb-pclk","spi_pclk";
+ dmas = <&pdma 8>, <&pdma 9>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default","idle";
- pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
- pinctrl-1 = <&sdio0_gpio>;
- clocks = <&clk_sdio>, <&clk_gates5 11>;
- clock-names = "clk_mmc", "hclk_mmc";
- dmas = <&pdma 11>;
- dma-names = "dw_mci";
- num-slots = <1>;
- fifo-depth = <0x100>;
- bus-width = <4>;
+ status = "disabled";
};
- gpu {
- compatible = "arm,mali400";
- reg = <0x10091000 0x200>,
- <0x10090000 0x100>,
- <0x10093000 0x100>,
- <0x10098000 0x1100>,
- <0x10094000 0x100>;
- reg-names = "Mali_L2",
- "Mali_GP",
- "Mali_GP_MMU",
- "Mali_PP0",
- "Mali_PP0_MMU";
-
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "Mali_GP_IRQ",
- "Mali_GP_MMU_IRQ",
- "Mali_PP0_IRQ",
- "Mali_PP0_MMU_IRQ";
- };
- dwc_control_usb: dwc-control-usb@20008000 {
- compatible = "rockchip,rk3036-dwc-control-usb";
- reg = <0x20008000 0x4>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg_bvalid";
- clocks = <&clk_gates9 13>;
- clock-names = "hclk_usb_peri";
- rockchip,remote_wakeup;
- rockchip,usb_irq_wakeup;
- resets = <&reset RK3036_RST_USBPOR>;
- reset-names = "usbphy_por";
- usb_bc{
- compatible = "rockchip,ctrl";
- rk_usb,bvalid = <0x14c 8 1>;
- rk_usb,iddig = <0x14c 11 1>;
- rk_usb,line = <0x14c 9 2>;
- rk_usb,softctrl = <0x17c 0 1>;
- rk_usb,opmode = <0x17c 2 2>;
- rk_usb,xcvrsel = <0x17c 4 2>;
- rk_usb,termsel = <0x17c 6 1>;
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3036-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@2007c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2007c000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- };
- usb0: usb@10180000 {
- compatible = "rockchip,rk3036_usb20_otg";
- reg = <0x10180000 0x40000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates1 5>, <&clk_gates5 13>;
- clock-names = "clk_usbphy0", "hclk_usb0";
- resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
- <&reset RK3036_RST_OTGC0>;
- reset-names = "otg_ahb", "otg_phy", "otg_controller";
- /*0 - Normal, 1 - Force Host, 2 - Force Device*/
- rockchip,usb-mode = <0>;
- };
- usb1: usb@101c0000 {
- compatible = "rockchip,rk3036_usb20_host";
- reg = <0x101c0000 0x40000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_gates1 6>, <&clk_gates7 3>;
- clock-names = "clk_usbphy1", "hclk_usb1";
- resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
- <&reset RK3036_RST_OTGC1>;
- reset-names = "host_ahb", "host_phy", "host_controller";
- };
+ gpio1: gpio1@20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
- fb: fb{
- compatible = "rockchip,rk-fb";
- rockchip,disp-mode = <NO_DUAL>;
- rockchip,disp-policy = <1>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
- rk_screen: rk_screen{
- compatible = "rockchip,screen";
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- lcdc: lcdc@10118000 {
- compatible = "rockchip,rk3036-lcdc";
- reg = <0x10118000 0x1000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- rockchip,iommu-enabled = <1>;
- };
+ gpio2: gpio2@20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
- hdmi: hdmi@20034000 {
- compatible = "rockchip,rk3036-hdmi";
- reg = <0x20034000 0x4000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,hdmi_lcdc_source = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
- pinctrl-1 = <&hdmi_gpio>;
- clocks = <&clk_gates3 8>;
- clock-names = "pclk_hdmi";
- status = "disabled";
- };
+ gpio-controller;
+ #gpio-cells = <2>;
- tve: tve{
- compatible = "rockchip,rk3036-tve";
- reg = <0x10118200 0x100>;
- status = "disabled";
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- ion {
- compatible = "rockchip,ion";
- #address-cells = <1>;
- #size-cells = <0>;
+ pcfg_pull_default: pcfg_pull_default {
+ bias-pull-pin-default;
+ };
- ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
- compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <1>;
- reg = <0x00000000 0x00000000>; /* 0MB */
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
};
- rockchip,ion-heap@3 { /* VMALLOC HEAP */
- compatible = "rockchip,ion-heap";
- rockchip,ion_heap = <3>;
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
};
- };
- vpu: vpu_service@10108000 {
- compatible = "vpu_service";
- iommu_enabled = <1>;
- reg = <0x10108000 0x800>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- name = "vpu_service";
- status = "okay";
- };
-
- hevc: hevc_service@1010c000 {
- compatible = "rockchip,hevc_service";
- iommu_enabled = <1>;
- reg = <0x1010c000 0x400>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- name = "hevc_service";
- status = "okay";
- };
-
- vop_mmu {
- dbgname = "vop";
- compatible = "rockchip,vop_mmu";
- reg = <0x10118300 0x100>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
- };
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
- hevc_mmu {
- dbgname = "hevc";
- compatible = "rockchip,hevc_mmu";
- reg = <0x1010c440 0x40>,
- <0x1010c480 0x40>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hevc_mmu";
- };
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 1 2 &pcfg_pull_none>;
+ };
+ };
- vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x10108800 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
- };
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ };
+ };
- rockchip_suspend {
- rockchip,ctrbits = <
- (0
- //|RKPM_CTR_PWR_DMNS
- |RKPM_CTR_GTCLKS
- |RKPM_CTR_PLLS
- |RKPM_CTR_IDLESRAM_MD
- |RKPM_CTR_DDR
- |RKPM_CTR_VOLTS
- |RKPM_CTR_VOL_PWM2
-
- //|RKPM_CTR_GPIOS
- //|RKPM_CTR_SYSCLK_DIV
- //|RKPM_CTR_IDLEAUTO_MD
- //|RKPM_CTR_ARMOFF_LPMD
- //|RKPM_CTR_ARMOFF_LOGDP_LPMD
- )
- >;
-/*
- rockchip,pmic-suspend_gpios = <
- RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
- >;
- rockchip,pmic-resume_gpios = <
- RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
- >;
-*/
- };
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
+ };
- vmac: eth@10200000 {
- compatible = "rockchip,vmac";
- reg = <0x10200000 0x4000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clk_mac_pll>, <&clk_mac_ref>,
- <&clk_mac_pll_div>, <&clk_mac_ref_div>,
- <&clk_gates2 6>, <&clk_gates3 5>;
- clock-names = "clk_mac_pll", "clk_mac_ref",
- "clk_mac_pll_div", "clk_mac_ref_div",
- "clk_tx_rx_gate", "hclk_mac";
- pinctrl-names = "default";
- pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
- };
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdmmc_cd: sdmcc-cd {
+ rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
+ <1 19 RK_FUNC_1 &pcfg_pull_default>,
+ <1 20 RK_FUNC_1 &pcfg_pull_default>,
+ <1 21 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ sdio {
+ sdio_bus1: sdio-bus1 {
+ rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
+ <0 12 RK_FUNC_1 &pcfg_pull_default>,
+ <0 13 RK_FUNC_1 &pcfg_pull_default>,
+ <0 14 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sdio_clk: sdio-clk {
+ rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /*
+ * We run eMMC at max speed; bump up drive strength.
+ * We also have external pulls, so disable the internal ones.
+ */
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
+ <1 25 RK_FUNC_2 &pcfg_pull_default>,
+ <1 26 RK_FUNC_2 &pcfg_pull_default>,
+ <1 27 RK_FUNC_2 &pcfg_pull_default>,
+ <1 28 RK_FUNC_2 &pcfg_pull_default>,
+ <1 29 RK_FUNC_2 &pcfg_pull_default>,
+ <1 30 RK_FUNC_2 &pcfg_pull_default>,
+ <1 31 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ };
+
+ emac {
+ emac_xfer: emac-xfer {
+ rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
+ <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
+ <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
+ <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
+ <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
+ <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
+ <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
+ <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
+ };
+
+ emac_mdio: emac-mdio {
+ rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
+ <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
+ <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
+ <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
+ <2 21 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s {
+ i2s_bus: i2s-bus {
+ rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
+ <1 1 RK_FUNC_1 &pcfg_pull_default>,
+ <1 2 RK_FUNC_1 &pcfg_pull_default>,
+ <1 3 RK_FUNC_1 &pcfg_pull_default>,
+ <1 4 RK_FUNC_1 &pcfg_pull_default>,
+ <1 5 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ hdmi {
+ hdmi_ctl: hdmi-ctl {
+ rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
+ <1 9 RK_FUNC_1 &pcfg_pull_none>,
+ <1 10 RK_FUNC_1 &pcfg_pull_none>,
+ <1 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
+ <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
+ <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart1 */
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
+ <1 19 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart2 */
+ };
+
+ spi {
+ spi_txd:spi-txd {
+ rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
+ };
+
+ spi_rxd:spi-rxd {
+ rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
+ };
+
+ spi_clk:spi-clk {
+ rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
+ };
+
+ spi_cs0:spi-cs0 {
+ rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
+
+ };
+
+ spi_cs1:spi-cs1 {
+ rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
+
+ };
+ };
+ };
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff