phy: rockchip-dp: Add support for rk3368 Display Port PHY

[firefly-linux-kernel-4.4.55.git] / Documentation / devicetree / bindings / phy / rockchip-dp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
index e3b4809fbe82c4798b7e5bef55e666505d6df527..b837bb8283297f82affc36981a4b69ca6a0eb81a 100644 (file)
--- a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -4,14 +4,21 @@ Rockchip specific extensions to the Analogix Display Port PHY
 Required properties:
 - compatible : should be one of the following supported values:
         - "rockchip.rk3288-dp-phy"
+        - "rockchip.rk3368-dp-phy"
 - clocks: from common clock binding: handle to dp clock.
        of memory mapped region.
 - clock-names: from common clock binding:
        Required elements: "24m"
 - #phy-cells : from the generic PHY bindings, must be 0;
 
+Optional properties
+ - resets : phandle to the reset of eDP 24m clock domain.
+ - reset-names : should be "edp_24m".
+
 Example:
 
+For Rockchip RK3288:
+
 grf: syscon@ff770000 {
        compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 
@@ -24,3 +31,20 @@ grf: syscon@ff770000 {
                #phy-cells = <0>;
        };
 };
+
+For Rockchip RK3368:
+
+grf: syscon@ff770000 {
+       compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
+
+...
+
+       edp_phy: edp-phy {
+               compatible = "rockchip,rk3368-dp-phy";
+               clocks = <&cru SCLK_EDP_24M>;
+               clock-names = "24m";
+               resets = <&cru SRST_EDP_24M>;
+               reset-names = "edp_24m";
+               #phy-cells = <0>;
+       };
+};