/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <186>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x8000000>;
			linux,cma-default;
		};

		/* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
		rockchip_logo: rockchip-logo@00000000 {
			compatible = "rockchip,fb-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};
	};

	ion {
		compatible = "rockchip,ion";
		#address-cells = <1>;
		#size-cells = <0>;

		cma-heap {
			reg = <0x00000000 0x02000000>;
		};

		system-heap {
		};
	};

	isp: isp@ff910000 {
		compatible = "rockchip,rk3368-isp", "rockchip,isp";
		reg = <0x0 0xff910000 0x0 0x10000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&power RK3368_PD_VIO>;
		clocks =
			<&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
			<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
			<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
			<&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
		clock-names =
			"aclk_isp", "hclk_isp", "clk_isp",
			"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
			"clk_cif_pll", "hclk_mipiphy1",
			"pclk_dphyrx", "clk_vio0_noc";
		pinctrl-names =
			"default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
			"isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
			"isp_mipi_fl_prefl", "isp_flash_as_gpio",
			"isp_flash_as_trigger_out";
		pinctrl-0 = <&cif_clkout>;
		pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
		pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
		pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
		pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
		pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
		pinctrl-6 = <&cif_clkout>;
		pinctrl-7 = <&cif_clkout &isp_prelight>;
		pinctrl-8 = <&isp_flash_trigger_as_gpio>;
		pinctrl-9 = <&isp_flash_trigger>;
		rockchip,isp,mipiphy = <2>;
		rockchip,isp,cifphy = <1>;
		rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
		rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
		rockchip,grf = <&grf>;
		rockchip,cru = <&cru>;
		rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
		rockchip,isp,iommu_enable = <1>;
		status = "disabled";
	};

	rga@ff920000 {
		compatible = "rockchip,rga2";
		dev_mode = <1>;
		reg = <0x0 0xff920000 0x0 0x1000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		status = "disabled";
	};

	hdmi: hdmi@ff980000 {
		compatible = "rockchip,rk3368-hdmi";
		reg = <0x0 0xff980000 0x0 0x20000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_HDMI_CTRL>,
			 <&cru SCLK_HDMI_HDCP>,
			 <&cru SCLK_HDMI_CEC>;
		clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
		power-domains = <&power RK3368_PD_VIO>;
		resets = <&cru SRST_HDMI>;
		reset-names = "hdmi";
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
		pinctrl-1 = <&i2c5_gpio>;
		status = "okay";
	};

	dwc_control_usb: dwc-control-usb {
		compatible = "rockchip,rk3368-dwc-control-usb";
		status = "okay";

		rockchip,grf = <&grf>;
		grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "otg_id", "otg_bvalid",
				  "otg_linestate", "host0_linestate";
		clocks = <&cru HCLK_USB_PERI>;
		clock-names = "hclk_usb_peri";

		otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
		rockchip,remote_wakeup;
		rockchip,usb_irq_wakeup;

		usb_bc {
			compatible = "inno,phy";
			regbase = &dwc_control_usb;
			rk_usb,bvalid     = <0x4bc 23 1>;
			rk_usb,iddig      = <0x4bc 26 1>;
			rk_usb,vdmsrcen   = <0x718 12 1>;
			rk_usb,vdpsrcen   = <0x718 11 1>;
			rk_usb,rdmpden    = <0x718 10 1>;
			rk_usb,idpsrcen   = <0x718  9 1>;
			rk_usb,idmsinken  = <0x718  8 1>;
			rk_usb,idpsinken  = <0x718  7 1>;
			rk_usb,dpattach   = <0x4b8 31 1>;
			rk_usb,cpdet      = <0x4b8 30 1>;
			rk_usb,dcpattach  = <0x4b8 29 1>;
		};
	};
};

&display_subsystem {
	status = "okay";
};

&vop {
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&usb_otg {
	status = "okay";
	clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
	clock-names = "sclk_otgphy0", "otg";
	resets = <&cru SRST_USBOTG_AHB>,
		 <&cru SRST_USBOTG_PHY>,
		 <&cru SRST_USBOTG_CON>;
	reset-names = "otg_ahb", "otg_phy", "otg_controller";
	/* 0 - Normal, 1 - Force Host, 2 - Force Device */
	rockchip,usb-mode = <0>;
};

&pinctrl {
	hdmi_i2c {
		hdmii2c_xfer: hdmii2c-xfer {
			rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
					<3 27 RK_FUNC_1 &pcfg_pull_none>;
		};
	};

	hdmi_pin {
		hdmi_cec: hdmi-cec {
			rockchip,pins =	<3 23 RK_FUNC_1 &pcfg_pull_none>;
		};
	};

	i2c5 {
		i2c5_gpio: i2c5-gpio {
			rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
					<3 27 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	isp {
		cif_clkout: cif-clkout {
			rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
		};

		isp_dvp_d2d9: isp-dvp-d2d9 {
			rockchip,pins =
					<1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
					<1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
					<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
					<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
					<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
					<1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
					<1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
					<1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
					<1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
					<1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
					<1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
					<1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
		};

		isp_dvp_d0d1: isp-dvp-d0d1 {
			rockchip,pins =
					<1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
					<1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
		};

		isp_dvp_d10d11:isp_d10d11 {
			rockchip,pins =
					<1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
					<1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
		};

		isp_dvp_d0d7: isp-dvp-d0d7 {
			rockchip,pins =
					<1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
					<1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
					<1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
					<1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
					<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
					<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
					<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
					<1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
		};

		isp_dvp_d4d11: isp-dvp-d4d11 {
			rockchip,pins =
					<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
					<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
					<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
					<1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
					<1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
					<1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
					<1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
					<1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
		};

		isp_shutter: isp-shutter {
			rockchip,pins =
					<3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
					<3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
		};

		isp_flash_trigger: isp-flash-trigger {
			rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
		};

		isp_prelight: isp-prelight {
			rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
		};

		isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
			rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
		};
	};
};