/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/display/rk_fb.h>
#include <dt-bindings/display/mipi_dsi.h>

/ {
	aliases {
		lcdc = &lcdc;
	};

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1";
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <186>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x8000000>;
			linux,cma-default;
		};

		/* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
		rockchip_logo: rockchip-logo@00000000 {
			compatible = "rockchip,fb-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};
	};

	ion {
		compatible = "rockchip,ion";
		#address-cells = <1>;
		#size-cells = <0>;

		cma-heap {
			reg = <0x00000000 0x02000000>;
		};

		system-heap {
		};
	};

	isp: isp@ff910000 {
		compatible = "rockchip,rk3368-isp", "rockchip,isp";
		reg = <0x0 0xff910000 0x0 0x10000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		/*power-domains = <&power PD_VIO>;*/
		clocks =
			<&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
			<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
			<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
			<&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
		clock-names =
			"aclk_isp", "hclk_isp", "clk_isp",
			"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
			"clk_cif_pll", "hclk_mipiphy1",
			"pclk_dphyrx", "clk_vio0_noc";
		pinctrl-names =
			"default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
			"isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
			"isp_mipi_fl_prefl", "isp_flash_as_gpio",
			"isp_flash_as_trigger_out";
		pinctrl-0 = <&cif_clkout>;
		pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
		pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
		pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
		pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
		pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
		pinctrl-6 = <&cif_clkout>;
		pinctrl-7 = <&cif_clkout &isp_prelight>;
		pinctrl-8 = <&isp_flash_trigger_as_gpio>;
		pinctrl-9 = <&isp_flash_trigger>;
		rockchip,isp,mipiphy = <2>;
		rockchip,isp,cifphy = <1>;
		rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
		rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
		rockchip,grf = <&grf>;
		rockchip,cru = <&cru>;
		rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
		rockchip,isp,iommu_enable = <1>;
		status = "disabled";
	};

	rga: rga@ff920000 {
		compatible = "rockchip,rga2";
		dev_mode = <1>;
		reg = <0x0 0xff920000 0x0 0x1000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		status = "disabled";
	};

	fb: fb {
		compatible = "rockchip,rk-fb";
		rockchip,disp-mode = <NO_DUAL>;
		status = "disabled";
	};

	rk_screen: screen {
		compatible = "rockchip,screen";
		status = "disabled";
	};

	lcdc: lcdc@ff930000 {
		compatible = "rockchip,rk3368-lcdc";
		rockchip,grf = <&grf>;
		rockchip,pmugrf = <&pmugrf>;
		rockchip,cru = <&cru>;
		rockchip,prop = <PRMRY>;
		rockchip,pwr18 = <0>;
		rockchip,iommu-enabled = <1>;
		reg = <0x0 0xff930000 0x0 0x10000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
		/*power-domains = <&power PD_VIO>;*/
		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";
	};

	mipi: mipi@ff960000 {
		compatible = "rockchip,rk3368-dsi";
		rockchip,prop = <0>;
		reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
		reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
		clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
		/*power-domains = <&power PD_VIO>;*/
		status = "disabled";
	};

	lvds: lvds@ff968000 {
		compatible = "rockchip,rk3368-lvds";
		rockchip,grf = <&grf>;
		reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
		reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
		clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
		clock-names = "pclk_lvds", "pclk_lvds_ctl";
		/*power-domains = <&power PD_VIO>;*/
		status = "disabled";
	};

	edp: edp@ff970000 {
		compatible = "rockchip,rk32-edp";
		reg = <0x0 0xff970000 0x0 0x4000>;
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
		clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
		/*power-domains = <&power PD_VIO>;*/
		resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
		reset-names = "edp_24m", "edp_apb";
		status = "disabled";
	};

	hdmi: hdmi@ff980000 {
		compatible = "rockchip,rk3368-hdmi";
		reg = <0x0 0xff980000 0x0 0x20000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_HDMI_CTRL>,
			 <&cru SCLK_HDMI_HDCP>,
			 <&cru SCLK_HDMI_CEC>;
		clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
		/*power-domains = <&power PD_VIO>;*/
		resets = <&cru SRST_HDMI>;
		reset-names = "hdmi";
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
		pinctrl-1 = <&i2c5_gpio>;
		status = "disabled";
	};

	iep_mmu: iep-mmu {
		dbgname = "iep";
		compatible = "rockchip,iep_mmu";
		reg = <0x0 0xff900800 0x0 0x100>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iep_mmu";
		status = "disabled";
	};

	vip_mmu: vip-mmu {
		dbgname = "vip";
		compatible = "rockchip,vip_mmu";
		reg = <0x0 0xff950800 0x0 0x100>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vip_mmu";
		status = "disabled";
	};

	vopb_mmu: vopb-mmu {
		dbgname = "vop";
		compatible = "rockchip,vopb_mmu";
		reg = <0x0 0xff930300 0x0 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vop_mmu";
		status = "disabled";
	};

	isp_mmu: isp-mmu {
		dbgname = "isp_mmu";
		compatible = "rockchip,isp_mmu";
		reg = <0x0 0xff914000 0x0 0x100>,
		      <0x0 0xff915000 0x0 0x100>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "isp_mmu";
		status = "disabled";
	};

	hdcp_mmu: hdcp-mmu {
		 dbgname = "hdcp_mmu";
		 compatible = "rockchip,hdcp_mmu";
		 reg = <0x0 0xff940000 0x0 0x100>;
		 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		 interrupt-names = "hdcp_mmu";
		status = "disabled";
	};

	hevc_mmu: hevc-mmu {
		dbgname = "hevc";
		compatible = "rockchip,hevc_mmu";
		reg = <0x0 0xff9a0440 0x0 0x40>,
		      <0x0 0xff9a0480 0x0 0x40>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hevc_mmu";
		status = "disabled";
	};

	vpu_mmu: vpu-mmu {
		dbgname = "vpu";
		compatible = "rockchip,vpu_mmu";
		reg = <0x0 0xff9a0800 0x0 0x100>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vepu_mmu", "vdpu_mmu";
		status = "disabled";
	};

	dwc_control_usb: dwc-control-usb {
		compatible = "rockchip,rk3368-dwc-control-usb";
		rockchip,grf = <&grf>;
		grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "otg_id", "otg_bvalid",
				  "otg_linestate", "host0_linestate";
		clocks = <&cru HCLK_USB_PERI>;
		clock-names = "hclk_usb_peri";
		status = "disabled";

		usb_bc {
			compatible = "inno,phy";
			regbase = &dwc_control_usb;
			rk_usb,bvalid     = <0x4bc 23 1>;
			rk_usb,iddig      = <0x4bc 26 1>;
			rk_usb,vdmsrcen   = <0x718 12 1>;
			rk_usb,vdpsrcen   = <0x718 11 1>;
			rk_usb,rdmpden    = <0x718 10 1>;
			rk_usb,idpsrcen   = <0x718  9 1>;
			rk_usb,idmsinken  = <0x718  8 1>;
			rk_usb,idpsinken  = <0x718  7 1>;
			rk_usb,dpattach   = <0x4b8 31 1>;
			rk_usb,cpdet      = <0x4b8 30 1>;
			rk_usb,dcpattach  = <0x4b8 29 1>;
		};
	};

	pinctrl {
		hdmi_i2c {
			hdmii2c_xfer: hdmii2c-xfer {
				rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
						<3 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		hdmi_pin {
			hdmi_cec: hdmi-cec {
				rockchip,pins =	<3 23 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c5 {
			i2c5_gpio: i2c5-gpio {
				rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
						<3 27 RK_FUNC_GPIO &pcfg_pull_none>;
			};
		};

		lcdc {
			lcdc_lcdc: lcdc-lcdc {
				rockchip,pins =
						<0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
						<0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
						<0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
						<0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
						<0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
						<0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
						<0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
						<0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
						<0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
						<0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
						<0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
						<0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
						<0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
						<0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
						<0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
						<0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
						<0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
						<0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
			};

			lcdc_gpio: lcdc-gpio {
				rockchip,pins =
						<0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
						<0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
						<0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
						<0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
						<0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
						<0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
						<0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
						<0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
						<0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
						<0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
						<0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
						<0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
						<0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
						<0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
						<0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
						<0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
						<0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
						<0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
			};
		};

		isp {
			cif_clkout: cif-clkout {
				rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
			};

			isp_dvp_d2d9: isp-dvp-d2d9 {
				rockchip,pins =
						<1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
						<1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
						<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
						<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
						<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
						<1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
						<1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
						<1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
						<1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
						<1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
						<1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
						<1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
			};

			isp_dvp_d0d1: isp-dvp-d0d1 {
				rockchip,pins =
						<1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
						<1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
			};

			isp_dvp_d10d11:isp_d10d11 {
				rockchip,pins =
						<1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
						<1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
			};

			isp_dvp_d0d7: isp-dvp-d0d7 {
				rockchip,pins =
						<1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
						<1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
						<1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
						<1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
						<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
						<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
						<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
						<1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
			};

			isp_dvp_d4d11: isp-dvp-d4d11 {
				rockchip,pins =
						<1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
						<1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
						<1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
						<1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
						<1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
						<1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
						<1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
						<1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
			};

			isp_shutter: isp-shutter {
				rockchip,pins =
						<3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
						<3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
			};

			isp_flash_trigger: isp-flash-trigger {
				rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
			};

			isp_prelight: isp-prelight {
				rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
			};

			isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
				rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
			};
		};
	};
};

&usb_otg {
	clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
	clock-names = "sclk_otgphy0", "otg";
	resets = <&cru SRST_USBOTG_AHB>,
		 <&cru SRST_USBOTG_PHY>,
		 <&cru SRST_USBOTG_CON>;
	reset-names = "otg_ahb", "otg_phy", "otg_controller";
	/* 0 - Normal, 1 - Force Host, 2 - Force Device */
	rockchip,usb-mode = <0>;
};