/*
 * Copyright (C) 2013 ROCKCHIP, Inc.
 * Author: chenxing <chenxing@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <dt-bindings/clock/rockchip,rk3188.h>

/{
	clocks {
		compatible = "rockchip,rk-clocks";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20000000 0x0100>;

		fixed_rate_cons {
			compatible = "rockchip,rk-fixed-rate-cons";

			xin24m: xin24m {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "xin24m";
				clock-frequency = <24000000>;
			};

			xin12m: xin12m {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clocks = <&xin24m>;
				clock-output-names = "xin12m";
				clock-frequency = <12000000>;
			};

			dummy: dummy {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "dummy";
				clock-frequency = <0>;
			};


			rmii_clkin: rmii_clkin {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "rmii_clkin";
				clock-frequency = <0>;
			};

			clk_hsadc_ext: clk_hsadc_ext {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "clk_hsadc_ext";
				clock-frequency = <0>;
			};

			clk_cif_in: clk_cif_in {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "clk_cif_in";
				clock-frequency = <0>;
			};

		};

		fixed_factor_cons {
			compatible = "rockchip,rk-fixed-factor-cons";

			otgphy0_480m: otgphy0_480m {
				compatible = "fixed-factor-clock";
				clocks = <&clk_gates1 5>;
				clock-output-names = "otgphy0_480m";
				clock-div = <1>;
				clock-mult = <20>;
				#clock-cells = <0>;
			};

			otgphy1_480m: otgphy1_480m {
				compatible = "fixed-factor-clock";
				clocks = <&clk_gates1 6>;
				clock-output-names = "otgphy1_480m";
				clock-div = <1>;
				clock-mult = <20>;
				#clock-cells = <0>;
			};

		};

		clock_regs {
			compatible = "rockchip,rk-clock-regs";
			reg = <0x0000 0x3ff>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			/* PLL control regs */
			pll_cons {
				compatible = "rockchip,rk-pll-cons";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges ;

				clk_apll: pll-clk@0000 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x0000 0x10>;
					mode-reg = <0x0040 0>;
					status-reg = <0x00ac 6>;
					clocks = <&xin24m>;
					clock-output-names = "clk_apll";
					rockchip,pll-type = <CLK_PLL_3188_APLL>;
					#clock-cells = <0>;
				};

				clk_dpll: pll-clk@0010 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x0010 0x10>;
					mode-reg = <0x0040 4>;
					status-reg = <0x00ac 5>;
					clocks = <&xin24m>;
					clock-output-names = "clk_dpll";
					rockchip,pll-type = <CLK_PLL_3188>;
					#clock-cells = <0>;
				};

				clk_cpll: pll-clk@0020 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x0020 0x10>;
					mode-reg = <0x0040 8>;
					status-reg = <0x00ac 7>;
					clocks = <&xin24m>;
					clock-output-names = "clk_cpll";
					rockchip,pll-type = <CLK_PLL_3188>;
					#clock-cells = <0>;
					#clock-init-cells = <1>;
				};

				clk_gpll: pll-clk@0030 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x0030 0x10>;
					mode-reg = <0x0040 12>;
					status-reg = <0x00ac 8>;
					clocks = <&xin24m>;
					clock-output-names = "clk_gpll";
					rockchip,pll-type = <CLK_PLL_3188>;
					#clock-cells = <0>;
					#clock-init-cells = <1>;
				};
			};

			/* Select control regs */
			clk_sel_cons {
				compatible = "rockchip,rk-sel-cons";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				clk_sel_con0: sel-con@0044 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0044 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					aclk_cpu_div: aclk_cpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 5>;
						clocks = <&aclk_cpu>;
						clock-output-names = "aclk_cpu";
						#clock-cells = <0>;
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
					};

					aclk_cpu: aclk_cpu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <5 1>;
						clocks = <&clk_apll>, <&clk_gpll>;
						clock-output-names = "aclk_cpu";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					clk_core_peri: clk_core_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <6 2>;
						clocks = <&clk_core>;
						clock-output-names = "clk_core_peri";
						rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
						rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
						#clock-cells = <0>;
						rockchip,div-relations = <0x0 2
								 0x1 4
								 0x2 8
								 0x3 16>;
					};

					clk_core: clk_core_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 1>;
						clocks = <&clk_apll>,
						       <&clk_gates0 1>;
						clock-output-names = "clk_core";
						rockchip,flags = <(CLK_GET_RATE_NOCACHE |
									CLK_SET_RATE_NO_REPARENT)>;
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					clk_core_div: clk_core_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <9 5>;
						clocks = <&clk_core>;
						clock-output-names = "clk_core";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
						#clock-cells = <0>;
					};

					/* reg[15:14]: reserved */

				};

				clk_sel_con1: sel-con@0048 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0048 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					/* reg[2:0]: reserved */

					aclk_core: aclk_core_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <3 3>;
						clocks = <&clk_core>;
						clock-output-names = "aclk_core";
						#clock-cells = <0>;
						rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
						rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
						rockchip,div-relations = <0x0 1
								 0x1 2
								 0x2 3
								 0x3 4
								 0x4 8>;
					};

					/* reg[7:6]: reserved */

					hclk_cpu: hclk_cpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 2>;
						clocks = <&aclk_cpu>;
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						clock-output-names = "hclk_cpu";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					/* reg[11:10]: reserved */

					pclk_cpu: pclk_cpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <12 2>;
						clocks = <&aclk_cpu>;
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						clock-output-names = "pclk_cpu";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					pclk_ahb2apb: pclk_ahb2apb_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <14 2>;
						clocks = <&hclk_cpu>;
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						clock-output-names = "pclk_ahb2apb";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

				};
				clk_sel_con2: sel-con@004c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x004c 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					/* reg[14:0]: reserved */

					clk_i2s_pll_mux: clk_i2s_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <15 1>;
						clocks = <&clk_gpll>, <&clk_cpll>;
						clock-output-names = "clk_i2s_pll";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};
				};

				clk_sel_con3: sel-con@0050 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0050 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_i2s_div: clk_i2s_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_i2s_pll_mux>;
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						clock-output-names = "clk_i2s_div";
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_i2s: clk_i2s_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_i2s_div>, <&clk_i2s_frac>, <&xin12m>;
						clock-output-names = "clk_i2s";
						rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */
				};

				/* clk_sel_con4: reserved */

				clk_sel_con5: sel-con@0058 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0058 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_spdif_div: clk_spdif_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_i2s_pll_mux>;
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						clock-output-names = "clk_spdif_div";
						/* spdif same as i2s */
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_spdif: clk_spdif_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_spdif_div>, <&clk_spdif_frac>, <&xin12m>;
						clock-output-names = "clk_spdif";
						rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */
				};

				/* clk_sel_con6: reserved */

				clk_sel_con7: sel-con@0060 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0060 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_i2s_frac: clk_i2s_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_i2s_div>;
						clock-output-names = "clk_i2s_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						#clock-cells = <0>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_I2S_FRAC>;
					};
				};

				/* clk_sel_con8: reserved */

				clk_sel_con9: sel-con@0068 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0068 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_spdif_frac: clk_spdif_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_spdif_div>;
						clock-output-names = "clk_spdif_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						#clock-cells = <0>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_I2S_FRAC>;
					};
				};

				clk_sel_con10: sel-con@006c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x006c 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					aclk_peri_div: aclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 5>;
						clocks = <&aclk_peri>;
						clock-output-names = "aclk_peri";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
						#clock-init-cells = <1>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
					};

					/* reg[7:5]: reserved */

					hclk_peri: hclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 2>;
						clocks = <&aclk_peri>;
						clock-output-names = "hclk_peri";
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					/* reg[11:10]: reserved */

					pclk_peri: pclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <12 2>;
						clocks = <&aclk_peri>;
						clock-output-names = "pclk_peri";
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					/* reg[14]: reserved */

					aclk_peri: aclk_peri_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <15 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "aclk_peri";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};
				};

				clk_sel_con11: sel-con@0070 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0070 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_sdmmc: clk_sdmmc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 6>;
						clocks = <&hclk_peri>;
						clock-output-names = "clk_sdmmc";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_EVENDIV>;
						#clock-cells = <0>;
					};

					/* reg[7:6]: reserved */

					clk_ehci1phy12m: ehci1_phy_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 6>;
						clocks = <&clk_ehci1phy480m>;
						clock-output-names = "clk_ehci1phy12m";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[15:14]: reserved */

				};

				clk_sel_con12: sel-con@0074 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0074 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_sdio: clk_sdio_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 6>;
						clocks = <&hclk_peri>;
						clock-output-names = "clk_sdio";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_EVENDIV>;
						#clock-cells = <0>;
					};

					/* reg[7:6]: reserved */

					clk_emmc: clk_emmc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 6>;
						clocks = <&hclk_peri>;
						clock-output-names = "clk_emmc";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_EVENDIV>;
						#clock-cells = <0>;
					};

					/* reg[14]: reserved */

					clk_uart_pll_mux: clk_uart_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <15 1>;
						clocks = <&clk_gpll>, <&clk_cpll>;
						clock-output-names = "clk_uart_pll";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};
				};

				clk_sel_con13: sel-con@0078 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0078 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_uart0_div: clk_uart0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_uart_pll_mux>;
						clock-output-names = "clk_uart0_div";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_uart0: clk_uart0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_uart0_div>, <&clk_uart0_frac>,
						       <&xin24m>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_UART>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_uart0";
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */

				};

				clk_sel_con14: sel-con@007c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x007c 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_uart1_div: clk_uart1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_uart_pll_mux>;
						clock-output-names = "clk_uart1_div";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_uart1: clk_uart1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_uart1_div>, <&clk_uart1_frac>,
						       <&xin24m>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_UART>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_uart1";
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */

				};

				clk_sel_con15: sel-con@0080 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0080 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_uart2_div: clk_uart2_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_uart_pll_mux>;
						clock-output-names = "clk_uart2_div";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_uart2: clk_uart2_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_uart2_div>, <&clk_uart2_frac>,
						       <&xin24m>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_UART>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_uart2";
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */

				};

				clk_sel_con16: sel-con@0084 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0084 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_uart3_div: clk_uart3_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&clk_uart_pll_mux>;
						clock-output-names = "clk_uart3_div";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[7]: reserved */

					clk_uart3: clk_uart3_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 2>;
						clocks = <&clk_uart3_div>, <&clk_uart3_frac>,
						       <&xin24m>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_UART>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_uart3";
						#clock-cells = <0>;
					};

					/* reg[15:10]: reserved */

				};

				clk_sel_con17: sel-con@0088 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0088 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_uart0_frac: clk_uart0_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_uart0_div>;
						clock-output-names = "clk_uart0_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_FRAC>;
						#clock-cells = <0>;
					};
				};
				clk_sel_con18: sel-con@008c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x008c 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_uart1_frac: clk_uart1_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_uart1_div>;
						clock-output-names = "clk_uart1_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_FRAC>;
						#clock-cells = <0>;
					};
				};
				clk_sel_con19: sel-con@0090 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0090 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_uart2_frac: clk_uart2_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_uart2_div>;
						clock-output-names = "clk_uart2_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_FRAC>;
						#clock-cells = <0>;
					};
				};
				clk_sel_con20: sel-con@0094 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0094 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_uart3_frac: clk_uart3_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_uart3_div>;
						clock-output-names = "clk_uart3_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_FRAC>;
						#clock-cells = <0>;
					};
				};

				clk_sel_con21: sel-con@0098 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x0098 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_mac_pll_mux: clk_mac_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 1>;
						clocks = <&clk_gpll>, <&clk_dpll>;
						clock-output-names = "clk_mac_pll";
						#clock-cells = <0>;
					};

					/* reg[3:1]: reserved */

					clk_mac: clk_mac_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <4 1>;
						clocks = <&clk_mac_pll_mux>, <&rmii_clkin>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MAC_REF>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_mac";
						#clock-cells = <0>;
					};

					/* reg[7:5]: reserved */

					clk_mac_pll_div: clk_mac_pll_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 5>;
						clocks = <&clk_mac_pll_mux>;
						clock-output-names = "clk_mac_pll";
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};

					/* reg[15:13]: reserved */
				};

				clk_sel_con22: sel-con@009c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x009c 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_hsadc_pll_mux: clk_hsadc_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 1>;
						clocks = <&clk_gpll>, <&clk_cpll>;
						clock-output-names = "clk_hsadc_pll";
						#clock-cells = <0>;
					};

					/* reg[3:1]: reserved */

					clk_hsadc: clk_hsadc_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <4 2>;
						clocks = <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
							 <&clk_hsadc_ext>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_HSADC>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_hsadc";
						#clock-cells = <0>;
					};

					/* reg[6]: reserved */

					clk_hsadc_inv: clk_hsadc_inv {
						compatible = "rockchip,rk3188-inv-con";
						rockchip,bits = <7 1>;
						clocks = <&clk_hsadc>;
					};

					clk_hsadc_div: clk_hsadc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 8>;
						clocks = <&clk_hsadc_pll_mux>;
						clock-output-names = "clk_hsadc_pll";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};
				};

				clk_sel_con23: sel-con@00a0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00a0 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_hsadc_frac: clk_hsadc_frac{
						compatible = "rockchip,rk3188-frac-con";
						clocks = <&clk_hsadc_pll_mux>;
						clock-output-names = "clk_hsadc_frac";
						/* numerator	denominator */
						rockchip,bits = <0 32>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_FRAC>;
						#clock-cells = <0>;
					};
				};

				clk_sel_con24: sel-con@00a4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00a4 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;
					clk_saradc: clk_saradc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 8>;
						clocks = <&xin24m>;
						clock-output-names = "clk_saradc";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};
				};

				clk_sel_con25: sel-con@00a8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00a8 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_spi0: clk_spi0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 7>;
						clocks = <&pclk_peri>;
						clock-output-names = "clk_spi0";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};
					/* reg[7]: reserved */
					clk_spi1: clk_spi1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 7>;
						clocks = <&pclk_peri>;
						clock-output-names = "clk_spi1";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						#clock-cells = <0>;
					};
					/* reg[15]: reserved */
				};

				clk_sel_con26: sel-con@00ac {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00ac 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_ddr_div: clk_ddr_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 2>;
						clocks = <&clk_ddr>;
						clock-output-names = "clk_ddr";
						rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
						rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
						#clock-cells = <0>;
					};

					/* reg[7:2]: reserved */

					clk_ddr: clk_ddr_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <8 1>;
						clocks = <&clk_dpll>,
						       <&clk_gates1 7>;
						clock-output-names = "clk_ddr";
						rockchip,flags = <(CLK_GET_RATE_NOCACHE |
									CLK_SET_RATE_NO_REPARENT)>;
						#clock-cells = <0>;
					};

					/* reg[15:9]: reserved */
				};

				clk_sel_con27: sel-con@00b0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00b0 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					dclk_lcdc0: dclk_lcdc0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "dclk_lcdc0";
						#clock-cells = <0>;
					};

					/* reg[7:1]: reserved */

					dclk_lcdc0_div: dclk_lcdc0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 8>;
						clocks = <&dclk_lcdc0>;
						clock-output-names = "dclk_lcdc0";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_EVENDIV>;
						#clock-cells = <0>;
					};
				};


				clk_sel_con28: sel-con@00b4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00b4 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					dclk_lcdc1: dclk_lcdc1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "dclk_lcdc1";
						#clock-cells = <0>;
					};

					/* reg[7:1]: reserved */

					dclk_lcdc1_div: dclk_lcdc1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 8>;
						clocks = <&dclk_lcdc1>;
						clock-output-names = "dclk_lcdc1";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_EVENDIV>;
						#clock-cells = <0>;
					};
				};

				clk_sel_con29: sel-con@00b8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00b8 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					cif_out_pll_mux: cif_out_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "cif_out_pll";
						#clock-cells = <0>;
					};

					cif0_out_div: cif0_out_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <1 5>;
						clocks = <&cif_out_pll_mux>;
						clock-output-names = "cif_out_pll";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[6]: reserved */

					clk_cif0: cif0_out_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <7 1>;
						clocks = <&cif_out_pll_mux>, <&xin24m>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_CIFOUT>;
						rockchip,flags = <CLK_SET_RATE_PARENT>;
						clock-output-names = "clk_cif0";
						#clock-cells = <0>;
					};

					/* reg[15:8]: reserved */
				};

				clk_sel_con30: sel-con@00bc {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00bc 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					clk_ehci1phy480m: clk_ehci1phy480m_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0 2>;
						clocks = <&otgphy0_480m>, <&otgphy1_480m>,
							 <&clk_gpll>, <&clk_cpll>;
						clock-output-names = "clk_ehci1phy480m";
						#clock-cells = <0>;
					};

					/* reg[7:2]: reserved */

					/* inv here?????? */

					/* reg[15:9]: reserved */
				};

				clk_sel_con31: sel-con@00c0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00c0 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					aclk_lcdc0_pre_div: aclk_lcdc0_pre_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 5>;
						clocks = <&aclk_lcdc0>;
						clock-output-names = "aclk_lcdc0";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[6:5]: reserved */

					aclk_lcdc0: aclk_lcdc0_pre_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <7 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "aclk_lcdc0";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					aclk_lcdc1_pre_div: aclk_lcdc1_pre_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 5>;
						clocks = <&aclk_lcdc1>;
						clock-output-names = "aclk_lcdc1";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[14:13]: reserved */

					aclk_lcdc1: aclk_lcdc1_pre_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <15 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "aclk_lcdc1";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};
				};

				clk_sel_con32: sel-con@00c4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00c4 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					aclk_vepu_div: aclk_vepu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 5>;
						clocks = <&clk_vepu>;
						clock-output-names = "clk_vepu";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[6:5]: reserved */

					clk_vepu: aclk_vepu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <7 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "clk_vepu";
						#clock-cells = <0>;
					};

					aclk_vdpu_div: aclk_vdpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <8 5>;
						clocks = <&clk_vdpu>;
						clock-output-names = "clk_vdpu";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[14:13]: reserved */

					clk_vdpu: aclk_vdpu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <15 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "clk_vdpu";
						#clock-cells = <0>;
					};
				};

				clk_sel_con34: sel-con@00cc {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x00cc 0x4>;
					#address-cells = <1>;
					#size-cells = <1>;

					aclk_gpu_div: aclk_gpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0 5>;
						clocks = <&clk_gpu>;
						clock-output-names = "clk_gpu";
						rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
						rockchip,clkops-idx =
							<CLKOPS_RATE_MUX_DIV>;
						#clock-cells = <0>;
					};

					/* reg[6:5]: reserved */

					clk_gpu: aclk_gpu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <7 1>;
						clocks = <&clk_cpll>, <&clk_gpll>;
						clock-output-names = "clk_gpu";
						#clock-cells = <0>;
						#clock-init-cells = <1>;
					};

					/* reg[15:8]: reserved */
				};
			};

			/* Gate control regs */
			clk_gate_cons {
				compatible = "rockchip,rk-gate-cons";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges ;

				clk_gates0: gate-clk@00d0 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00d0 0x4>;
					clocks = <&clk_core_peri>,	<&clk_gpll>,
						 <&clk_dpll>,		<&aclk_cpu>,

						 <&hclk_cpu>,		<&pclk_cpu>,
						 <&pclk_cpu>,		<&aclk_core>,

						 <&dummy>,		<&clk_i2s_div>,
						 <&clk_i2s_frac>,	<&dummy>,

						 <&dummy>,		<&clk_spdif_div>,
						 <&clk_spdif_frac>,	<&dummy>;

					clock-output-names =
						"clk_core_peri",	"clk_arm_gpll",
						"clk_dpll",		"aclk_cpu",

						"hclk_cpu",		"pclk_cpu",
						"g_atclk_cpu",		"aclk_core",

						"reserved",		"clk_i2s_div",
						"clk_i2s_frac",		"reserved",

						"reserved",		"clk_spdif_div",
						"clk_spdif_frac",	"g_testclk";
						rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>;

					#clock-cells = <1>;
				};

				clk_gates1: gate-clk@00d4 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00d4 0x4>;
					clocks = <&xin24m>,		<&xin24m>,
						 <&xin24m>,		<&dummy>,

						 <&aclk_lcdc1>,		<&xin24m>,
						 <&xin24m>,		<&clk_gpll>,

						 <&clk_uart0_div>,	<&clk_uart0_frac>,
						 <&clk_uart1_div>,	<&clk_uart1_frac>,

						 <&clk_uart2_div>,	<&clk_uart2_frac>,
						 <&clk_uart3_div>,	<&clk_uart3_frac>;

					clock-output-names =
						"timer0",		"timer1",
						"timer3",		"g_jtag",

						"aclk_lcdc1",		"g_otgphy0",
						"g_otgphy1",		"clk_ddr_gpll",

						"clk_uart0_div",	"clk_uart0_frac",
						"clk_uart1_div",	"clk_uart1_frac",

						"clk_uart2_div",	"clk_uart2_frac",
						"clk_uart3_div",	"clk_uart3_frac";
						rockchip,suspend-clkgating-setting=<0x0 0x0>;

					#clock-cells = <1>;
				};

				clk_gates2: gate-clk@00d8 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00d8 0x4>;
					clocks = <&aclk_peri>,	<&aclk_peri>,
						 <&hclk_peri>,		<&pclk_peri>,

						 <&hclk_peri>,		<&clk_mac_pll_mux>,
						 <&clk_hsadc_pll_mux>,	<&clk_hsadc_frac>,

						 <&clk_saradc>,		<&clk_spi0>,
						 <&clk_spi1>,		<&clk_sdmmc>,

						 <&dummy>,		<&clk_sdio>,
						 <&clk_emmc>,		<&dummy>;

					clock-output-names =
						"aclk_peri",		"g_aclk_peri",
						"hclk_peri",		"pclk_peri",

						"g_smc_src",		"clk_mac_pll",
						"clk_hsadc_pll",	"clk_hsadc_frac",

						"clk_saradc",		"clk_spi0",
						"clk_spi1",		"clk_sdmmc",

						"g_mac_lbtest",		"clk_sdio",
						"clk_emmc",		"reserved";
						//rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
						rockchip,suspend-clkgating-setting=<0x1f 0x1b>;

					#clock-cells = <1>;
				};

				clk_gates3: gate-clk@00dc {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00dc 0x4>;
					clocks = <&aclk_lcdc0>,		<&dclk_lcdc0>,
						 <&dclk_lcdc1>,		<&clk_cif_in>,

						 <&xin24m>,			<&xin24m>,
						 <&clk_ehci1phy480m>,	<&clk_cif0>,

						 <&xin24m>,		<&clk_vepu>,
						 <&clk_vepu>,		<&clk_vdpu>,

						 <&clk_vdpu>,		<&dummy>,
						 <&xin24m>,		<&clk_gpu>;

					clock-output-names =
						"aclk_lcdc0",		"dclk_lcdc0",
						"dclk_lcdc1",		"g_clk_cif_in",

						/*
						 * FIXME: cif_out_pll can be set to
						 * clk_cif as virtual
						 */
						"timer2",		"timer4",
						"clk_ehci1phy480m",	"clk_cif0",

						"timer5",		"clk_vepu",
						"g_h_vepu",		"clk_vdpu",

						"g_h_vdpu",		"reserved",
						"timer6",		"clk_gpu";
					rockchip,suspend-clkgating-setting=<0x0 0x0>;

					#clock-cells = <1>;
				};

				clk_gates4: gate-clk@00e0 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00e0 0x4>;
					clocks = <&hclk_peri>,		<&pclk_peri>,
						 <&aclk_peri>,		<&aclk_peri>,

						 <&aclk_peri>,		<&hclk_peri>,
						 <&hclk_peri>,		<&hclk_peri>,

						 <&hclk_cpu>,		<&hclk_cpu>,
						 <&aclk_cpu>,		<&dummy>,

						 <&aclk_cpu>,		<&dummy>,
						 <&hclk_cpu>,		<&hclk_cpu>;

					/*
					 * g_ap: gate_aclk_peri_...
					 * g_hp: gate_hclk_peri_...
					 * g_pp: gate_pclk_peri_...
					 */
					clock-output-names =
						"g_hp_axi_matrix",	"g_pp_axi_matrix",
						"g_a_cpu_peri",		"g_ap_axi_matrix",

						"g_a_peri_niu",		"g_h_usb_peri",
						"g_hp_ahb_arbi",	"g_h_emem_peri",

						"g_h_cpubus",		"g_h_ahb2apb",
						"g_a_strc_sys",		"reserved",

						"g_a_intmem",		"reserved",
						"g_h_imem1",		"g_h_imem0";

					//rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
					rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
					#clock-cells = <1>;
				};

				clk_gates5: gate-clk@00e4 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00e4 0x4>;
					clocks = <&aclk_cpu>,		<&aclk_peri>,
						 <&pclk_cpu>,		<&pclk_cpu>,

						 <&pclk_cpu>,		<&pclk_cpu>,
						 <&hclk_cpu>,		<&pclk_cpu>,

						 <&aclk_peri>,		<&hclk_peri>,
						 <&hclk_peri>,		<&hclk_peri>,

						 <&hclk_peri>,		<&hclk_peri>;

					clock-output-names =
						"g_a_dmac1",		"g_a_dmac2",
						"g_p_efuse",		"g_p_tzpc",

						"g_p_grf",		"g_p_pmu",
						"g_h_rom",		"g_p_ddrupctl",

						"g_a_smc",		"g_h_nandc",
						"g_h_sdmmc0",		"g_h_sdio",

						"g_h_emmc",		"g_h_otg0";
					rockchip,suspend-clkgating-setting=<0x80 0x80>;

					#clock-cells = <1>;
				};

				clk_gates6: gate-clk@00e8 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00e8 0x4>;
					clocks = <&clk_gates6 13>,	<&hclk_cpu>,
						 <&hclk_cpu>,		<&clk_gates9 5>,

						 <&hclk_cpu>,		<&clk_gates6 13>,
						 <&dummy>,		<&dummy>,

						 <&clk_gates6 13>,	<&hclk_cpu>,
						 <&hclk_cpu>,		<&clk_gates9 5>,

						 <&hclk_cpu>,		<&aclk_lcdc0>;

					clock-output-names =
						"g_a_lcdc0",		"g_h_lcdc0",
						"g_h_lcdc1",		"g_a_lcdc1",

						"g_h_cif0",		"g_a_cif0",
						"reserved",		"reserved",

						"g_a_ipp",		"g_h_ipp",
						"g_h_rga",		"g_a_rga",

						"g_h_vio_bus",		"g_a_vio0";

					rockchip,suspend-clkgating-setting=<0x0 0x0>;
					#clock-cells = <1>;
				};

				clk_gates7: gate-clk@00ec {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00ec 0x4>;
					clocks = <&hclk_peri>,		<&hclk_cpu>,
						 <&hclk_cpu>,		<&hclk_peri>,

						 <&hclk_peri>,		<&hclk_peri>,
						 <&hclk_peri>,		<&pclk_cpu>,

						 <&dummy>,		<&pclk_cpu>,
						 <&pclk_cpu>,		<&pclk_peri>,

						 <&pclk_peri>,		<&pclk_peri>,
						 <&pclk_peri>,		<&pclk_peri>;

					clock-output-names =
						"g_h_emac",		"g_h_spdif",
						"g_h_i2s0_2ch",		"g_h_otg1",

						"g_h_ehci1",		"g_h_hsadc",
						"g_h_pidf",		"g_p_timer0",

						"reserved",		"g_p_timer2",
						"g_p_pwm01",		"g_p_pwm23",

						"g_p_spi0",		"g_p_spi1",
						"g_p_saradc",		"g_p_wdt";
					rockchip,suspend-clkgating-setting=<0x0 0x0>;

					#clock-cells = <1>;
				};

				clk_gates8: gate-clk@00f0 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00f0 0x4>;
					clocks = <&pclk_ahb2apb>,	<&pclk_ahb2apb>,
						 <&pclk_peri>,		<&pclk_peri>,

						 <&pclk_cpu>,		<&pclk_cpu>,
						 <&pclk_peri>,		<&pclk_peri>,

						 <&pclk_peri>,		<&pclk_cpu>,
						 <&pclk_cpu>,		<&pclk_cpu>,

						 <&pclk_peri>,		<&aclk_peri>;

					clock-output-names =
						"g_p_uart0",		"g_p_uart1",
						"g_p_uart2",		"g_p_uart3",

						"g_p_i2c0",		"g_p_i2c1",
						"g_p_i2c2",		"g_p_i2c3",

						"g_p_i2c4",		"g_p_gpio0",
						"g_p_gpio1",		"g_p_gpio2",

						"g_p_gpio3",		"g_a_gps";
						rockchip,suspend-clkgating-setting=<0x200 0x200>;

					#clock-cells = <1>;
				};

				clk_gates9: gate-clk@00f4 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x00f4 0x4>;
					clocks = <&clk_core>,		<&pclk_cpu>,
						 <&clk_gates0 6>,	<&clk_gates0 6>,

						 <&clk_core>,		<&aclk_lcdc1>,
						 <&pclk_cpu>,		<&clk_gpu>;

					clock-output-names =
						"g_clk_core_dbg",	"g_p_dbg",
						"g_clk_trace",		"g_atclk",

						"g_clk_l2c",		"g_a_vio1",
						"g_p_ddrpubl",		"g_a_gpu";
					rockchip,suspend-clkgating-setting=<0x50 0x50>;

					#clock-cells = <1>;
				};
			};
		};
	};
};