1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_device.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
24 #include "rockchip_i2s.h"
26 #define DRV_NAME "rockchip-i2s"
39 struct snd_dmaengine_dai_dma_data capture_dma_data;
40 struct snd_dmaengine_dai_dma_data playback_dma_data;
42 struct regmap *regmap;
46 * Used to indicate the tx/rx status.
47 * I2S controller hopes to start the tx and rx together,
48 * also to stop them when they are both try to stop.
53 const struct rk_i2s_pins *pins;
56 static int i2s_runtime_suspend(struct device *dev)
58 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
60 clk_disable_unprepare(i2s->mclk);
65 static int i2s_runtime_resume(struct device *dev)
67 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
70 ret = clk_prepare_enable(i2s->mclk);
72 dev_err(i2s->dev, "clock enable failed %d\n", ret);
79 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
81 return snd_soc_dai_get_drvdata(dai);
84 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
90 regmap_update_bits(i2s->regmap, I2S_DMACR,
91 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
93 regmap_update_bits(i2s->regmap, I2S_XFER,
94 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
95 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
99 i2s->tx_start = false;
101 regmap_update_bits(i2s->regmap, I2S_DMACR,
102 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
104 if (!i2s->rx_start) {
105 regmap_update_bits(i2s->regmap, I2S_XFER,
111 regmap_update_bits(i2s->regmap, I2S_CLR,
112 I2S_CLR_TXC | I2S_CLR_RXC,
113 I2S_CLR_TXC | I2S_CLR_RXC);
115 regmap_read(i2s->regmap, I2S_CLR, &val);
117 /* Should wait for clear operation to finish */
119 regmap_read(i2s->regmap, I2S_CLR, &val);
122 dev_warn(i2s->dev, "fail to clear\n");
130 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
132 unsigned int val = 0;
136 regmap_update_bits(i2s->regmap, I2S_DMACR,
137 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
139 regmap_update_bits(i2s->regmap, I2S_XFER,
140 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
141 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
143 i2s->rx_start = true;
145 i2s->rx_start = false;
147 regmap_update_bits(i2s->regmap, I2S_DMACR,
148 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
150 if (!i2s->tx_start) {
151 regmap_update_bits(i2s->regmap, I2S_XFER,
157 regmap_update_bits(i2s->regmap, I2S_CLR,
158 I2S_CLR_TXC | I2S_CLR_RXC,
159 I2S_CLR_TXC | I2S_CLR_RXC);
161 regmap_read(i2s->regmap, I2S_CLR, &val);
163 /* Should wait for clear operation to finish */
165 regmap_read(i2s->regmap, I2S_CLR, &val);
168 dev_warn(i2s->dev, "fail to clear\n");
176 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
179 struct rk_i2s_dev *i2s = to_info(cpu_dai);
180 unsigned int mask = 0, val = 0;
182 mask = I2S_CKR_MSS_MASK;
183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
184 case SND_SOC_DAIFMT_CBS_CFS:
185 /* Set source clock in Master mode */
186 val = I2S_CKR_MSS_MASTER;
187 i2s->is_master_mode = true;
189 case SND_SOC_DAIFMT_CBM_CFM:
190 val = I2S_CKR_MSS_SLAVE;
191 i2s->is_master_mode = false;
197 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
199 mask = I2S_TXCR_IBM_MASK;
200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
201 case SND_SOC_DAIFMT_RIGHT_J:
202 val = I2S_TXCR_IBM_RSJM;
204 case SND_SOC_DAIFMT_LEFT_J:
205 val = I2S_TXCR_IBM_LSJM;
207 case SND_SOC_DAIFMT_I2S:
208 val = I2S_TXCR_IBM_NORMAL;
214 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
216 mask = I2S_RXCR_IBM_MASK;
217 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
218 case SND_SOC_DAIFMT_RIGHT_J:
219 val = I2S_RXCR_IBM_RSJM;
221 case SND_SOC_DAIFMT_LEFT_J:
222 val = I2S_RXCR_IBM_LSJM;
224 case SND_SOC_DAIFMT_I2S:
225 val = I2S_RXCR_IBM_NORMAL;
231 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
236 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
237 struct snd_pcm_hw_params *params,
238 struct snd_soc_dai *dai)
240 struct rk_i2s_dev *i2s = to_info(dai);
241 struct snd_soc_pcm_runtime *rtd = substream->private_data;
242 unsigned int val = 0;
243 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
245 if (i2s->is_master_mode) {
246 mclk_rate = clk_get_rate(i2s->mclk);
247 bclk_rate = 2 * 32 * params_rate(params);
248 if (bclk_rate && mclk_rate % bclk_rate)
251 div_bclk = mclk_rate / bclk_rate;
252 div_lrck = bclk_rate / params_rate(params);
253 regmap_update_bits(i2s->regmap, I2S_CKR,
255 I2S_CKR_MDIV(div_bclk));
257 regmap_update_bits(i2s->regmap, I2S_CKR,
260 I2S_CKR_TSD(div_lrck) |
261 I2S_CKR_RSD(div_lrck));
264 switch (params_format(params)) {
265 case SNDRV_PCM_FORMAT_S8:
266 val |= I2S_TXCR_VDW(8);
268 case SNDRV_PCM_FORMAT_S16_LE:
269 val |= I2S_TXCR_VDW(16);
271 case SNDRV_PCM_FORMAT_S20_3LE:
272 val |= I2S_TXCR_VDW(20);
274 case SNDRV_PCM_FORMAT_S24_LE:
275 val |= I2S_TXCR_VDW(24);
277 case SNDRV_PCM_FORMAT_S32_LE:
278 val |= I2S_TXCR_VDW(32);
284 switch (params_channels(params)) {
298 dev_err(i2s->dev, "invalid channel: %d\n",
299 params_channels(params));
303 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
304 regmap_update_bits(i2s->regmap, I2S_RXCR,
305 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
308 regmap_update_bits(i2s->regmap, I2S_TXCR,
309 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
312 if (!IS_ERR(i2s->grf) && i2s->pins) {
313 regmap_read(i2s->regmap, I2S_TXCR, &val);
314 val &= I2S_TXCR_CSR_MASK;
318 val = I2S_IO_4CH_OUT_6CH_IN;
321 val = I2S_IO_6CH_OUT_4CH_IN;
324 val = I2S_IO_8CH_OUT_2CH_IN;
327 val = I2S_IO_2CH_OUT_8CH_IN;
331 val <<= i2s->pins->shift;
332 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
333 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
336 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
338 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
341 val = I2S_CKR_TRCM_TXRX;
342 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
343 val = I2S_CKR_TRCM_TXONLY;
345 regmap_update_bits(i2s->regmap, I2S_CKR,
351 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
352 int cmd, struct snd_soc_dai *dai)
354 struct rk_i2s_dev *i2s = to_info(dai);
358 case SNDRV_PCM_TRIGGER_START:
359 case SNDRV_PCM_TRIGGER_RESUME:
360 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
361 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
362 rockchip_snd_rxctrl(i2s, 1);
364 rockchip_snd_txctrl(i2s, 1);
366 case SNDRV_PCM_TRIGGER_SUSPEND:
367 case SNDRV_PCM_TRIGGER_STOP:
368 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
369 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
370 rockchip_snd_rxctrl(i2s, 0);
372 rockchip_snd_txctrl(i2s, 0);
382 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
383 unsigned int freq, int dir)
385 struct rk_i2s_dev *i2s = to_info(cpu_dai);
388 ret = clk_set_rate(i2s->mclk, freq);
390 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
395 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
397 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
399 dai->capture_dma_data = &i2s->capture_dma_data;
400 dai->playback_dma_data = &i2s->playback_dma_data;
405 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
406 .hw_params = rockchip_i2s_hw_params,
407 .set_sysclk = rockchip_i2s_set_sysclk,
408 .set_fmt = rockchip_i2s_set_fmt,
409 .trigger = rockchip_i2s_trigger,
412 static struct snd_soc_dai_driver rockchip_i2s_dai = {
413 .probe = rockchip_i2s_dai_probe,
415 .stream_name = "Playback",
418 .rates = SNDRV_PCM_RATE_8000_192000,
419 .formats = (SNDRV_PCM_FMTBIT_S8 |
420 SNDRV_PCM_FMTBIT_S16_LE |
421 SNDRV_PCM_FMTBIT_S20_3LE |
422 SNDRV_PCM_FMTBIT_S24_LE |
423 SNDRV_PCM_FMTBIT_S32_LE),
426 .stream_name = "Capture",
429 .rates = SNDRV_PCM_RATE_8000_192000,
430 .formats = (SNDRV_PCM_FMTBIT_S8 |
431 SNDRV_PCM_FMTBIT_S16_LE |
432 SNDRV_PCM_FMTBIT_S20_3LE |
433 SNDRV_PCM_FMTBIT_S24_LE |
434 SNDRV_PCM_FMTBIT_S32_LE),
436 .ops = &rockchip_i2s_dai_ops,
437 .symmetric_rates = 1,
440 static const struct snd_soc_component_driver rockchip_i2s_component = {
444 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
461 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
480 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
491 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
499 static const struct reg_default rockchip_i2s_reg_defaults[] = {
507 static const struct regmap_config rockchip_i2s_regmap_config = {
511 .max_register = I2S_RXDR,
512 .reg_defaults = rockchip_i2s_reg_defaults,
513 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
514 .writeable_reg = rockchip_i2s_wr_reg,
515 .readable_reg = rockchip_i2s_rd_reg,
516 .volatile_reg = rockchip_i2s_volatile_reg,
517 .precious_reg = rockchip_i2s_precious_reg,
518 .cache_type = REGCACHE_FLAT,
521 static const struct rk_i2s_pins rk3399_i2s_pins = {
522 .reg_offset = 0xe220,
526 static const struct of_device_id rockchip_i2s_match[] = {
527 { .compatible = "rockchip,rk3066-i2s", },
528 { .compatible = "rockchip,rk3188-i2s", },
529 { .compatible = "rockchip,rk3288-i2s", },
530 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
534 static int rockchip_i2s_probe(struct platform_device *pdev)
536 struct device_node *node = pdev->dev.of_node;
537 const struct of_device_id *of_id;
538 struct rk_i2s_dev *i2s;
539 struct snd_soc_dai_driver *soc_dai;
540 struct resource *res;
545 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
547 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
551 i2s->dev = &pdev->dev;
553 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
554 if (!IS_ERR(i2s->grf)) {
555 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
556 if (!of_id || !of_id->data)
559 i2s->pins = of_id->data;
562 /* try to prepare related clocks */
563 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
564 if (IS_ERR(i2s->hclk)) {
565 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
566 return PTR_ERR(i2s->hclk);
568 ret = clk_prepare_enable(i2s->hclk);
570 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
574 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
575 if (IS_ERR(i2s->mclk)) {
576 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
577 return PTR_ERR(i2s->mclk);
580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 regs = devm_ioremap_resource(&pdev->dev, res);
583 return PTR_ERR(regs);
585 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
586 &rockchip_i2s_regmap_config);
587 if (IS_ERR(i2s->regmap)) {
589 "Failed to initialise managed register map\n");
590 return PTR_ERR(i2s->regmap);
593 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
594 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
595 i2s->playback_dma_data.maxburst = 4;
597 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
598 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 i2s->capture_dma_data.maxburst = 4;
601 dev_set_drvdata(&pdev->dev, i2s);
603 pm_runtime_enable(&pdev->dev);
604 if (!pm_runtime_enabled(&pdev->dev)) {
605 ret = i2s_runtime_resume(&pdev->dev);
610 soc_dai = devm_kzalloc(&pdev->dev,
611 sizeof(*soc_dai), GFP_KERNEL);
615 memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
616 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
617 if (val >= 2 && val <= 8)
618 soc_dai->playback.channels_max = val;
621 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
622 if (val >= 2 && val <= 8)
623 soc_dai->capture.channels_max = val;
626 ret = devm_snd_soc_register_component(&pdev->dev,
627 &rockchip_i2s_component,
631 dev_err(&pdev->dev, "Could not register DAI\n");
635 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
637 dev_err(&pdev->dev, "Could not register PCM\n");
644 if (!pm_runtime_status_suspended(&pdev->dev))
645 i2s_runtime_suspend(&pdev->dev);
647 pm_runtime_disable(&pdev->dev);
652 static int rockchip_i2s_remove(struct platform_device *pdev)
654 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
656 pm_runtime_disable(&pdev->dev);
657 if (!pm_runtime_status_suspended(&pdev->dev))
658 i2s_runtime_suspend(&pdev->dev);
660 clk_disable_unprepare(i2s->mclk);
661 clk_disable_unprepare(i2s->hclk);
666 #ifdef CONFIG_PM_SLEEP
667 static int rockchip_i2s_suspend(struct device *dev)
669 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
671 regcache_mark_dirty(i2s->regmap);
676 static int rockchip_i2s_resume(struct device *dev)
678 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
681 ret = pm_runtime_get_sync(dev);
684 ret = regcache_sync(i2s->regmap);
691 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
692 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
694 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_suspend, rockchip_i2s_resume)
697 static struct platform_driver rockchip_i2s_driver = {
698 .probe = rockchip_i2s_probe,
699 .remove = rockchip_i2s_remove,
702 .of_match_table = of_match_ptr(rockchip_i2s_match),
703 .pm = &rockchip_i2s_pm_ops,
706 module_platform_driver(rockchip_i2s_driver);
708 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
709 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
710 MODULE_LICENSE("GPL v2");
711 MODULE_ALIAS("platform:" DRV_NAME);
712 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);