1 /* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 #ifndef __ROCKCHIP_SIP_H
13 #define __ROCKCHIP_SIP_H
15 #include <linux/arm-smccc.h>
18 /* SMC function IDs for SiP Service queries */
19 #define SIP_SVC_CALL_COUNT 0x8200ff00
20 #define SIP_SVC_UID 0x8200ff01
21 #define SIP_SVC_VERSION 0x8200ff03
23 #define SIP_ATF_VERSION32 0x82000001
24 #define SIP_ACCESS_REG 0x82000002
25 #define SIP_SUSPEND_MODE32 0x82000003
26 #define SIP_DDR_CFG32 0x82000008
27 #define SIP_SHARE_MEM32 0x82000009
28 #define SIP_SIP_VERSION32 0x8200000a
30 /* SIP_ACCESS_REG read/write */
31 #define SECURE_REG_RD 0x0
32 #define SECURE_REG_WR 0x1
34 /* Share mem page types */
36 SHARE_PAGE_TYPE_INVALID = 0,
37 SHARE_PAGE_TYPE_UARTDBG,
41 /* Error return code */
42 #define SIP_RET_SUCCESS 0
43 #define SIP_RET_NOT_SUPPORTED -1
44 #define SIP_RET_INVALID_PARAMS -2
45 #define SIP_RET_INVALID_ADDRESS -3
46 #define SIP_RET_DENIED -4
47 #define SIP_RET_SMC_UNKNOWN 0xffffffff
50 #define SIP_IMPLEMENT_V1 (1)
51 #define SIP_IMPLEMENT_V2 (2)
53 #define RK_SIP_DISABLE_FIQ 0xc2000006
54 #define RK_SIP_ENABLE_FIQ 0xc2000007
55 #define PSCI_SIP_RKTF_VER 0x82000001
56 #define PSCI_SIP_ACCESS_REG 0x82000002
57 #define PSCI_SIP_ACCESS_REG64 0xc2000002
58 #define PSCI_SIP_SUSPEND_WR_CTRBITS 0x82000003
59 #define PSCI_SIP_PENDING_CPUS 0x82000004
60 #define PSCI_SIP_UARTDBG_CFG 0x82000005
61 #define PSCI_SIP_UARTDBG_CFG64 0xc2000005
62 #define PSCI_SIP_EL3FIQ_CFG 0x82000006
63 #define PSCI_SIP_SMEM_CONFIG 0x82000007
65 #define UARTDBG_CFG_INIT 0xf0
66 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
67 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
68 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
69 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
70 #define UARTDBG_CFG_PRINT_PORT 0xf7
72 #define SUSPEND_MODE_CONFIG 0x01
73 #define WKUP_SOURCE_CONFIG 0x02
74 #define PWM_REGULATOR_CONFIG 0x03
75 #define GPIO_POWER_CONFIG 0x04
76 #define SUSPEND_DEBUG_ENABLE 0x05
77 #define APIOS_SUSPEND_CONFIG 0x06
78 #define VIRTUAL_POWEROFF 0x07
80 /* struct arm_smccc_res: a0: error code; a1~a3: data */
82 int sip_smc_set_suspend_mode(u32 ctrl,
85 int rk_psci_virtual_poweroff(void);
87 struct arm_smccc_res sip_smc_get_call_count(void);
88 struct arm_smccc_res sip_smc_get_atf_version(void);
89 struct arm_smccc_res sip_smc_get_sip_version(void);
90 struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1,
92 struct arm_smccc_res sip_smc_get_share_mem_page(u32 page_num,
93 share_page_type_t page_type);
94 u32 sip_smc_secure_reg_read(u32 addr_phy);
95 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
97 void psci_enable_fiq(void);
98 u32 rockchip_psci_smc_get_tf_ver(void);
99 void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset);
100 void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback);
101 u32 psci_fiq_debugger_switch_cpu(u32 cpu);
102 void psci_fiq_debugger_enable_debug(bool val);
103 int psci_fiq_debugger_set_print_port(u32 port, u32 baudrate);