1 /* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 #ifndef __ROCKCHIP_SIP_H
13 #define __ROCKCHIP_SIP_H
15 #include <linux/arm-smccc.h>
18 /* SMC function IDs for SiP Service queries */
19 #define SIP_SVC_CALL_COUNT 0x8200ff00
20 #define SIP_SVC_UID 0x8200ff01
21 #define SIP_SVC_VERSION 0x8200ff03
23 #define SIP_ATF_VERSION32 0x82000001
24 #define SIP_SUSPEND_MODE32 0x82000003
25 #define SIP_DDR_CFG32 0x82000008
26 #define SIP_SHARE_MEM32 0x82000009
27 #define SIP_SIP_VERSION32 0x8200000a
29 /* Share mem page types */
31 SHARE_PAGE_TYPE_INVALID = 0,
32 SHARE_PAGE_TYPE_UARTDBG,
36 /* Error return code */
37 #define SIP_RET_SUCCESS 0
38 #define SIP_RET_NOT_SUPPORTED -1
39 #define SIP_RET_INVALID_PARAMS -2
40 #define SIP_RET_INVALID_ADDRESS -3
41 #define SIP_RET_DENIED -4
42 #define SIP_RET_SMC_UNKNOWN 0xffffffff
45 #define SIP_IMPLEMENT_V1 (1)
46 #define SIP_IMPLEMENT_V2 (2)
48 #define RK_SIP_DISABLE_FIQ 0xc2000006
49 #define RK_SIP_ENABLE_FIQ 0xc2000007
50 #define PSCI_SIP_RKTF_VER 0x82000001
51 #define PSCI_SIP_ACCESS_REG 0x82000002
52 #define PSCI_SIP_ACCESS_REG64 0xc2000002
53 #define PSCI_SIP_SUSPEND_WR_CTRBITS 0x82000003
54 #define PSCI_SIP_PENDING_CPUS 0x82000004
55 #define PSCI_SIP_UARTDBG_CFG 0x82000005
56 #define PSCI_SIP_UARTDBG_CFG64 0xc2000005
57 #define PSCI_SIP_EL3FIQ_CFG 0x82000006
58 #define PSCI_SIP_SMEM_CONFIG 0x82000007
60 #define UARTDBG_CFG_INIT 0xf0
61 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
62 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
63 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
64 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
65 #define UARTDBG_CFG_PRINT_PORT 0xf7
67 #define SUSPEND_MODE_CONFIG 0x01
68 #define WKUP_SOURCE_CONFIG 0x02
69 #define PWM_REGULATOR_CONFIG 0x03
70 #define GPIO_POWER_CONFIG 0x04
71 #define SUSPEND_DEBUG_ENABLE 0x05
72 #define APIOS_SUSPEND_CONFIG 0x06
73 #define VIRTUAL_POWEROFF 0x07
75 /* struct arm_smccc_res: a0: error code; a1~a3: data */
77 int sip_smc_set_suspend_mode(u32 ctrl,
80 int rk_psci_virtual_poweroff(void);
82 struct arm_smccc_res sip_smc_get_call_count(void);
83 struct arm_smccc_res sip_smc_get_atf_version(void);
84 struct arm_smccc_res sip_smc_get_sip_version(void);
85 struct arm_smccc_res sip_smc_ddr_cfg(u32 arg0, u32 arg1,
87 struct arm_smccc_res sip_smc_get_share_mem_page(u32 page_num,
88 share_page_type_t page_type);
90 void psci_enable_fiq(void);
91 u32 rockchip_psci_smc_get_tf_ver(void);
92 void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset);
93 void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback);
94 u32 psci_fiq_debugger_switch_cpu(u32 cpu);
95 void psci_fiq_debugger_enable_debug(bool val);
96 int psci_fiq_debugger_set_print_port(u32 port, u32 baudrate);