1 #ifndef __ROCKCHIP_PSCI_H
2 #define __ROCKCHIP_PSCI_H
4 #define SEC_REG_RW_SHT (0x0)
5 #define SEC_REG_RD (0x0)
6 #define SEC_REG_WR (0x1)
8 #define SEC_REG_BITS_SHT (0x1)
9 #define SEC_REG_32 (0x0)
10 #define SEC_REG_64 (0x2)
12 #define SEC_REG_RD_32 (SEC_REG_RD | SEC_REG_32)
13 #define SEC_REG_RD_64 (SEC_REG_RD | SEC_REG_64)
14 #define SEC_REG_WR_32 (SEC_REG_WR | SEC_REG_32)
15 #define SEC_REG_WR_64 (SEC_REG_WR | SEC_REG_64)
18 * trust firmware verison
20 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
21 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
24 * pcsi smc funciton id
26 #define PSCI_SIP_RKTF_VER (0x82000001)
27 #define PSCI_SIP_ACCESS_REG (0x82000002)
28 #define PSCI_SIP_SUSPEND_WR_CTRBITS (0x82000003)
29 #define PSCI_SIP_PENDING_CPUS (0x82000004)
30 #define PSCI_SIP_UARTDBG_CFG (0x82000005)
31 #define PSCI_SIP_EL3FIQ_CFG (0x82000006)
34 * pcsi smc funciton err code
36 #define PSCI_SMC_FUNC_UNK 0xffffffff
39 * define PSCI_SIP_UARTDBG_CFG call type
41 #define UARTDBG_CFG_INIT 0xf0
42 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
43 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
44 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
45 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
48 * rockchip psci function call interface
50 u32 rockchip_psci_smc_read(u64 function_id, u64 arg0, u64 arg1, u64 arg2,
52 u32 rockchip_psci_smc_write(u64 function_id, u64 arg0, u64 arg1, u64 arg2);
54 u32 rockchip_psci_smc_get_tf_ver(void);
55 u32 rockchip_secure_reg_read32(u64 addr_phy);
56 u32 rockchip_secure_reg_write32(u64 addr_phy, u32 val);
58 u32 psci_fiq_debugger_switch_cpu(u32 cpu);
59 void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset);
60 void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback);
61 void psci_fiq_debugger_enable_debug(bool val);
63 #endif /* __ROCKCHIP_PSCI_H */