include/linux/rockchip/cpu_axi.h

   1 #ifndef __CPU_AXI_H
   2 #define __CPU_AXI_H
   3
   4 #define CPU_AXI_QOS_PRIORITY    0x08
   5 #define CPU_AXI_QOS_MODE        0x0c
   6 #define CPU_AXI_QOS_BANDWIDTH   0x10
   7 #define CPU_AXI_QOS_SATURATION  0x14
   8 #define CPU_AXI_QOS_EXTCONTROL  0x18
   9
  10 #define CPU_AXI_QOS_MODE_NONE           0
  11 #define CPU_AXI_QOS_MODE_FIXED          1
  12 #define CPU_AXI_QOS_MODE_LIMITER        2
  13 #define CPU_AXI_QOS_MODE_REGULATOR      3
  14
  15 #define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
  16         ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
  17 #define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
  18         writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)
  19
  20 #define CPU_AXI_SET_QOS_MODE(mode, base) \
  21         writel_relaxed((mode) & 3, base + CPU_AXI_QOS_MODE)
  22
  23 #define CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base) \
  24         writel_relaxed((bandwidth) & 0x7ff, base + CPU_AXI_QOS_BANDWIDTH)
  25
  26 #define CPU_AXI_SET_QOS_SATURATION(saturation, base) \
  27         writel_relaxed((saturation) & 0x3ff, base + CPU_AXI_QOS_SATURATION)
  28
  29 #define CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base) \
  30         writel_relaxed((extcontrol) & 7, base + CPU_AXI_QOS_EXTCONTROL)
  31
  32 #define CPU_AXI_QOS_NUM_REGS 5
  33 #define CPU_AXI_SAVE_QOS(array, base) do { \
  34         array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
  35         array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
  36         array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
  37         array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
  38         array[4] = readl_relaxed(base + CPU_AXI_QOS_EXTCONTROL); \
  39 } while (0)
  40 #define CPU_AXI_RESTORE_QOS(array, base) do { \
  41         writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
  42         writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
  43         writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
  44         writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
  45         writel_relaxed(array[4], base + CPU_AXI_QOS_EXTCONTROL); \
  46 } while (0)
  47
  48 #define RK3188_CPU_AXI_DMAC_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x1000)
  49 #define RK3188_CPU_AXI_CPU0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x2000)
  50 #define RK3188_CPU_AXI_CPU1R_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2080)
  51 #define RK3188_CPU_AXI_CPU1W_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x2100)
  52 #define RK3188_CPU_AXI_PERI_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x4000)
  53 #define RK3188_CPU_AXI_GPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x5000)
  54 #define RK3188_CPU_AXI_VPU_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x6000)
  55 #define RK3188_CPU_AXI_LCDC0_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7000)
  56 #define RK3188_CPU_AXI_CIF0_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7080)
  57 #define RK3188_CPU_AXI_IPP_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7100)
  58 #define RK3188_CPU_AXI_LCDC1_QOS_VIRT   (RK_CPU_AXI_BUS_VIRT + 0x7180)
  59 #define RK3188_CPU_AXI_CIF1_QOS_VIRT    (RK_CPU_AXI_BUS_VIRT + 0x7200)
  60 #define RK3188_CPU_AXI_RGA_QOS_VIRT     (RK_CPU_AXI_BUS_VIRT + 0x7280)
  61
  62 /* service core */
  63 #define RK3288_SERVICE_CORE_VIRT                RK_CPU_AXI_BUS_VIRT
  64 #define RK3288_CPU_AXI_CPUM_R_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x80)
  65 #define RK3288_CPU_AXI_CPUM_W_QOS_VIRT          (RK3288_SERVICE_CORE_VIRT + 0x100)
  66 #define RK3288_CPU_AXI_CPUP_QOS_VIRT            (RK3288_SERVICE_CORE_VIRT + 0x0)
  67 /* service dmac */
  68 #define RK3288_SERVICE_DMAC_VIRT                (RK3288_SERVICE_CORE_VIRT + RK3288_SERVICE_CORE_SIZE)
  69 #define RK3288_CPU_AXI_BUS_DMAC_QOS_VIRT        (RK3288_SERVICE_DMAC_VIRT + 0x0)
  70 #define RK3288_CPU_AXI_CCP_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x180)
  71 #define RK3288_CPU_AXI_CRYPTO_QOS_VIRT          (RK3288_SERVICE_DMAC_VIRT + 0x100)
  72 #define RK3288_CPU_AXI_CCS_QOS_VIRT             (RK3288_SERVICE_DMAC_VIRT + 0x200)
  73 #define RK3288_CPU_AXI_HOST_QOS_VIRT            (RK3288_SERVICE_DMAC_VIRT + 0x80)
  74 /* service gpu */
  75 #define RK3288_SERVICE_GPU_VIRT                 (RK3288_SERVICE_DMAC_VIRT + RK3288_SERVICE_DMAC_SIZE)
  76 #define RK3288_CPU_AXI_GPU_R_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x0)
  77 #define RK3288_CPU_AXI_GPU_W_QOS_VIRT           (RK3288_SERVICE_GPU_VIRT + 0x80)
  78 /* service peri */
  79 #define RK3288_SERVICE_PERI_VIRT                (RK3288_SERVICE_GPU_VIRT + RK3288_SERVICE_GPU_SIZE)
  80 #define RK3288_CPU_AXI_PERI_QOS_VIRT            (RK3288_SERVICE_PERI_VIRT + 0x0)
  81 /* service bus */
  82 #define RK3288_SERVICE_BUS_VIRT                 (RK3288_SERVICE_PERI_VIRT + RK3288_SERVICE_PERI_SIZE)
  83 /* service vio */
  84 #define RK3288_SERVICE_VIO_VIRT                 (RK3288_SERVICE_BUS_VIRT + RK3288_SERVICE_BUS_SIZE)
  85 #define RK3288_CPU_AXI_VIO0_IEP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x500)
  86 #define RK3288_CPU_AXI_VIO0_VIP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x480)
  87 #define RK3288_CPU_AXI_VIO0_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x400)
  88 #define RK3288_CPU_AXI_VIO1_ISP_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x900)
  89 #define RK3288_CPU_AXI_VIO1_ISP_W0_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x100)
  90 #define RK3288_CPU_AXI_VIO1_ISP_W1_QOS_VIRT     (RK3288_SERVICE_VIO_VIRT + 0x180)
  91 #define RK3288_CPU_AXI_VIO1_VOP_QOS_VIRT        (RK3288_SERVICE_VIO_VIRT + 0x0)
  92 #define RK3288_CPU_AXI_VIO2_RGA_R_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x800)
  93 #define RK3288_CPU_AXI_VIO2_RGA_W_QOS_VIRT      (RK3288_SERVICE_VIO_VIRT + 0x880)
  94 /* service video */
  95 #define RK3288_SERVICE_VIDEO_VIRT               (RK3288_SERVICE_VIO_VIRT + RK3288_SERVICE_VIO_SIZE)
  96 #define RK3288_CPU_AXI_VIDEO_QOS_VIRT           (RK3288_SERVICE_VIDEO_VIRT + 0x0)
  97 /* service hevc */
  98 #define RK3288_SERVICE_HEVC_VIRT                (RK3288_SERVICE_VIDEO_VIRT + RK3288_SERVICE_VIDEO_SIZE)
  99 #define RK3288_CPU_AXI_HEVC_R_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x0)
 100 #define RK3288_CPU_AXI_HEVC_W_QOS_VIRT          (RK3288_SERVICE_HEVC_VIRT + 0x100)
 101
 102 #define RK312X_CPU_AXI_QOS_NUM_REGS 4
 103 #define RK312X_CPU_AXI_SAVE_QOS(array, base) do { \
 104         array[0] = readl_relaxed(base + CPU_AXI_QOS_PRIORITY); \
 105         array[1] = readl_relaxed(base + CPU_AXI_QOS_MODE); \
 106         array[2] = readl_relaxed(base + CPU_AXI_QOS_BANDWIDTH); \
 107         array[3] = readl_relaxed(base + CPU_AXI_QOS_SATURATION); \
 108 } while (0)
 109 #define RK312X_CPU_AXI_RESTORE_QOS(array, base) do { \
 110         writel_relaxed(array[0], base + CPU_AXI_QOS_PRIORITY); \
 111         writel_relaxed(array[1], base + CPU_AXI_QOS_MODE); \
 112         writel_relaxed(array[2], base + CPU_AXI_QOS_BANDWIDTH); \
 113         writel_relaxed(array[3], base + CPU_AXI_QOS_SATURATION); \
 114 } while (0)
 115 #define RK312X_SERVICE_VIO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x7000)
 116
 117 #define RK312X_CPU_AXI_VIO_RGA_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT)
 118 #define RK312X_CPU_AXI_VIO_EBC_QOS_VIRT        (RK312X_SERVICE_VIO_VIRT + 0x80)
 119 #define RK312X_CPU_AXI_VIO_IEP_QOS_VIRT      (RK312X_SERVICE_VIO_VIRT + 0x100)
 120 #define RK312X_CPU_AXI_VIO_LCDC0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x180)
 121 #define RK312X_CPU_AXI_VIO_VIP0_QOS_VIRT     (RK312X_SERVICE_VIO_VIRT + 0x200)
 122
 123 #define RK312X_SERVICE_GPU_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x5000)
 124 #define RK312X_CPU_AXI_GPU_QOS_VIRT        (RK312X_SERVICE_GPU_VIRT)
 125
 126 #define RK312X_SERVICE_VIDEO_VIRT                 (RK_CPU_AXI_BUS_VIRT + 0x6000)
 127 #define RK312X_CPU_AXI_VIDEO_QOS_VIRT        (RK312X_SERVICE_VIDEO_VIRT)
 128 #endif