2 * include/linux/arm-hdlcd.h
4 * Copyright (C) 2011 ARM Limited
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
10 * ARM HDLCD Controller register definition
14 #include <linux/completion.h>
16 /* register offsets */
17 #define HDLCD_REG_VERSION 0x0000 /* ro */
18 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
19 #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
20 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
21 #define HDLCD_REG_INT_STATUS 0x001c /* ro */
22 #define HDLCD_REG_USER_OUT 0x0020 /* rw */
23 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
24 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
25 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
26 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
27 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
28 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
29 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
30 #define HDLCD_REG_V_DATA 0x0208 /* rw */
31 #define HDLCD_REG_V_FRONT_PORCH 0x020c /* rw */
32 #define HDLCD_REG_H_SYNC 0x0210 /* rw */
33 #define HDLCD_REG_H_BACK_PORCH 0x0214 /* rw */
34 #define HDLCD_REG_H_DATA 0x0218 /* rw */
35 #define HDLCD_REG_H_FRONT_PORCH 0x021c /* rw */
36 #define HDLCD_REG_POLARITIES 0x0220 /* rw */
37 #define HDLCD_REG_COMMAND 0x0230 /* rw */
38 #define HDLCD_REG_PIXEL_FORMAT 0x0240 /* rw */
39 #define HDLCD_REG_BLUE_SELECT 0x0244 /* rw */
40 #define HDLCD_REG_GREEN_SELECT 0x0248 /* rw */
41 #define HDLCD_REG_RED_SELECT 0x024c /* rw */
44 #define HDLCD_PRODUCT_ID 0x1CDC0000
45 #define HDLCD_PRODUCT_MASK 0xFFFF0000
46 #define HDLCD_VERSION_MAJOR_MASK 0x0000FF00
47 #define HDLCD_VERSION_MINOR_MASK 0x000000FF
50 #define HDLCD_INTERRUPT_DMA_END (1 << 0)
51 #define HDLCD_INTERRUPT_BUS_ERROR (1 << 1)
52 #define HDLCD_INTERRUPT_VSYNC (1 << 2)
53 #define HDLCD_INTERRUPT_UNDERRUN (1 << 3)
56 #define HDLCD_POLARITY_VSYNC (1 << 0)
57 #define HDLCD_POLARITY_HSYNC (1 << 1)
58 #define HDLCD_POLARITY_DATAEN (1 << 2)
59 #define HDLCD_POLARITY_DATA (1 << 3)
60 #define HDLCD_POLARITY_PIXELCLK (1 << 4)
63 #define HDLCD_COMMAND_DISABLE (0 << 0)
64 #define HDLCD_COMMAND_ENABLE (1 << 0)
67 #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN (0 << 31)
68 #define HDLCD_PIXEL_FMT_BIG_ENDIAN (1 << 31)
69 #define HDLCD_BYTES_PER_PIXEL_MASK (3 << 3)
72 #define HDLCD_BUS_BURST_MASK 0x01f
73 #define HDLCD_BUS_MAX_OUTSTAND 0xf00
74 #define HDLCD_BUS_BURST_NONE (0 << 0)
75 #define HDLCD_BUS_BURST_1 (1 << 0)
76 #define HDLCD_BUS_BURST_2 (1 << 1)
77 #define HDLCD_BUS_BURST_4 (1 << 2)
78 #define HDLCD_BUS_BURST_8 (1 << 3)
79 #define HDLCD_BUS_BURST_16 (1 << 4)
81 /* Max resolution supported is 4096x4096, 8 bit per color component,
82 8 bit alpha, but we are going to choose the usual hardware default
83 (2048x2048, 32 bpp) and enable double buffering */
84 #define HDLCD_MAX_XRES 2048
85 #define HDLCD_MAX_YRES 2048
86 #define HDLCD_MAX_FRAMEBUFFER_SIZE (HDLCD_MAX_XRES * HDLCD_MAX_YRES << 2)
88 #define HDLCD_MEM_BASE (CONFIG_PAGE_OFFSET - 0x1000000)
90 #define NR_PALETTE 256
92 /* OEMs using HDLCD may wish to enable these settings if
93 * display disruption is apparent and you suspect HDLCD
94 * access to RAM may be starved.
96 /* Turn HDLCD default color red instead of black so
97 * that it's easy to see pixel clock data underruns
98 * (compared to other visual disruption)
100 //#define HDLCD_RED_DEFAULT_COLOUR
101 /* Add a counter in the IRQ handler to count buffer underruns
102 * and /proc/hdlcd_underrun to read the counter
104 //#define HDLCD_COUNT_BUFFERUNDERRUNS
105 /* Restrict height to 1x screen size
108 //#define HDLCD_NO_VIRTUAL_SCREEN
110 #ifdef CONFIG_ANDROID
111 #define HDLCD_NO_VIRTUAL_SCREEN
114 struct hdlcd_device {
120 struct completion vsync_completion;