2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
16 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
28 /* sclk gates (special clocks) */
29 #define SCLK_GPU_CORE 64
37 #define SCLK_SARADC 73
38 #define SCLK_NANDC0 75
44 #define SCLK_I2S_8CH 82
45 #define SCLK_SPDIF_8CH 83
46 #define SCLK_I2S_2CH 84
47 #define SCLK_TIMER0 85
48 #define SCLK_TIMER1 86
49 #define SCLK_TIMER2 87
50 #define SCLK_TIMER3 88
51 #define SCLK_TIMER4 89
52 #define SCLK_TIMER5 90
53 #define SCLK_TIMER6 91
54 #define SCLK_OTGPHY0 93
55 #define SCLK_OTG_ADP 96
56 #define SCLK_HSICPHY480M 97
57 #define SCLK_HSICPHY12M 98
58 #define SCLK_MACREF 99
59 #define SCLK_VOP0_PWM 100
60 #define SCLK_MAC_RX 102
61 #define SCLK_MAC_TX 103
62 #define SCLK_EDP_24M 104
67 #define SCLK_HDMI_HDCP 109
68 #define SCLK_HDMI_CEC 110
69 #define SCLK_HEVC_CABAC 111
70 #define SCLK_HEVC_CORE 112
71 #define SCLK_I2S_8CH_OUT 113
72 #define SCLK_SDMMC_DRV 114
73 #define SCLK_SDIO0_DRV 115
74 #define SCLK_EMMC_DRV 117
75 #define SCLK_SDMMC_SAMPLE 118
76 #define SCLK_SDIO0_SAMPLE 119
77 #define SCLK_EMMC_SAMPLE 121
78 #define SCLK_USBPHY480M 122
79 #define SCLK_PVTM_CORE 123
80 #define SCLK_PVTM_GPU 124
81 #define SCLK_PVTM_PMU 125
84 #define SCLK_MACREF_OUT 128
85 #define SCLK_MIPIDSI_24M 129
86 #define SCLK_CRYPTO 130
87 #define SCLK_VIP_SRC 131
88 #define SCLK_VIP_OUT 132
91 #define MCLK_CRYPTO 191
94 #define ACLK_GPU_MEM 192
95 #define ACLK_GPU_CFG 193
96 #define ACLK_DMAC_BUS 194
97 #define ACLK_DMAC_PERI 195
98 #define ACLK_PERI_MMU 196
101 #define ACLK_VOP_IEP 199
103 #define ACLK_HDCP 201
105 #define ACLK_VIO0_NOC 203
108 #define ACLK_VIO1_NOC 206
109 #define ACLK_VIDEO 208
111 #define ACLK_PERI 210
114 #define PCLK_GPIO0 320
115 #define PCLK_GPIO1 321
116 #define PCLK_GPIO2 322
117 #define PCLK_GPIO3 323
118 #define PCLK_PMUGRF 324
119 #define PCLK_MAILBOX 325
121 #define PCLK_SGRF 330
123 #define PCLK_I2C0 332
124 #define PCLK_I2C1 333
125 #define PCLK_I2C2 334
126 #define PCLK_I2C3 335
127 #define PCLK_I2C4 336
128 #define PCLK_I2C5 337
129 #define PCLK_SPI0 338
130 #define PCLK_SPI1 339
131 #define PCLK_SPI2 340
132 #define PCLK_UART0 341
133 #define PCLK_UART1 342
134 #define PCLK_UART2 343
135 #define PCLK_UART3 344
136 #define PCLK_UART4 345
137 #define PCLK_TSADC 346
138 #define PCLK_SARADC 347
140 #define PCLK_GMAC 349
141 #define PCLK_PWM0 350
142 #define PCLK_PWM1 351
143 #define PCLK_TIMER0 353
144 #define PCLK_TIMER1 354
145 #define PCLK_EDP_CTRL 355
146 #define PCLK_MIPI_DSI0 356
147 #define PCLK_MIPI_CSI 358
148 #define PCLK_HDCP 359
149 #define PCLK_HDMI_CTRL 360
150 #define PCLK_VIO_H2P 361
152 #define PCLK_PERI 363
153 #define PCLK_DDRUPCTL 364
154 #define PCLK_DDRPHY 365
158 #define PCLK_DPHYRX 369
159 #define PCLK_DPHYTX0 370
162 #define HCLK_USB_PERI 447
164 #define HCLK_OTG0 449
165 #define HCLK_HOST0 450
166 #define HCLK_HOST1 451
167 #define HCLK_HSIC 452
168 #define HCLK_NANDC0 453
170 #define HCLK_SDMMC 456
171 #define HCLK_SDIO0 457
172 #define HCLK_EMMC 459
173 #define HCLK_HSADC 460
174 #define HCLK_CRYPTO 461
175 #define HCLK_I2S_2CH 462
176 #define HCLK_I2S_8CH 463
177 #define HCLK_SPDIF 464
183 #define HCLK_VIO_AHB_ARBI 471
184 #define HCLK_VIO_NOC 472
186 #define HCLK_VIO_H2P 474
187 #define HCLK_VIO_HDCPMMU 475
188 #define HCLK_VIDEO 476
190 #define HCLK_PERI 478
192 #define CLK_NR_CLKS (HCLK_PERI + 1)
194 /* soft-reset indices */
195 #define SRST_CORE_B0 0
196 #define SRST_CORE_B1 1
197 #define SRST_CORE_B2 2
198 #define SRST_CORE_B3 3
199 #define SRST_CORE_B0_PO 4
200 #define SRST_CORE_B1_PO 5
201 #define SRST_CORE_B2_PO 6
202 #define SRST_CORE_B3_PO 7
205 #define SRST_PD_CORE_B_NIU 10
206 #define SRST_PDBUS_STRSYS 11
207 #define SRST_SOCDBG_B 14
208 #define SRST_CORE_B_DBG 15
210 #define SRST_DMAC1 18
211 #define SRST_INTMEM 19
213 #define SRST_SPDIF8CH 21
214 #define SRST_I2S8CH 23
215 #define SRST_MAILBOX 24
216 #define SRST_I2S2CH 25
217 #define SRST_EFUSE_256 26
218 #define SRST_MCU_SYS 28
219 #define SRST_MCU_PO 29
220 #define SRST_MCU_NOC 30
221 #define SRST_EFUSE 31
223 #define SRST_GPIO0 32
224 #define SRST_GPIO1 33
225 #define SRST_GPIO2 34
226 #define SRST_GPIO3 35
227 #define SRST_GPIO4 36
228 #define SRST_PMUGRF 41
236 #define SRST_DWPWM 48
237 #define SRST_MMC_PERI 49
238 #define SRST_PERIPH_MMU 50
241 #define SRST_PERIPH_AXI 57
242 #define SRST_PERIPH_AHB 58
243 #define SRST_PERIPH_APB 59
244 #define SRST_PERIPH_NIU 60
245 #define SRST_PDPERI_AHB_ARBI 61
247 #define SRST_USB_PERI 63
249 #define SRST_DMAC2 64
252 #define SRST_RKPWM 69
253 #define SRST_USBHOST0 72
255 #define SRST_HSIC_AUX 74
256 #define SRST_HSIC_PHY 75
257 #define SRST_HSADC 76
258 #define SRST_NANDC0 77
264 #define SRST_SARADC 87
265 #define SRST_PDALIVE_NIU 88
266 #define SRST_PDPMU_INTMEM 89
267 #define SRST_PDPMU_NIU 90
270 #define SRST_VIO_ARBI 96
271 #define SRST_RGA_NIU 97
272 #define SRST_VIO0_NIU_AXI 98
273 #define SRST_VIO_NIU_AHB 99
274 #define SRST_LCDC0_AXI 100
275 #define SRST_LCDC0_AHB 101
276 #define SRST_LCDC0_DCLK 102
278 #define SRST_RGA_CORE 105
279 #define SRST_IEP_AXI 106
280 #define SRST_IEP_AHB 107
281 #define SRST_RGA_AXI 108
282 #define SRST_RGA_AHB 109
284 #define SRST_EDP_24M 111
286 #define SRST_VIDEO_AXI 112
287 #define SRST_VIDEO_AHB 113
288 #define SRST_MIPIDPHYTX 114
289 #define SRST_MIPIDSI0 115
290 #define SRST_MIPIDPHYRX 116
291 #define SRST_MIPICSI 117
293 #define SRST_HDMI 121
295 #define SRST_PMU_PVTM 123
296 #define SRST_CORE_PVTM 124
297 #define SRST_GPU_PVTM 125
298 #define SRST_GPU_SYS 126
299 #define SRST_GPU_MEM_NIU 127
301 #define SRST_MMC0 128
302 #define SRST_SDIO0 129
303 #define SRST_EMMC 131
304 #define SRST_USBOTG_AHB 132
305 #define SRST_USBOTG_PHY 133
306 #define SRST_USBOTG_CON 134
307 #define SRST_USBHOST0_AHB 135
308 #define SRST_USBHOST0_PHY 136
309 #define SRST_USBHOST0_CON 137
310 #define SRST_USBOTG_UTMI 138
311 #define SRST_USBHOST1_UTMI 139
312 #define SRST_USB_ADP 141
314 #define SRST_CORESIGHT 144
315 #define SRST_PD_CORE_AHB_NOC 145
316 #define SRST_PD_CORE_APB_NOC 146
318 #define SRST_LCDC_PWM0 149
319 #define SRST_RGA_H2P_BRG 153
320 #define SRST_VIDEO 154
321 #define SRST_GPU_CFG_NIU 157
322 #define SRST_TSADC 159
324 #define SRST_DDRPHY0 160
325 #define SRST_DDRPHY0_APB 161
326 #define SRST_DDRCTRL0 162
327 #define SRST_DDRCTRL0_APB 163
328 #define SRST_VIDEO_NIU 165
329 #define SRST_VIDEO_NIU_AHB 167
330 #define SRST_DDRMSCH0 170
331 #define SRST_PDBUS_AHB 173
332 #define SRST_CRYPTO 174
334 #define SRST_UART0 179
335 #define SRST_UART1 180
336 #define SRST_UART2 181
337 #define SRST_UART3 182
338 #define SRST_UART4 183
339 #define SRST_SIMC 186
341 #define SRST_TSP_CLKIN0 189
343 #define SRST_CORE_L0 192
344 #define SRST_CORE_L1 193
345 #define SRST_CORE_L2 194
346 #define SRST_CORE_L3 195
347 #define SRST_CORE_L0_PO 195
348 #define SRST_CORE_L1_PO 197
349 #define SRST_CORE_L2_PO 198
350 #define SRST_CORE_L3_PO 199
351 #define SRST_L2_L 200
352 #define SRST_ADB_L 201
353 #define SRST_PD_CORE_L_NIU 202
354 #define SRST_CCI_SYS 203
355 #define SRST_CCI_DDR 204
357 #define SRST_SOCDBG_L 206
358 #define SRST_CORE_L_DBG 207
360 #define SRST_CORE_B0_NC 208
361 #define SRST_CORE_B0_PO_NC 209
362 #define SRST_L2_B_NC 210
363 #define SRST_ADB_B_NC 211
364 #define SRST_PD_CORE_B_NIU_NC 212
365 #define SRST_PDBUS_STRSYS_NC 213
366 #define SRST_CORE_L0_NC 214
367 #define SRST_CORE_L0_PO_NC 215
368 #define SRST_L2_L_NC 216
369 #define SRST_ADB_L_NC 217
370 #define SRST_PD_CORE_L_NIU_NC 218
371 #define SRST_CCI_SYS_NC 219
372 #define SRST_CCI_DDR_NC 220
373 #define SRST_CCI_NC 221
374 #define SRST_TRACE_NC 222
376 #define SRST_TIMER00 224
377 #define SRST_TIMER01 225
378 #define SRST_TIMER02 226
379 #define SRST_TIMER03 227
380 #define SRST_TIMER04 228
381 #define SRST_TIMER05 229
382 #define SRST_TIMER10 230
383 #define SRST_TIMER11 231
384 #define SRST_TIMER12 232
385 #define SRST_TIMER13 233
386 #define SRST_TIMER14 234
387 #define SRST_TIMER15 235
388 #define SRST_TIMER0_APB 236
389 #define SRST_TIMER1_APB 237