drivers/video/rockchip/iep/hw_iep_config_addr.h

   1 #ifndef HW_IEP_CONFIG_ADDR_H_
   2 #define HW_IEP_CONFIG_ADDR_H_
   3
   4 #include <asm/io.h>
   5
   6 /*ignore the IEP_BASE when program running in linux kernel */
   7 #define      IEP_BASE                      0x0
   8
   9 #define      IEP_CONFIG0                       0x0000
  10 #define      IEP_CONFIG1                       0x0004
  11
  12 #define      IEP_STATUS                    0x0008
  13 #define      IEP_INT                       0x000C
  14 #define      IEP_FRM_START                         0x0010
  15 #define      IEP_SOFT_RST                  0x0014
  16 #define      IEP_CONF_DONE                 0x0018
  17
  18 #define      IEP_VIR_IMG_WIDTH             0x0020
  19
  20 #define      IEP_IMG_SCL_FCT               0x0024
  21
  22 #define      IEP_SRC_IMG_SIZE              0x0028
  23 #define      IEP_DST_IMG_SIZE              0x002C
  24
  25 #define      IEP_DST_IMG_WIDTH_TILE0       0x0030
  26 #define      IEP_DST_IMG_WIDTH_TILE1       0x0034
  27 #define      IEP_DST_IMG_WIDTH_TILE2       0x0038
  28 #define      IEP_DST_IMG_WIDTH_TILE3       0x003C
  29
  30 #define      IEP_ENH_YUV_CNFG_0            0x0040
  31 #define      IEP_ENH_YUV_CNFG_1            0x0044
  32 #define      IEP_ENH_YUV_CNFG_2            0x0048
  33 #define      IEP_ENH_RGB_CNFG              0x004C
  34 #define      IEP_ENH_C_COE                 0x0050
  35
  36 #define      IEP_SRC_ADDR_YRGB             0x0080
  37 #define      IEP_SRC_ADDR_CBCR             0x0084
  38 #define      IEP_SRC_ADDR_CR               0x0088
  39 #define      IEP_SRC_ADDR_Y1               0x008C
  40 #define      IEP_SRC_ADDR_CBCR1            0x0090
  41 #define      IEP_SRC_ADDR_CR1              0x0094
  42 #define      IEP_SRC_ADDR_Y_ITEMP          0x0098
  43 #define      IEP_SRC_ADDR_CBCR_ITEMP       0x009C
  44 #define      IEP_SRC_ADDR_CR_ITEMP         0x00A0
  45 #define      IEP_SRC_ADDR_Y_FTEMP          0x00A4
  46 #define      IEP_SRC_ADDR_CBCR_FTEMP       0x00A8
  47 #define      IEP_SRC_ADDR_CR_FTEMP         0x00AC
  48
  49 #define      IEP_DST_ADDR_YRGB             0x00B0
  50 #define      IEP_DST_ADDR_CBCR             0x00B4
  51 #define      IEP_DST_ADDR_CR               0x00B8
  52 #define      IEP_DST_ADDR_Y1               0x00BC
  53 #define      IEP_DST_ADDR_CBCR1            0x00C0
  54 #define      IEP_DST_ADDR_CR1              0x00C4
  55 #define      IEP_DST_ADDR_Y_ITEMP          0x00C8
  56 #define      IEP_DST_ADDR_CBCR_ITEMP       0x00CC
  57 #define      IEP_DST_ADDR_CR_ITEMP         0x00D0
  58 #define      IEP_DST_ADDR_Y_FTEMP          0x00D4
  59 #define      IEP_DST_ADDR_CBCR_FTEMP       0x00D8
  60 #define      IEP_DST_ADDR_CR_FTEMP         0x00DC
  61
  62 #define      IEP_DIL_MTN_TAB0              0x00E0
  63 #define      IEP_DIL_MTN_TAB1              0x00E4
  64 #define      IEP_DIL_MTN_TAB2              0x00E8
  65 #define      IEP_DIL_MTN_TAB3              0x00EC
  66 #define      IEP_DIL_MTN_TAB4              0x00F0
  67 #define      IEP_DIL_MTN_TAB5              0x00F4
  68 #define      IEP_DIL_MTN_TAB6              0x00F8
  69 #define      IEP_DIL_MTN_TAB7              0x00FC
  70
  71 #define      IEP_ENH_CG_TAB                0x0100
  72
  73 #define      IEP_YUV_DNS_CRCT_TEMP         0x0400
  74 #define      IEP_YUV_DNS_CRCT_SPAT         0x0800
  75
  76 #define      IEP_ENH_DDE_COE0              0x0C00
  77 #define      IEP_ENH_DDE_COE1              0x0E00
  78
  79 #define      RAW_IEP_CONFIG0               0x0058
  80 #define      RAW_IEP_CONFIG1                       0x005C
  81 #define      RAW_IEP_VIR_IMG_WIDTH         0x0060
  82
  83 #define      RAW_IEP_IMG_SCL_FCT           0x0064
  84
  85 #define      RAW_IEP_SRC_IMG_SIZE          0x0068
  86 #define      RAW_IEP_DST_IMG_SIZE          0x006C
  87
  88 #define      RAW_IEP_ENH_YUV_CNFG_0        0x0070
  89 #define      RAW_IEP_ENH_YUV_CNFG_1        0x0074
  90 #define      RAW_IEP_ENH_YUV_CNFG_2        0x0078
  91 #define      RAW_IEP_ENH_RGB_CNFG          0x007C
  92
  93 #define ReadReg32(base, raddr)          (__raw_readl(base + raddr))
  94 #define WriteReg32(base, waddr, value)  (__raw_writel(value, base + waddr))
  95 #define ConfRegBits32(base, raddr, waddr, position, value)           WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
  96 #define MaskRegBits32(base, waddr, position, value)                  WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
  97
  98 #endif