drivers/usb/dwc_otg_310/dwc_otg_pcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
   3  * $Revision: #119 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_HOST_ONLY
  34
  35 #include "dwc_otg_pcd.h"
  36 #include "dwc_otg_driver.h"
  37
  38 #ifdef DWC_UTE_CFI
  39 #include "dwc_otg_cfi.h"
  40 #endif
  41
  42 #ifdef DWC_UTE_PER_IO
  43 extern void complete_xiso_ep(dwc_otg_pcd_ep_t *ep);
  44 #endif
  45 /* #define PRINT_CFI_DMA_DESCS */
  46
  47 #define DEBUG_EP0
  48
  49 /**
  50  * This function updates OTG.
  51  */
  52 static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
  53 {
  54
  55         if (reset) {
  56                 pcd->b_hnp_enable = 0;
  57                 pcd->a_hnp_support = 0;
  58                 pcd->a_alt_hnp_support = 0;
  59         }
  60
  61         if (pcd->fops->hnp_changed) {
  62                 pcd->fops->hnp_changed(pcd);
  63         }
  64 }
  65
  66 /** @file
  67  * This file contains the implementation of the PCD Interrupt handlers.
  68  *
  69  * The PCD handles the device interrupts.  Many conditions can cause a
  70  * device interrupt. When an interrupt occurs, the device interrupt
  71  * service routine determines the cause of the interrupt and
  72  * dispatches handling to the appropriate function. These interrupt
  73  * handling functions are described below.
  74  * All interrupt registers are processed from LSB to MSB.
  75  */
  76
  77 /**
  78  * This function prints the ep0 state for debug purposes.
  79  */
  80 static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
  81 {
  82 #ifdef DEBUG
  83         char str[40];
  84
  85         switch (pcd->ep0state) {
  86         case EP0_DISCONNECT:
  87                 dwc_strcpy(str, "EP0_DISCONNECT");
  88                 break;
  89         case EP0_IDLE:
  90                 dwc_strcpy(str, "EP0_IDLE");
  91                 break;
  92         case EP0_IN_DATA_PHASE:
  93                 dwc_strcpy(str, "EP0_IN_DATA_PHASE");
  94                 break;
  95         case EP0_OUT_DATA_PHASE:
  96                 dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
  97                 break;
  98         case EP0_IN_STATUS_PHASE:
  99                 dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
 100                 break;
 101         case EP0_OUT_STATUS_PHASE:
 102                 dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
 103                 break;
 104         case EP0_STALL:
 105                 dwc_strcpy(str, "EP0_STALL");
 106                 break;
 107         default:
 108                 dwc_strcpy(str, "EP0_INVALID");
 109         }
 110
 111         DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
 112 #endif
 113 }
 114
 115 /**
 116  * This function calculate the size of the payload in the memory
 117  * for out endpoints and prints size for debug purposes(used in
 118  * 2.93a DevOutNak feature).
 119  */
 120 static inline void print_memory_payload(dwc_otg_pcd_t *pcd, dwc_ep_t *ep)
 121 {
 122 #ifdef DEBUG
 123         deptsiz_data_t deptsiz_init = {.d32 = 0 };
 124         deptsiz_data_t deptsiz_updt = {.d32 = 0 };
 125         int pack_num;
 126         unsigned payload;
 127
 128         deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
 129         deptsiz_updt.d32 =
 130             DWC_READ_REG32(&pcd->core_if->dev_if->
 131                            out_ep_regs[ep->num]->doeptsiz);
 132         /* Payload will be */
 133         payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
 134         /* Packet count is decremented every time a packet
 135          * is written to the RxFIFO not in to the external memory
 136          * So, if payload == 0, then it means no packet was sent to ext memory*/
 137         pack_num =
 138             (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
 139         DWC_DEBUGPL(DBG_PCDV, "Payload for EP%d-%s\n", ep->num,
 140                     (ep->is_in ? "IN" : "OUT"));
 141         DWC_DEBUGPL(DBG_PCDV, "Number of transfered bytes = 0x%08x\n", payload);
 142         DWC_DEBUGPL(DBG_PCDV, "Number of transfered packets = %d\n", pack_num);
 143 #endif
 144 }
 145
 146 #ifdef DWC_UTE_CFI
 147 static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
 148                               const uint8_t *epname, int descnum)
 149 {
 150         CFI_INFO
 151             ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
 152              epname, descnum, ddesc->buf, ddesc->status.b.bytes,
 153              ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
 154              ddesc->status.b.bs);
 155 }
 156 #endif
 157
 158 /**
 159  * This function returns pointer to in ep struct with number ep_num
 160  */
 161 static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
 162 {
 163         int i;
 164         int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
 165         if (ep_num == 0) {
 166                 return &pcd->ep0;
 167         } else {
 168                 for (i = 0; i < num_in_eps; ++i) {
 169                         if (pcd->in_ep[i].dwc_ep.num == ep_num)
 170                                 return &pcd->in_ep[i];
 171                 }
 172                 return 0;
 173         }
 174 }
 175
 176 /**
 177  * This function returns pointer to out ep struct with number ep_num
 178  */
 179 static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
 180 {
 181         int i;
 182         int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
 183         if (ep_num == 0) {
 184                 return &pcd->ep0;
 185         } else {
 186                 for (i = 0; i < num_out_eps; ++i) {
 187                         if (pcd->out_ep[i].dwc_ep.num == ep_num)
 188                                 return &pcd->out_ep[i];
 189                 }
 190                 return 0;
 191         }
 192 }
 193
 194 /**
 195  * This functions gets a pointer to an EP from the wIndex address
 196  * value of the control request.
 197  */
 198 dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t *pcd, u16 wIndex)
 199 {
 200         dwc_otg_pcd_ep_t *ep;
 201         uint32_t ep_num = UE_GET_ADDR(wIndex);
 202
 203         if (ep_num == 0) {
 204                 ep = &pcd->ep0;
 205         } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
 206                 ep = &pcd->in_ep[ep_num - 1];
 207         } else {
 208                 ep = &pcd->out_ep[ep_num - 1];
 209         }
 210
 211         return ep;
 212 }
 213
 214 /**
 215  * This function checks the EP request queue, if the queue is not
 216  * empty the next request is started.
 217  */
 218 void start_next_request(dwc_otg_pcd_ep_t *ep)
 219 {
 220         dwc_otg_pcd_request_t *req = 0;
 221         uint32_t max_transfer =
 222             GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
 223
 224 #ifdef DWC_UTE_CFI
 225         struct dwc_otg_pcd *pcd;
 226         pcd = ep->pcd;
 227 #endif
 228
 229         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
 230                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
 231
 232 #ifdef DWC_UTE_CFI
 233                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
 234                         ep->dwc_ep.cfi_req_len = req->length;
 235                         pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
 236                 } else {
 237 #endif
 238                         /* Setup and start the Transfer */
 239                         if (req->dw_align_buf) {
 240                                 ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
 241                                 ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
 242                                 ep->dwc_ep.xfer_buff = req->dw_align_buf;
 243                         } else {
 244                                 ep->dwc_ep.dma_addr = req->dma;
 245                                 ep->dwc_ep.start_xfer_buff = req->buf;
 246                                 ep->dwc_ep.xfer_buff = req->buf;
 247                         }
 248                         ep->dwc_ep.sent_zlp = 0;
 249                         ep->dwc_ep.total_len = req->length;
 250                         ep->dwc_ep.xfer_len = 0;
 251                         ep->dwc_ep.xfer_count = 0;
 252
 253                         ep->dwc_ep.maxxfer = max_transfer;
 254                         if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
 255                                 uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
 256                                     - (DDMA_MAX_TRANSFER_SIZE % 4);
 257                                 if (ep->dwc_ep.is_in) {
 258                                         if (ep->dwc_ep.maxxfer >
 259                                             DDMA_MAX_TRANSFER_SIZE) {
 260                                                 ep->dwc_ep.maxxfer =
 261                                                     DDMA_MAX_TRANSFER_SIZE;
 262                                         }
 263                                 } else {
 264                                         if (ep->dwc_ep.maxxfer > out_max_xfer) {
 265                                                 ep->dwc_ep.maxxfer =
 266                                                     out_max_xfer;
 267                                         }
 268                                 }
 269                         }
 270                         if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
 271                                 ep->dwc_ep.maxxfer -=
 272                                     (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
 273                         }
 274                         if (req->sent_zlp) {
 275                                 if ((ep->dwc_ep.total_len %
 276                                      ep->dwc_ep.maxpacket == 0)
 277                                     && (ep->dwc_ep.total_len != 0)) {
 278                                         ep->dwc_ep.sent_zlp = 1;
 279                                 }
 280
 281                         }
 282 #ifdef DWC_UTE_CFI
 283                 }
 284 #endif
 285                 dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
 286         } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
 287                 DWC_PRINTF("There are no more ISOC requests \n");
 288                 ep->dwc_ep.frame_num = 0xFFFFFFFF;
 289         }
 290 }
 291
 292 /**
 293  * This function handles the SOF Interrupts. At this time the SOF
 294  * Interrupt is disabled.
 295  */
 296 int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
 297 {
 298         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
 299
 300         gintsts_data_t gintsts;
 301
 302         DWC_DEBUGPL(DBG_PCD, "SOF\n");
 303
 304         /* Clear interrupt */
 305         gintsts.d32 = 0;
 306         gintsts.b.sofintr = 1;
 307         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
 308
 309         return 1;
 310 }
 311
 312 /**
 313  * This function handles the Rx Status Queue Level Interrupt, which
 314  * indicates that there is a least one packet in the Rx FIFO.  The
 315  * packets are moved from the FIFO to memory, where they will be
 316  * processed when the Endpoint Interrupt Register indicates Transfer
 317  * Complete or SETUP Phase Done.
 318  *
 319  * Repeat the following until the Rx Status Queue is empty:
 320  *       -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
 321  *              info
 322  *       -# If Receive FIFO is empty then skip to step Clear the interrupt
 323  *              and exit
 324  *       -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
 325  *              SETUP data to the buffer
 326  *       -# If OUT Data Packet call dwc_otg_read_packet to copy the data
 327  *              to the destination buffer
 328  */
 329 int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
 330 {
 331         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
 332         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
 333         gintmsk_data_t gintmask = {.d32 = 0 };
 334         device_grxsts_data_t status;
 335         dwc_otg_pcd_ep_t *ep;
 336         gintsts_data_t gintsts;
 337 #ifdef DEBUG
 338         static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
 339 #endif
 340
 341         /* DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); */
 342         /* Disable the Rx Status Queue Level interrupt */
 343         gintmask.b.rxstsqlvl = 1;
 344         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
 345
 346         /* Get the Status from the top of the FIFO */
 347         status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
 348
 349         DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
 350                     "pktsts:%x Frame:%d(0x%0x)\n",
 351                     status.b.epnum, status.b.bcnt,
 352                     dpid_str[status.b.dpid],
 353                     status.b.pktsts, status.b.fn, status.b.fn);
 354         /* Get pointer to EP structure */
 355         ep = get_out_ep(pcd, status.b.epnum);
 356
 357         switch (status.b.pktsts) {
 358         case DWC_DSTS_GOUT_NAK:
 359                 DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
 360                 break;
 361         case DWC_STS_DATA_UPDT:
 362                 DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
 363                 if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
 364                         /** @todo NGS Check for buffer overflow? */
 365                         dwc_otg_read_packet(core_if,
 366                                             ep->dwc_ep.xfer_buff,
 367                                             status.b.bcnt);
 368                         ep->dwc_ep.xfer_count += status.b.bcnt;
 369                         ep->dwc_ep.xfer_buff += status.b.bcnt;
 370                 }
 371                 break;
 372         case DWC_STS_XFER_COMP:
 373                 DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
 374                 break;
 375         case DWC_DSTS_SETUP_COMP:
 376 #ifdef DEBUG_EP0
 377                 DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
 378 #endif
 379                 break;
 380         case DWC_DSTS_SETUP_UPDT:
 381                 dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
 382 #ifdef DEBUG_EP0
 383                 DWC_DEBUGPL(DBG_PCD,
 384                             "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
 385                             pcd->setup_pkt->req.bmRequestType,
 386                             pcd->setup_pkt->req.bRequest,
 387                             UGETW(pcd->setup_pkt->req.wValue),
 388                             UGETW(pcd->setup_pkt->req.wIndex),
 389                             UGETW(pcd->setup_pkt->req.wLength));
 390 #endif
 391                 ep->dwc_ep.xfer_count += status.b.bcnt;
 392                 break;
 393         default:
 394                 DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
 395                             status.b.pktsts);
 396                 break;
 397         }
 398
 399         /* Enable the Rx Status Queue Level interrupt */
 400         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
 401         /* Clear interrupt */
 402         gintsts.d32 = 0;
 403         gintsts.b.rxstsqlvl = 1;
 404         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
 405
 406         /* DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); */
 407         return 1;
 408 }
 409
 410 /**
 411  * This function examines the Device IN Token Learning Queue to
 412  * determine the EP number of the last IN token received.  This
 413  * implementation is for the Mass Storage device where there are only
 414  * 2 IN EPs (Control-IN and BULK-IN).
 415  *
 416  * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
 417  * are 8 EP Numbers in each of the other possible DTKNQ Registers.
 418  *
 419  * @param core_if Programming view of DWC_otg controller.
 420  *
 421  */
 422 static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
 423 {
 424         dwc_otg_device_global_regs_t *dev_global_regs =
 425             core_if->dev_if->dev_global_regs;
 426         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
 427         /* Number of Token Queue Registers */
 428         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
 429         dtknq1_data_t dtknqr1;
 430         uint32_t in_tkn_epnums[4];
 431         int ndx = 0;
 432         int i = 0;
 433         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
 434         int epnum = 0;
 435
 436         /* DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); */
 437
 438         /* Read the DTKNQ Registers */
 439         for (i = 0; i < DTKNQ_REG_CNT; i++) {
 440                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
 441                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
 442                             in_tkn_epnums[i]);
 443                 if (addr == &dev_global_regs->dvbusdis) {
 444                         addr = &dev_global_regs->dtknqr3_dthrctl;
 445                 } else {
 446                         ++addr;
 447                 }
 448
 449         }
 450
 451         /* Copy the DTKNQR1 data to the bit field. */
 452         dtknqr1.d32 = in_tkn_epnums[0];
 453         /* Get the EP numbers */
 454         in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
 455         ndx = dtknqr1.b.intknwptr - 1;
 456
 457         /* DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); */
 458         if (ndx == -1) {
 459                 /** @todo Find a simpler way to calculate the max
 460                  * queue position.*/
 461                 int cnt = TOKEN_Q_DEPTH;
 462                 if (TOKEN_Q_DEPTH <= 6) {
 463                         cnt = TOKEN_Q_DEPTH - 1;
 464                 } else if (TOKEN_Q_DEPTH <= 14) {
 465                         cnt = TOKEN_Q_DEPTH - 7;
 466                 } else if (TOKEN_Q_DEPTH <= 22) {
 467                         cnt = TOKEN_Q_DEPTH - 15;
 468                 } else {
 469                         cnt = TOKEN_Q_DEPTH - 23;
 470                 }
 471                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
 472         } else {
 473                 if (ndx <= 5) {
 474                         epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
 475                 } else if (ndx <= 13) {
 476                         ndx -= 6;
 477                         epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
 478                 } else if (ndx <= 21) {
 479                         ndx -= 14;
 480                         epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
 481                 } else if (ndx <= 29) {
 482                         ndx -= 22;
 483                         epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
 484                 }
 485         }
 486         /* DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); */
 487         return epnum;
 488 }
 489
 490 /**
 491  * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
 492  * The active request is checked for the next packet to be loaded into
 493  * the non-periodic Tx FIFO.
 494  */
 495 int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
 496 {
 497         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
 498         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
 499         dwc_otg_dev_in_ep_regs_t *ep_regs;
 500         gnptxsts_data_t txstatus = {.d32 = 0 };
 501         gintsts_data_t gintsts;
 502
 503         int epnum = 0;
 504         dwc_otg_pcd_ep_t *ep = 0;
 505         uint32_t len = 0;
 506         int dwords;
 507
 508         /* Get the epnum from the IN Token Learning Queue. */
 509         epnum = get_ep_of_last_in_token(core_if);
 510         ep = get_in_ep(pcd, epnum);
 511
 512         DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
 513
 514         ep_regs = core_if->dev_if->in_ep_regs[epnum];
 515
 516         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
 517         if (len > ep->dwc_ep.maxpacket) {
 518                 len = ep->dwc_ep.maxpacket;
 519         }
 520         dwords = (len + 3) / 4;
 521
 522         /* While there is space in the queue and space in the FIFO and
 523          * More data to tranfer, Write packets to the Tx FIFO */
 524         txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
 525         DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
 526
 527         while (txstatus.b.nptxqspcavail > 0 &&
 528                txstatus.b.nptxfspcavail > dwords &&
 529                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
 530                 /* Write the FIFO */
 531                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
 532                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
 533
 534                 if (len > ep->dwc_ep.maxpacket) {
 535                         len = ep->dwc_ep.maxpacket;
 536                 }
 537
 538                 dwords = (len + 3) / 4;
 539                 txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
 540                 DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
 541         }
 542
 543         DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
 544                     DWC_READ_REG32(&global_regs->gnptxsts));
 545
 546         /* Clear interrupt */
 547         gintsts.d32 = 0;
 548         gintsts.b.nptxfempty = 1;
 549         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
 550
 551         return 1;
 552 }
 553
 554 /**
 555  * This function is called when dedicated Tx FIFO Empty interrupt occurs.
 556  * The active request is checked for the next packet to be loaded into
 557  * apropriate Tx FIFO.
 558  */
 559 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
 560 {
 561         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
 562         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
 563         dwc_otg_dev_in_ep_regs_t *ep_regs;
 564         dtxfsts_data_t txstatus = {.d32 = 0 };
 565         dwc_otg_pcd_ep_t *ep = 0;
 566         uint32_t len = 0;
 567         int dwords;
 568
 569         ep = get_in_ep(pcd, epnum);
 570
 571         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
 572
 573         ep_regs = core_if->dev_if->in_ep_regs[epnum];
 574
 575         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
 576
 577         if (len > ep->dwc_ep.maxpacket) {
 578                 len = ep->dwc_ep.maxpacket;
 579         }
 580
 581         dwords = (len + 3) / 4;
 582
 583         /* While there is space in the queue and space in the FIFO and
 584          * More data to tranfer, Write packets to the Tx FIFO */
 585         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
 586         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
 587
 588         while (txstatus.b.txfspcavail > dwords &&
 589                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
 590                ep->dwc_ep.xfer_len != 0) {
 591                 /* Write the FIFO */
 592                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
 593
 594                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
 595                 if (len > ep->dwc_ep.maxpacket) {
 596                         len = ep->dwc_ep.maxpacket;
 597                 }
 598
 599                 dwords = (len + 3) / 4;
 600                 txstatus.d32 =
 601                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
 602                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
 603                             txstatus.d32);
 604         }
 605
 606         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
 607                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
 608
 609         return 1;
 610 }
 611
 612 /**
 613  * This function is called when the Device is disconnected. It stops
 614  * any active requests and informs the Gadget driver of the
 615  * disconnect.
 616  */
 617 void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
 618 {
 619         int i, num_in_eps, num_out_eps;
 620         dwc_otg_pcd_ep_t *ep;
 621         gintmsk_data_t intr_mask = {.d32 = 0 };
 622
 623         DWC_SPINLOCK(pcd->lock);
 624
 625         num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
 626         num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
 627
 628         DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
 629         /* don't disconnect drivers more than once */
 630         if (pcd->ep0state == EP0_DISCONNECT) {
 631                 DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
 632                 DWC_SPINUNLOCK(pcd->lock);
 633                 return;
 634         }
 635         pcd->ep0state = EP0_DISCONNECT;
 636
 637         /* Reset the OTG state. */
 638         dwc_otg_pcd_update_otg(pcd, 1);
 639
 640         /* Disable the NP Tx Fifo Empty Interrupt. */
 641         intr_mask.b.nptxfempty = 1;
 642         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
 643                          intr_mask.d32, 0);
 644
 645         /* Flush the FIFOs */
 646         /**@todo NGS Flush Periodic FIFOs */
 647         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
 648         dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
 649
 650         /* prevent new request submissions, kill any outstanding requests  */
 651         ep = &pcd->ep0;
 652         dwc_otg_request_nuke(ep);
 653         /* prevent new request submissions, kill any outstanding requests  */
 654         for (i = 0; i < num_in_eps; i++) {
 655                 dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
 656                 dwc_otg_request_nuke(ep);
 657         }
 658         /* prevent new request submissions, kill any outstanding requests  */
 659         for (i = 0; i < num_out_eps; i++) {
 660                 dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
 661                 dwc_otg_request_nuke(ep);
 662         }
 663
 664         /* report disconnect; the driver is already quiesced */
 665         if (pcd->fops->disconnect) {
 666                 DWC_SPINUNLOCK(pcd->lock);
 667                 pcd->fops->disconnect(pcd);
 668                 DWC_SPINLOCK(pcd->lock);
 669         }
 670         DWC_SPINUNLOCK(pcd->lock);
 671 }
 672
 673 /**
 674  * This interrupt indicates that ...
 675  */
 676 int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
 677 {
 678         gintmsk_data_t intr_mask = {.d32 = 0 };
 679         gintsts_data_t gintsts;
 680
 681         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
 682         intr_mask.b.i2cintr = 1;
 683         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
 684                          intr_mask.d32, 0);
 685
 686         /* Clear interrupt */
 687         gintsts.d32 = 0;
 688         gintsts.b.i2cintr = 1;
 689         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
 690                         gintsts.d32);
 691         return 1;
 692 }
 693
 694 /**
 695  * This interrupt indicates that ...
 696  */
 697 int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
 698 {
 699         gintsts_data_t gintsts;
 700 #if defined(VERBOSE)
 701         DWC_PRINTF("Early Suspend Detected\n");
 702 #endif
 703
 704         /* Clear interrupt */
 705         gintsts.d32 = 0;
 706         gintsts.b.erlysuspend = 1;
 707         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
 708                         gintsts.d32);
 709         return 1;
 710 }
 711
 712 /**
 713  * This function configures EPO to receive SETUP packets.
 714  *
 715  * @todo NGS: Update the comments from the HW FS.
 716  *
 717  *      -# Program the following fields in the endpoint specific registers
 718  *      for Control OUT EP 0, in order to receive a setup packet
 719  *      - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
 720  *        setup packets)
 721  *      - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
 722  *        to back setup packets)
 723  *              - In DMA mode, DOEPDMA0 Register with a memory address to
 724  *                store any setup packets received
 725  *
 726  * @param core_if Programming view of DWC_otg controller.
 727  * @param pcd     Programming view of the PCD.
 728  */
 729 static inline void ep0_out_start(dwc_otg_core_if_t *core_if,
 730                                  dwc_otg_pcd_t *pcd)
 731 {
 732         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
 733         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
 734         dwc_otg_dev_dma_desc_t *dma_desc;
 735         depctl_data_t doepctl = {.d32 = 0 };
 736
 737 #ifdef VERBOSE
 738         DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
 739                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
 740 #endif
 741         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
 742                 doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
 743                 if (doepctl.b.epena) {
 744                         return;
 745                 }
 746         }
 747
 748         doeptsize0.b.supcnt = 1;
 749         doeptsize0.b.pktcnt = 1;
 750         doeptsize0.b.xfersize = 8 * 3;
 751
 752         if (core_if->dma_enable) {
 753                 if (!core_if->dma_desc_enable) {
 754                         /** put here as for Hermes mode deptisz register should not be written */
 755                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
 756                                         doeptsize0.d32);
 757
 758                         /** @todo dma needs to handle multiple setup packets (up to 3) */
 759                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
 760                                         pcd->setup_pkt_dma_handle);
 761                 } else {
 762                         dev_if->setup_desc_index =
 763                             (dev_if->setup_desc_index + 1) & 1;
 764                         dma_desc =
 765                             dev_if->setup_desc_addr[dev_if->setup_desc_index];
 766
 767                         /** DMA Descriptor Setup */
 768                         dma_desc->status.b.bs = BS_HOST_BUSY;
 769                         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
 770                                 dma_desc->status.b.sr = 0;
 771                                 dma_desc->status.b.mtrf = 0;
 772                         }
 773                         dma_desc->status.b.l = 1;
 774                         dma_desc->status.b.ioc = 1;
 775                         dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
 776                         dma_desc->buf = pcd->setup_pkt_dma_handle;
 777                         dma_desc->status.b.sts = 0;
 778                         dma_desc->status.b.bs = BS_HOST_READY;
 779
 780                         /** DOEPDMA0 Register write */
 781                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
 782                                         dev_if->dma_setup_desc_addr
 783                                         [dev_if->setup_desc_index]);
 784                 }
 785
 786         } else {
 787                 /** put here as for Hermes mode deptisz register should not be written */
 788                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
 789                                 doeptsize0.d32);
 790         }
 791
 792         /** DOEPCTL0 Register write cnak will be set after setup interrupt */
 793         doepctl.d32 = 0;
 794         doepctl.b.epena = 1;
 795         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
 796                 doepctl.b.cnak = 1;
 797                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
 798         } else {
 799                 DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0,
 800                                  doepctl.d32);
 801         }
 802
 803 #ifdef VERBOSE
 804         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
 805                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
 806         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
 807                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
 808 #endif
 809 }
 810
 811 /**
 812  * This interrupt occurs when a USB Reset is detected. When the USB
 813  * Reset Interrupt occurs the device state is set to DEFAULT and the
 814  * EP0 state is set to IDLE.
 815  *      -#      Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
 816  *      -#      Unmask the following interrupt bits
 817  *              - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
 818  *      - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
 819  *      - DOEPMSK.SETUP = 1
 820  *      - DOEPMSK.XferCompl = 1
 821  *      - DIEPMSK.XferCompl = 1
 822  *      - DIEPMSK.TimeOut = 1
 823  *      -# Program the following fields in the endpoint specific registers
 824  *      for Control OUT EP 0, in order to receive a setup packet
 825  *      - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
 826  *        setup packets)
 827  *      - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
 828  *        to back setup packets)
 829  *              - In DMA mode, DOEPDMA0 Register with a memory address to
 830  *                store any setup packets received
 831  * At this point, all the required initialization, except for enabling
 832  * the control 0 OUT endpoint is done, for receiving SETUP packets.
 833  */
 834 int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t *pcd)
 835 {
 836         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
 837         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
 838         depctl_data_t doepctl = {.d32 = 0 };
 839         depctl_data_t diepctl = {.d32 = 0 };
 840         daint_data_t daintmsk = {.d32 = 0 };
 841         doepmsk_data_t doepmsk = {.d32 = 0 };
 842         diepmsk_data_t diepmsk = {.d32 = 0 };
 843         dcfg_data_t dcfg = {.d32 = 0 };
 844         grstctl_t resetctl = {.d32 = 0 };
 845         dctl_data_t dctl = {.d32 = 0 };
 846         int i = 0;
 847         gintsts_data_t gintsts;
 848         pcgcctl_data_t power = {.d32 = 0 };
 849
 850         power.d32 = DWC_READ_REG32(core_if->pcgcctl);
 851         if (power.b.stoppclk) {
 852                 power.d32 = 0;
 853                 power.b.stoppclk = 1;
 854                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
 855
 856                 power.b.pwrclmp = 1;
 857                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
 858
 859                 power.b.rstpdwnmodule = 1;
 860                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
 861         }
 862
 863         core_if->lx_state = DWC_OTG_L0;
 864         core_if->otg_sts = 0;
 865
 866         DWC_PRINTF("USB RESET\n");
 867 #ifdef DWC_EN_ISOC
 868         for (i = 1; i < 16; ++i) {
 869                 dwc_otg_pcd_ep_t *ep;
 870                 dwc_ep_t *dwc_ep;
 871                 ep = get_in_ep(pcd, i);
 872                 if (ep != 0) {
 873                         dwc_ep = &ep->dwc_ep;
 874                         dwc_ep->next_frame = 0xffffffff;
 875                 }
 876         }
 877 #endif /* DWC_EN_ISOC */
 878
 879         /* reset the HNP settings */
 880         dwc_otg_pcd_update_otg(pcd, 1);
 881
 882         /* Clear the Remote Wakeup Signalling */
 883         dctl.b.rmtwkupsig = 1;
 884         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
 885
 886         /* Set NAK for all OUT EPs */
 887         doepctl.b.snak = 1;
 888         for (i = 0; i <= dev_if->num_out_eps; i++) {
 889                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
 890         }
 891
 892         /* Flush the NP Tx FIFO */
 893         dwc_otg_flush_tx_fifo(core_if, 0x10);
 894         /* Flush the Learning Queue */
 895         resetctl.b.intknqflsh = 1;
 896         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
 897
 898         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
 899                 core_if->start_predict = 0;
 900                 for (i = 0; i <= core_if->dev_if->num_in_eps; ++i) {
 901                         core_if->nextep_seq[i] = 0xff; /*0xff - EP not active */
 902                 }
 903                 core_if->nextep_seq[0] = 0;
 904                 core_if->first_in_nextep_seq = 0;
 905                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
 906                 diepctl.b.nextep = 0;
 907                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
 908
 909                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
 910                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
 911                 dcfg.b.epmscnt = 2;
 912                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
 913
 914                 DWC_DEBUGPL(DBG_PCDV,
 915                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
 916                             __func__, core_if->first_in_nextep_seq);
 917                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
 918                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
 919                 }
 920         }
 921
 922         if (core_if->multiproc_int_enable) {
 923                 daintmsk.b.inep0 = 1;
 924                 daintmsk.b.outep0 = 1;
 925                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
 926                                 daintmsk.d32);
 927
 928                 doepmsk.b.setup = 1;
 929                 doepmsk.b.xfercompl = 1;
 930                 doepmsk.b.ahberr = 1;
 931                 doepmsk.b.epdisabled = 1;
 932
 933                 if ((core_if->dma_desc_enable) ||
 934                     (core_if->dma_enable
 935                      && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
 936                         doepmsk.b.stsphsercvd = 1;
 937                 }
 938                 if (core_if->dma_desc_enable)
 939                         doepmsk.b.bna = 1;
 940 /*
 941                 doepmsk.b.babble = 1;
 942                 doepmsk.b.nyet = 1;
 943
 944                 if (core_if->dma_enable) {
 945                         doepmsk.b.nak = 1;
 946                 }
 947 */
 948                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
 949                                 doepmsk.d32);
 950
 951                 diepmsk.b.xfercompl = 1;
 952                 diepmsk.b.timeout = 1;
 953                 diepmsk.b.epdisabled = 1;
 954                 diepmsk.b.ahberr = 1;
 955                 diepmsk.b.intknepmis = 1;
 956                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
 957                         diepmsk.b.intknepmis = 0;
 958
 959 /*              if (core_if->dma_desc_enable) {
 960                         diepmsk.b.bna = 1;
 961                 }
 962 */
 963 /*
 964                 if (core_if->dma_enable) {
 965                         diepmsk.b.nak = 1;
 966                 }
 967 */
 968                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
 969                                 diepmsk.d32);
 970         } else {
 971                 daintmsk.b.inep0 = 1;
 972                 daintmsk.b.outep0 = 1;
 973                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
 974                                 daintmsk.d32);
 975
 976                 doepmsk.b.setup = 1;
 977                 doepmsk.b.xfercompl = 1;
 978                 doepmsk.b.ahberr = 1;
 979                 doepmsk.b.epdisabled = 1;
 980
 981                 if ((core_if->dma_desc_enable) ||
 982                     (core_if->dma_enable
 983                      && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
 984                         doepmsk.b.stsphsercvd = 1;
 985                 }
 986                 if (core_if->dma_desc_enable)
 987                         doepmsk.b.bna = 1;
 988                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
 989
 990                 diepmsk.b.xfercompl = 1;
 991                 diepmsk.b.timeout = 1;
 992                 diepmsk.b.epdisabled = 1;
 993                 diepmsk.b.ahberr = 1;
 994                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
 995                         diepmsk.b.intknepmis = 0;
 996 /*
 997                 if (core_if->dma_desc_enable) {
 998                         diepmsk.b.bna = 1;
 999                 }
1000 */
1001
1002                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
1003         }
1004
1005         /* Reset Device Address */
1006         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1007         dcfg.b.devaddr = 0;
1008         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1009
1010         /* setup EP0 to receive SETUP packets */
1011         if (core_if->snpsid <= OTG_CORE_REV_2_94a)
1012                 ep0_out_start(core_if, pcd);
1013
1014         /* Clear interrupt */
1015         gintsts.d32 = 0;
1016         gintsts.b.usbreset = 1;
1017         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1018
1019         return 1;
1020 }
1021
1022 /**
1023  * Get the device speed from the device status register and convert it
1024  * to USB speed constant.
1025  *
1026  * @param core_if Programming view of DWC_otg controller.
1027  */
1028 static int get_device_speed(dwc_otg_core_if_t *core_if)
1029 {
1030         dsts_data_t dsts;
1031         int speed = 0;
1032         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
1033
1034         switch (dsts.b.enumspd) {
1035         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
1036                 speed = USB_SPEED_HIGH;
1037                 break;
1038         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
1039         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
1040                 speed = USB_SPEED_FULL;
1041                 break;
1042
1043         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
1044                 speed = USB_SPEED_LOW;
1045                 break;
1046         }
1047
1048         return speed;
1049 }
1050
1051 /**
1052  * Read the device status register and set the device speed in the
1053  * data structure.
1054  * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
1055  */
1056 int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
1057 {
1058         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1059         gintsts_data_t gintsts;
1060         gusbcfg_data_t gusbcfg;
1061         dwc_otg_core_global_regs_t *global_regs =
1062             GET_CORE_IF(pcd)->core_global_regs;
1063         uint8_t utmi16b, utmi8b;
1064         int speed;
1065
1066         DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
1067
1068         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
1069                 utmi16b = 5;    /* vahrama old value was 6; */
1070                 utmi8b = 9;
1071         } else {
1072                 utmi16b = 4;
1073                 utmi8b = 8;
1074         }
1075         dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
1076         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
1077                 ep0_out_start(GET_CORE_IF(pcd), pcd);
1078         }
1079 #ifdef DEBUG_EP0
1080         print_ep0_state(pcd);
1081 #endif
1082
1083         if (pcd->ep0state == EP0_DISCONNECT) {
1084                 pcd->ep0state = EP0_IDLE;
1085         } else if (pcd->ep0state == EP0_STALL) {
1086                 pcd->ep0state = EP0_IDLE;
1087         }
1088
1089         pcd->ep0state = EP0_IDLE;
1090
1091         ep0->stopped = 0;
1092
1093         speed = get_device_speed(GET_CORE_IF(pcd));
1094         pcd->fops->connect(pcd, speed);
1095
1096         /* Set USB turnaround time based on device speed and PHY interface. */
1097         gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1098         if (speed == USB_SPEED_HIGH) {
1099                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
1100                     DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
1101                         /* ULPI interface */
1102                         gusbcfg.b.usbtrdtim = 9;
1103                 }
1104                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
1105                     DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
1106                         /* UTMI+ interface */
1107                         if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
1108                                 gusbcfg.b.usbtrdtim = utmi8b;
1109                         } else if (GET_CORE_IF(pcd)->hwcfg4.
1110                                    b.utmi_phy_data_width == 1) {
1111                                 gusbcfg.b.usbtrdtim = utmi16b;
1112                         } else if (GET_CORE_IF(pcd)->
1113                                    core_params->phy_utmi_width == 8) {
1114                                 gusbcfg.b.usbtrdtim = utmi8b;
1115                         } else {
1116                                 gusbcfg.b.usbtrdtim = utmi16b;
1117                         }
1118                 }
1119                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
1120                     DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
1121                         /* UTMI+  OR  ULPI interface */
1122                         if (gusbcfg.b.ulpi_utmi_sel == 1) {
1123                                 /* ULPI interface */
1124                                 gusbcfg.b.usbtrdtim = 9;
1125                         } else {
1126                                 /* UTMI+ interface */
1127                                 if (GET_CORE_IF(pcd)->
1128                                     core_params->phy_utmi_width == 16) {
1129                                         gusbcfg.b.usbtrdtim = utmi16b;
1130                                 } else {
1131                                         gusbcfg.b.usbtrdtim = utmi8b;
1132                                 }
1133                         }
1134                 }
1135         } else {
1136                 /* Full or low speed */
1137                 gusbcfg.b.usbtrdtim = 9;
1138         }
1139         DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
1140
1141         /* Clear interrupt */
1142         gintsts.d32 = 0;
1143         gintsts.b.enumdone = 1;
1144         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
1145                         gintsts.d32);
1146         return 1;
1147 }
1148
1149 /**
1150  * This interrupt indicates that the ISO OUT Packet was dropped due to
1151  * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs
1152  * read all the data from the Rx FIFO.
1153  */
1154 int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
1155 {
1156         gintmsk_data_t intr_mask = {.d32 = 0 };
1157         gintsts_data_t gintsts;
1158
1159         DWC_WARN("INTERRUPT Handler not implemented for %s\n",
1160                  "ISOC Out Dropped");
1161
1162         intr_mask.b.isooutdrop = 1;
1163         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
1164                          intr_mask.d32, 0);
1165
1166         /* Clear interrupt */
1167         gintsts.d32 = 0;
1168         gintsts.b.isooutdrop = 1;
1169         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
1170                         gintsts.d32);
1171
1172         return 1;
1173 }
1174
1175 /**
1176  * This interrupt indicates the end of the portion of the micro-frame
1177  * for periodic transactions.  If there is a periodic transaction for
1178  * the next frame, load the packets into the EP periodic Tx FIFO.
1179  */
1180 int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
1181 {
1182         gintmsk_data_t intr_mask = {.d32 = 0 };
1183         gintsts_data_t gintsts;
1184         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
1185
1186         intr_mask.b.eopframe = 1;
1187         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
1188                          intr_mask.d32, 0);
1189
1190         /* Clear interrupt */
1191         gintsts.d32 = 0;
1192         gintsts.b.eopframe = 1;
1193         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
1194                         gintsts.d32);
1195
1196         return 1;
1197 }
1198
1199 /**
1200  * This interrupt indicates that EP of the packet on the top of the
1201  * non-periodic Tx FIFO does not match EP of the IN Token received.
1202  *
1203  * The "Device IN Token Queue" Registers are read to determine the
1204  * order the IN Tokens have been received. The non-periodic Tx FIFO
1205  * is flushed, so it can be reloaded in the order seen in the IN Token
1206  * Queue.
1207  */
1208 int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t *pcd)
1209 {
1210         gintsts_data_t gintsts;
1211         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1212         dctl_data_t dctl;
1213         gintmsk_data_t intr_mask = {.d32 = 0 };
1214
1215         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
1216                 core_if->start_predict = 1;
1217
1218                 DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
1219
1220                 gintsts.d32 =
1221                     DWC_READ_REG32(&core_if->core_global_regs->gintsts);
1222                 if (!gintsts.b.ginnakeff) {
1223                         /* Disable EP Mismatch interrupt */
1224                         intr_mask.d32 = 0;
1225                         intr_mask.b.epmismatch = 1;
1226                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
1227                                          intr_mask.d32, 0);
1228                         /* Enable the Global IN NAK Effective Interrupt */
1229                         intr_mask.d32 = 0;
1230                         intr_mask.b.ginnakeff = 1;
1231                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
1232                                          intr_mask.d32);
1233                         /* Set the global non-periodic IN NAK handshake */
1234                         dctl.d32 =
1235                             DWC_READ_REG32(&core_if->dev_if->
1236                                            dev_global_regs->dctl);
1237                         dctl.b.sgnpinnak = 1;
1238                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1239                                         dctl.d32);
1240                 } else {
1241                         DWC_PRINTF
1242                             ("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
1243                 }
1244                 /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
1245                  * handler after Global IN NAK Effective interrupt will be asserted */
1246         }
1247         /* Clear interrupt */
1248         gintsts.d32 = 0;
1249         gintsts.b.epmismatch = 1;
1250         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1251
1252         return 1;
1253 }
1254
1255 /**
1256  * This interrupt is valid only in DMA mode. This interrupt indicates that the
1257  * core has stopped fetching data for IN endpoints due to the unavailability of
1258  * TxFIFO space or Request Queue space. This interrupt is used by the
1259  * application for an endpoint mismatch algorithm.
1260  *
1261  * @param pcd The PCD
1262  */
1263 int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t *pcd)
1264 {
1265         gintsts_data_t gintsts;
1266         gintmsk_data_t gintmsk_data;
1267         dctl_data_t dctl;
1268         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1269         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
1270
1271         /* Clear the global non-periodic IN NAK handshake */
1272         dctl.d32 = 0;
1273         dctl.b.cgnpinnak = 1;
1274         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,
1275                          dctl.d32);
1276
1277         /* Mask GINTSTS.FETSUSP interrupt */
1278         gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
1279         gintmsk_data.b.fetsusp = 0;
1280         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
1281
1282         /* Clear interrupt */
1283         gintsts.d32 = 0;
1284         gintsts.b.fetsusp = 1;
1285         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1286
1287         return 1;
1288 }
1289
1290 /**
1291  * This funcion stalls EP0.
1292  */
1293 static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
1294 {
1295         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1296         usb_device_request_t *ctrl = &pcd->setup_pkt->req;
1297         DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
1298                  ctrl->bmRequestType, ctrl->bRequest, err_val);
1299
1300         ep0->dwc_ep.is_in = 1;
1301         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
1302         ep0->dwc_ep.is_in = 0;
1303         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
1304         pcd->ep0.stopped = 1;
1305         pcd->ep0state = EP0_IDLE;
1306         ep0_out_start(GET_CORE_IF(pcd), pcd);
1307 }
1308
1309 /**
1310  * This functions delegates the setup command to the gadget driver.
1311  */
1312 static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
1313                                    usb_device_request_t *ctrl)
1314 {
1315         int ret = 0;
1316         DWC_SPINUNLOCK(pcd->lock);
1317         ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
1318         if (spin_is_locked((spinlock_t *) pcd->lock))
1319                 DWC_WARN("%s warning: pcd->lock locked without unlock\n",
1320                          __func__);
1321         DWC_SPINLOCK(pcd->lock);
1322         if (ret < 0) {
1323                 ep0_do_stall(pcd, ret);
1324         }
1325
1326         /** @todo This is a g_file_storage gadget driver specific
1327          * workaround: a DELAYED_STATUS result from the fsg_setup
1328          * routine will result in the gadget queueing a EP0 IN status
1329          * phase for a two-stage control transfer. Exactly the same as
1330          * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
1331          * specific request.  Need a generic way to know when the gadget
1332          * driver will queue the status phase. Can we assume when we
1333          * call the gadget driver setup() function that it will always
1334          * queue and require the following flag? Need to look into
1335          * this.
1336          */
1337
1338         if (ret == 256 + 999) {
1339                 pcd->request_config = 1;
1340         }
1341 }
1342
1343 #ifdef DWC_UTE_CFI
1344 /**
1345  * This functions delegates the CFI setup commands to the gadget driver.
1346  * This function will return a negative value to indicate a failure.
1347  */
1348 static inline int cfi_gadget_setup(dwc_otg_pcd_t *pcd,
1349                                    struct cfi_usb_ctrlrequest *ctrl_req)
1350 {
1351         int ret = 0;
1352
1353         if (pcd->fops && pcd->fops->cfi_setup) {
1354                 DWC_SPINUNLOCK(pcd->lock);
1355                 ret = pcd->fops->cfi_setup(pcd, ctrl_req);
1356                 DWC_SPINLOCK(pcd->lock);
1357                 if (ret < 0) {
1358                         ep0_do_stall(pcd, ret);
1359                         return ret;
1360                 }
1361         }
1362
1363         return ret;
1364 }
1365 #endif
1366
1367 /**
1368  * This function starts the Zero-Length Packet for the IN status phase
1369  * of a 2 stage control transfer.
1370  */
1371 static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
1372 {
1373         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1374         if (pcd->ep0state == EP0_STALL) {
1375                 return;
1376         }
1377
1378         pcd->ep0state = EP0_IN_STATUS_PHASE;
1379
1380         /* Prepare for more SETUP Packets */
1381         DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
1382         if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
1383             && (pcd->core_if->dma_desc_enable)
1384             && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
1385                 DWC_DEBUGPL(DBG_PCDV,
1386                             "Data terminated wait next packet in out_desc_addr\n");
1387                 pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
1388                 pcd->data_terminated = 1;
1389         }
1390         ep0->dwc_ep.xfer_len = 0;
1391         ep0->dwc_ep.xfer_count = 0;
1392         ep0->dwc_ep.is_in = 1;
1393         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
1394         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
1395
1396         /* Prepare for more SETUP Packets */
1397         /* ep0_out_start(GET_CORE_IF(pcd), pcd); */
1398 }
1399
1400 /**
1401  * This function starts the Zero-Length Packet for the OUT status phase
1402  * of a 2 stage control transfer.
1403  */
1404 static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
1405 {
1406         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1407         if (pcd->ep0state == EP0_STALL) {
1408                 DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
1409                 return;
1410         }
1411         pcd->ep0state = EP0_OUT_STATUS_PHASE;
1412
1413         DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
1414         ep0->dwc_ep.xfer_len = 0;
1415         ep0->dwc_ep.xfer_count = 0;
1416         ep0->dwc_ep.is_in = 0;
1417         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
1418         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
1419
1420         /* Prepare for more SETUP Packets */
1421         if (GET_CORE_IF(pcd)->dma_enable == 0) {
1422                 ep0_out_start(GET_CORE_IF(pcd), pcd);
1423         }
1424 }
1425
1426 /**
1427  * Clear the EP halt (STALL) and if pending requests start the
1428  * transfer.
1429  */
1430 static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
1431 {
1432         if (ep->dwc_ep.stall_clear_flag) {
1433                 /* Start Control Status Phase */
1434                 do_setup_in_status_phase(pcd);
1435                 return;
1436         }
1437
1438         dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
1439
1440         /* Reactive the EP */
1441         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
1442         if (ep->stopped) {
1443                 ep->stopped = 0;
1444                 /* If there is a request in the EP queue start it */
1445
1446                 /** @todo FIXME: this causes an EP mismatch in DMA mode.
1447                  * epmismatch not yet implemented. */
1448
1449                 /*
1450                  * Above fixme is solved by implmenting a tasklet to call the
1451                  * start_next_request(), outside of interrupt context at some
1452                  * time after the current time, after a clear-halt setup packet.
1453                  * Still need to implement ep mismatch in the future if a gadget
1454                  * ever uses more than one endpoint at once
1455                  */
1456                 ep->queue_sof = 1;
1457                 DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
1458         }
1459         /* Start Control Status Phase */
1460         do_setup_in_status_phase(pcd);
1461 }
1462
1463 /**
1464  * This function is called when the SET_FEATURE TEST_MODE Setup packet
1465  * is sent from the host.  The Device Control register is written with
1466  * the Test Mode bits set to the specified Test Mode.  This is done as
1467  * a tasklet so that the "Status" phase of the control transfer
1468  * completes before transmitting the TEST packets.
1469  *
1470  * @todo This has not been tested since the tasklet struct was put
1471  * into the PCD struct!
1472  *
1473  */
1474 void do_test_mode(void *data)
1475 {
1476         dctl_data_t dctl;
1477         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
1478         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1479         int test_mode = pcd->test_mode;
1480
1481         /* DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); */
1482
1483         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1484         switch (test_mode) {
1485         case 1:         /* TEST_J */
1486                 dctl.b.tstctl = 1;
1487                 break;
1488
1489         case 2:         /* TEST_K */
1490                 dctl.b.tstctl = 2;
1491                 break;
1492
1493         case 3:         /* TEST_SE0_NAK */
1494                 dctl.b.tstctl = 3;
1495                 break;
1496
1497         case 4:         /* TEST_PACKET */
1498                 dctl.b.tstctl = 4;
1499                 break;
1500
1501         case 5:         /* TEST_FORCE_ENABLE */
1502                 dctl.b.tstctl = 5;
1503                 break;
1504         case 7:
1505                 dwc_otg_set_hnpreq(core_if, 1);
1506         }
1507         DWC_PRINTF("test mode = %d\n", test_mode);
1508         core_if->test_mode = test_mode;
1509         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
1510 }
1511
1512 /**
1513  * This function process the GET_STATUS Setup Commands.
1514  */
1515 static inline void do_get_status(dwc_otg_pcd_t *pcd)
1516 {
1517         usb_device_request_t ctrl = pcd->setup_pkt->req;
1518         dwc_otg_pcd_ep_t *ep;
1519         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1520         uint16_t *status = pcd->status_buf;
1521         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1522
1523 #ifdef DEBUG_EP0
1524         DWC_DEBUGPL(DBG_PCD,
1525                     "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
1526                     ctrl.bmRequestType, ctrl.bRequest,
1527                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
1528                     UGETW(ctrl.wLength));
1529 #endif
1530
1531         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
1532         case UT_DEVICE:
1533                 if (UGETW(ctrl.wIndex) == 0xF000) {     /* OTG Status selector */
1534                         DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
1535                         DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
1536                         DWC_PRINTF("OTG CAP - %d, %d\n",
1537                                    core_if->core_params->otg_cap,
1538                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1539                         if (core_if->otg_ver == 1
1540                             && core_if->core_params->otg_cap ==
1541                             DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
1542                                 uint8_t *otgsts = (uint8_t *) pcd->status_buf;
1543                                 *otgsts = (core_if->otg_sts & 0x1);
1544                                 pcd->ep0_pending = 1;
1545                                 ep0->dwc_ep.start_xfer_buff =
1546                                     (uint8_t *) otgsts;
1547                                 ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
1548                                 ep0->dwc_ep.dma_addr =
1549                                     pcd->status_buf_dma_handle;
1550                                 ep0->dwc_ep.xfer_len = 1;
1551                                 ep0->dwc_ep.xfer_count = 0;
1552                                 ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
1553                                 dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
1554                                                            &ep0->dwc_ep);
1555                                 return;
1556                         } else {
1557                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1558                                 return;
1559                         }
1560                         break;
1561                 } else {
1562                         *status = 0x1;  /* Self powered */
1563                         *status |= pcd->remote_wakeup_enable << 1;
1564                         break;
1565                 }
1566         case UT_INTERFACE:
1567                 *status = 0;
1568                 break;
1569
1570         case UT_ENDPOINT:
1571                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
1572                 if (ep == 0 || UGETW(ctrl.wLength) > 2) {
1573                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1574                         return;
1575                 }
1576                 /** @todo check for EP stall */
1577                 *status = ep->stopped;
1578                 break;
1579         }
1580         pcd->ep0_pending = 1;
1581         ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
1582         ep0->dwc_ep.xfer_buff = (uint8_t *) status;
1583         ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
1584         ep0->dwc_ep.xfer_len = 2;
1585         ep0->dwc_ep.xfer_count = 0;
1586         ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
1587         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
1588 }
1589
1590 /**
1591  * This function process the SET_FEATURE Setup Commands.
1592  */
1593 static inline void do_set_feature(dwc_otg_pcd_t *pcd)
1594 {
1595         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1596         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1597         usb_device_request_t ctrl = pcd->setup_pkt->req;
1598         dwc_otg_pcd_ep_t *ep = 0;
1599         int32_t otg_cap_param = core_if->core_params->otg_cap;
1600         gotgctl_data_t gotgctl = {.d32 = 0 };
1601
1602         DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
1603                     ctrl.bmRequestType, ctrl.bRequest,
1604                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
1605                     UGETW(ctrl.wLength));
1606         DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
1607
1608         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
1609         case UT_DEVICE:
1610                 switch (UGETW(ctrl.wValue)) {
1611                 case UF_DEVICE_REMOTE_WAKEUP:
1612                         pcd->remote_wakeup_enable = 1;
1613                         break;
1614
1615                 case UF_TEST_MODE:
1616                         /* Setup the Test Mode tasklet to do the Test
1617                          * Packet generation after the SETUP Status
1618                          * phase has completed. */
1619
1620                         /** @todo This has not been tested since the
1621                          * tasklet struct was put into the PCD
1622                          * struct! */
1623                         pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
1624                         DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
1625                         break;
1626
1627                 case UF_DEVICE_B_HNP_ENABLE:
1628                         DWC_DEBUGPL(DBG_PCDV,
1629                                     "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1630
1631                         /* dev may initiate HNP */
1632                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
1633                                 gotgctl.b.devhnpen = 1;
1634                                 if (core_if->otg_ver == 1)
1635                                         DWC_MODIFY_REG32(&global_regs->gotgctl,
1636                                                          0, gotgctl.d32);
1637                                 else {
1638                                         pcd->b_hnp_enable = 1;
1639                                         dwc_otg_pcd_update_otg(pcd, 0);
1640                                         DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
1641                                         /**@todo Is the gotgctl.devhnpen cleared
1642                                          * by a USB Reset? */
1643                                         gotgctl.b.hnpreq = 1;
1644                                         DWC_WRITE_REG32(&global_regs->gotgctl,
1645                                                         gotgctl.d32);
1646                                 }
1647                         } else {
1648                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1649                                 return;
1650                         }
1651                         break;
1652
1653                 case UF_DEVICE_A_HNP_SUPPORT:
1654                         /* RH port supports HNP */
1655                         DWC_DEBUGPL(DBG_PCDV,
1656                                     "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
1657                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
1658                                 pcd->a_hnp_support = 1;
1659                                 dwc_otg_pcd_update_otg(pcd, 0);
1660                         } else {
1661                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1662                                 return;
1663                         }
1664                         break;
1665
1666                 case UF_DEVICE_A_ALT_HNP_SUPPORT:
1667                         /* other RH port does */
1668                         DWC_DEBUGPL(DBG_PCDV,
1669                                     "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1670                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
1671                                 pcd->a_alt_hnp_support = 1;
1672                                 dwc_otg_pcd_update_otg(pcd, 0);
1673                         } else {
1674                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1675                                 return;
1676                         }
1677                         break;
1678
1679                 default:
1680                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1681                         return;
1682
1683                 }
1684                 do_setup_in_status_phase(pcd);
1685                 break;
1686
1687         case UT_INTERFACE:
1688                 do_gadget_setup(pcd, &ctrl);
1689                 break;
1690
1691         case UT_ENDPOINT:
1692                 if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
1693                         ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
1694                         if (ep == 0) {
1695                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1696                                 return;
1697                         }
1698                         ep->stopped = 1;
1699                         dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
1700                 }
1701                 do_setup_in_status_phase(pcd);
1702                 break;
1703         }
1704 }
1705
1706 /**
1707  * This function process the CLEAR_FEATURE Setup Commands.
1708  */
1709 static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
1710 {
1711         usb_device_request_t ctrl = pcd->setup_pkt->req;
1712         dwc_otg_pcd_ep_t *ep = 0;
1713
1714         DWC_DEBUGPL(DBG_PCD,
1715                     "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
1716                     ctrl.bmRequestType, ctrl.bRequest,
1717                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
1718                     UGETW(ctrl.wLength));
1719
1720         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
1721         case UT_DEVICE:
1722                 switch (UGETW(ctrl.wValue)) {
1723                 case UF_DEVICE_REMOTE_WAKEUP:
1724                         pcd->remote_wakeup_enable = 0;
1725                         break;
1726
1727                 case UF_TEST_MODE:
1728                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1729                         break;
1730
1731                 default:
1732                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1733                         return;
1734                 }
1735                 do_setup_in_status_phase(pcd);
1736                 break;
1737
1738         case UT_ENDPOINT:
1739                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
1740                 if (ep == 0) {
1741                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
1742                         return;
1743                 }
1744
1745                 pcd_clear_halt(pcd, ep);
1746
1747                 break;
1748         }
1749 }
1750
1751 /**
1752  * This function process the SET_ADDRESS Setup Commands.
1753  */
1754 static inline void do_set_address(dwc_otg_pcd_t *pcd)
1755 {
1756         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
1757         usb_device_request_t ctrl = pcd->setup_pkt->req;
1758
1759         if (ctrl.bmRequestType == UT_DEVICE) {
1760                 dcfg_data_t dcfg = {.d32 = 0 };
1761
1762 #ifdef DEBUG_EP0
1763                 /* DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); */
1764 #endif
1765                 dcfg.b.devaddr = UGETW(ctrl.wValue);
1766                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
1767                 do_setup_in_status_phase(pcd);
1768         }
1769 }
1770
1771 /**
1772  *      This function processes SETUP commands. In Linux, the USB Command
1773  *      processing is done in two places - the first being the PCD and the
1774  *      second in the Gadget Driver (for example, the File-Backed Storage
1775  *      Gadget Driver).
1776  *
1777  * <table>
1778  * <tr><td>Command      </td><td>Driver </td><td>Description</td></tr>
1779  *
1780  * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
1781  * defined in chapter 9 of the USB 2.0 Specification chapter 9
1782  * </td></tr>
1783  *
1784  * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
1785  * requests are the ENDPOINT_HALT feature is procesed, all others the
1786  * interface requests are ignored.</td></tr>
1787  *
1788  * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
1789  * requests are processed by the PCD.  Interface requests are passed
1790  * to the Gadget Driver.</td></tr>
1791  *
1792  * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
1793  * with device address received </td></tr>
1794  *
1795  * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
1796  * requested descriptor</td></tr>
1797  *
1798  * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
1799  * not implemented by any of the existing Gadget Drivers.</td></tr>
1800  *
1801  * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
1802  * all EPs and enable EPs for new configuration.</td></tr>
1803  *
1804  * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
1805  * the current configuration</td></tr>
1806  *
1807  * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
1808  * EPs and enable EPs for new configuration.</td></tr>
1809  *
1810  * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
1811  * current interface.</td></tr>
1812  *
1813  * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
1814  * message.</td></tr>
1815  * </table>
1816  *
1817  * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
1818  * processed by pcd_setup. Calling the Function Driver's setup function from
1819  *pcd_setup processes the gadget SETUP commands.
1820  */
1821 static inline void pcd_setup(dwc_otg_pcd_t *pcd)
1822 {
1823         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
1824         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1825         usb_device_request_t ctrl = pcd->setup_pkt->req;
1826         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
1827
1828         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
1829
1830 #ifdef DWC_UTE_CFI
1831         int retval = 0;
1832         struct cfi_usb_ctrlrequest cfi_req;
1833 #endif
1834
1835         doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
1836
1837 #ifdef DEBUG_EP0
1838         DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1839                     ctrl.bmRequestType, ctrl.bRequest,
1840                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
1841                     UGETW(ctrl.wLength));
1842 #endif
1843
1844         /* Clean up the request queue */
1845         dwc_otg_request_nuke(ep0);
1846         ep0->stopped = 0;
1847
1848         if (ctrl.bmRequestType & UE_DIR_IN) {
1849                 ep0->dwc_ep.is_in = 1;
1850                 pcd->ep0state = EP0_IN_DATA_PHASE;
1851         } else {
1852                 ep0->dwc_ep.is_in = 0;
1853                 pcd->ep0state = EP0_OUT_DATA_PHASE;
1854         }
1855
1856         if (UGETW(ctrl.wLength) == 0) {
1857                 ep0->dwc_ep.is_in = 1;
1858                 pcd->ep0state = EP0_IN_STATUS_PHASE;
1859         }
1860
1861         if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
1862
1863 #ifdef DWC_UTE_CFI
1864                 DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
1865
1866                 /* printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
1867                  * ctrl.bRequestType, ctrl.bRequest); */
1868                 if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
1869                         if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
1870                                 retval = cfi_setup(pcd, &cfi_req);
1871                                 if (retval < 0) {
1872                                         ep0_do_stall(pcd, retval);
1873                                         pcd->ep0_pending = 0;
1874                                         return;
1875                                 }
1876
1877                                 /* if need gadget setup then call it and check the retval */
1878                                 if (pcd->cfi->need_gadget_att) {
1879                                         retval =
1880                                             cfi_gadget_setup(pcd,
1881                                                              &pcd->
1882                                                              cfi->ctrl_req);
1883                                         if (retval < 0) {
1884                                                 pcd->ep0_pending = 0;
1885                                                 return;
1886                                         }
1887                                 }
1888
1889                                 if (pcd->cfi->need_status_in_complete) {
1890                                         do_setup_in_status_phase(pcd);
1891                                 }
1892                                 return;
1893                         }
1894                 }
1895 #endif
1896
1897                 /* handle non-standard (class/vendor) requests in the gadget driver */
1898                 do_gadget_setup(pcd, &ctrl);
1899                 return;
1900         }
1901
1902         /** @todo NGS: Handle bad setup packet? */
1903
1904         /* --- Standard Request handling --- */
1905
1906         switch (ctrl.bRequest) {
1907         case UR_GET_STATUS:
1908                 do_get_status(pcd);
1909                 break;
1910
1911         case UR_CLEAR_FEATURE:
1912                 do_clear_feature(pcd);
1913                 break;
1914
1915         case UR_SET_FEATURE:
1916                 do_set_feature(pcd);
1917                 break;
1918
1919         case UR_SET_ADDRESS:
1920                 do_set_address(pcd);
1921                 break;
1922
1923         case UR_SET_INTERFACE:
1924         case UR_SET_CONFIG:
1925                 /* _pcd->request_config = 1; */      /* Configuration changed */
1926                 do_gadget_setup(pcd, &ctrl);
1927                 break;
1928
1929         case UR_SYNCH_FRAME:
1930                 do_gadget_setup(pcd, &ctrl);
1931                 break;
1932
1933         default:
1934                 /* Call the Gadget Driver's setup functions */
1935                 do_gadget_setup(pcd, &ctrl);
1936                 break;
1937         }
1938 }
1939
1940 /**
1941  * This function completes the ep0 control transfer.
1942  */
1943 static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
1944 {
1945         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
1946         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1947         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
1948             dev_if->in_ep_regs[ep->dwc_ep.num];
1949 #ifdef DEBUG_EP0
1950         dwc_otg_dev_out_ep_regs_t *out_ep_regs =
1951             dev_if->out_ep_regs[ep->dwc_ep.num];
1952 #endif
1953         deptsiz0_data_t deptsiz;
1954         dev_dma_desc_sts_t desc_sts;
1955         dwc_otg_pcd_request_t *req;
1956         int is_last = 0;
1957         dwc_otg_pcd_t *pcd = ep->pcd;
1958
1959 #ifdef DWC_UTE_CFI
1960         struct cfi_usb_ctrlrequest *ctrlreq;
1961         int retval = -DWC_E_NOT_SUPPORTED;
1962 #endif
1963
1964         if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
1965                 if (ep->dwc_ep.is_in) {
1966 #ifdef DEBUG_EP0
1967                         DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
1968 #endif
1969                         do_setup_out_status_phase(pcd);
1970                 } else {
1971 #ifdef DEBUG_EP0
1972                         DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
1973 #endif
1974
1975 #ifdef DWC_UTE_CFI
1976                         ctrlreq = &pcd->cfi->ctrl_req;
1977
1978                         if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
1979                                 if (ctrlreq->bRequest > 0xB0
1980                                     && ctrlreq->bRequest < 0xBF) {
1981
1982                                         /* Return if the PCD failed to handle the request */
1983                                         retval = pcd->cfi->ops.
1984                                                  ctrl_write_complete(pcd->cfi, pcd);
1985                                         if (retval < 0) {
1986                                                 CFI_INFO
1987                                                     ("ERROR setting a new value in the PCD(%d)\n",
1988                                                      retval);
1989                                                 ep0_do_stall(pcd, retval);
1990                                                 pcd->ep0_pending = 0;
1991                                                 return 0;
1992                                         }
1993
1994                                         /* If the gadget needs to be notified on the request */
1995                                         if (pcd->cfi->need_gadget_att == 1) {
1996                                                 /* retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); */
1997                                                 retval =
1998                                                     cfi_gadget_setup(pcd,
1999                                                                      &pcd->cfi->
2000                                                                      ctrl_req);
2001
2002                                                 /* Return from the function if the gadget failed to process
2003                                                  * the request properly - this should never happen !!!
2004                                                  */
2005                                                 if (retval < 0) {
2006                                                         CFI_INFO
2007                                                             ("ERROR setting a new value in the gadget(%d)\n",
2008                                                              retval);
2009                                                         pcd->ep0_pending = 0;
2010                                                         return 0;
2011                                                 }
2012                                         }
2013
2014                                         CFI_INFO("%s: RETVAL=%d\n", __func__,
2015                                                  retval);
2016                                         /* If we hit here then the PCD and the gadget has properly
2017                                          * handled the request - so send the ZLP IN to the host.
2018                                          */
2019                                         /* @todo: MAS - decide whether we need to start the setup
2020                                          * stage based on the need_setup value of the cfi object
2021                                          */
2022                                         do_setup_in_status_phase(pcd);
2023                                         pcd->ep0_pending = 0;
2024                                         return 1;
2025                                 }
2026                         }
2027 #endif
2028
2029                         do_setup_in_status_phase(pcd);
2030                 }
2031                 pcd->ep0_pending = 0;
2032                 return 1;
2033         }
2034
2035         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
2036                 return 0;
2037         }
2038         req = DWC_CIRCLEQ_FIRST(&ep->queue);
2039
2040         if (pcd->ep0state == EP0_OUT_STATUS_PHASE
2041             || pcd->ep0state == EP0_IN_STATUS_PHASE) {
2042                 is_last = 1;
2043         } else if (ep->dwc_ep.is_in) {
2044                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
2045                 if (core_if->dma_desc_enable != 0)
2046                         desc_sts = dev_if->in_desc_addr->status;
2047 #ifdef DEBUG_EP0
2048                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
2049                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
2050                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
2051 #endif
2052
2053                 if (((core_if->dma_desc_enable == 0)
2054                      && (deptsiz.b.xfersize == 0))
2055                     || ((core_if->dma_desc_enable != 0)
2056                         && (desc_sts.b.bytes == 0))) {
2057                         req->actual = ep->dwc_ep.xfer_count;
2058                         /* Is a Zero Len Packet needed? */
2059                         if (req->sent_zlp) {
2060 #ifdef DEBUG_EP0
2061                                 DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
2062 #endif
2063                                 req->sent_zlp = 0;
2064                         }
2065                         do_setup_out_status_phase(pcd);
2066                 }
2067         } else {
2068                 /* ep0-OUT */
2069 #ifdef DEBUG_EP0
2070                 deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
2071                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
2072                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
2073                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
2074 #endif
2075                 req->actual = ep->dwc_ep.xfer_count;
2076
2077                 /* Is a Zero Len Packet needed? */
2078                 if (req->sent_zlp) {
2079 #ifdef DEBUG_EP0
2080                         DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
2081 #endif
2082                         req->sent_zlp = 0;
2083                 }
2084                 /* For older cores do setup in status phase in Slave/BDMA modes,
2085                  * starting from 3.00 do that only in slave, and for DMA modes
2086                  * just re-enable ep 0 OUT here*/
2087                 do_setup_in_status_phase(pcd);
2088         }
2089
2090         /* Complete the request */
2091         if (is_last) {
2092                 dwc_otg_request_done(ep, req, 0);
2093                 ep->dwc_ep.start_xfer_buff = 0;
2094                 ep->dwc_ep.xfer_buff = 0;
2095                 ep->dwc_ep.xfer_len = 0;
2096                 return 1;
2097         }
2098         return 0;
2099 }
2100
2101 #ifdef DWC_UTE_CFI
2102 /**
2103  * This function calculates traverses all the CFI DMA descriptors and
2104  * and accumulates the bytes that are left to be transfered.
2105  *
2106  * @return The total bytes left to transfered, or a negative value as failure
2107  */
2108 static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t *ep)
2109 {
2110         int32_t ret = 0;
2111         int i;
2112         struct dwc_otg_dma_desc *ddesc = NULL;
2113         struct cfi_ep *cfiep;
2114
2115         /* See if the pcd_ep has its respective cfi_ep mapped */
2116         cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
2117         if (!cfiep) {
2118                 CFI_INFO("%s: Failed to find ep\n", __func__);
2119                 return -1;
2120         }
2121
2122         ddesc = ep->dwc_ep.descs;
2123
2124         for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
2125
2126 #if defined(PRINT_CFI_DMA_DESCS)
2127                 print_desc(ddesc, ep->ep.name, i);
2128 #endif
2129                 ret += ddesc->status.b.bytes;
2130                 ddesc++;
2131         }
2132
2133         if (ret)
2134                 CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
2135                          ret);
2136
2137         return ret;
2138 }
2139 #endif
2140
2141 /**
2142  * This function completes the request for the EP. If there are
2143  * additional requests for the EP in the queue they will be started.
2144  */
2145 static void complete_ep(dwc_otg_pcd_ep_t *ep)
2146 {
2147         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
2148         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
2149         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
2150             dev_if->in_ep_regs[ep->dwc_ep.num];
2151         deptsiz_data_t deptsiz;
2152         dev_dma_desc_sts_t desc_sts;
2153         dwc_otg_pcd_request_t *req = 0;
2154         dwc_otg_dev_dma_desc_t *dma_desc;
2155         uint32_t byte_count = 0;
2156         int is_last = 0;
2157         int i;
2158
2159         DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
2160                     (ep->dwc_ep.is_in ? "IN" : "OUT"));
2161
2162         /* Get any pending requests */
2163         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
2164                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
2165                 if (!req) {
2166                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
2167                         return;
2168                 }
2169         } else {
2170                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
2171                 return;
2172         }
2173
2174         DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
2175
2176         if (ep->dwc_ep.is_in) {
2177                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
2178
2179                 if (core_if->dma_enable) {
2180                         if (core_if->dma_desc_enable == 0) {
2181                                 if (deptsiz.b.xfersize == 0
2182                                     && deptsiz.b.pktcnt == 0) {
2183                                         byte_count =
2184                                             ep->dwc_ep.xfer_len -
2185                                             ep->dwc_ep.xfer_count;
2186
2187                                         ep->dwc_ep.xfer_buff += byte_count;
2188                                         ep->dwc_ep.dma_addr += byte_count;
2189                                         ep->dwc_ep.xfer_count += byte_count;
2190
2191                                         DWC_DEBUGPL(DBG_PCDV,
2192                                                     "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
2193                                                     ep->dwc_ep.num,
2194                                                     (ep->dwc_ep.is_in ? "IN" :
2195                                                      "OUT"),
2196                                                     ep->dwc_ep.xfer_len,
2197                                                     deptsiz.b.xfersize,
2198                                                     deptsiz.b.pktcnt);
2199
2200                                         if (ep->dwc_ep.xfer_len <
2201                                             ep->dwc_ep.total_len) {
2202                                                 dwc_otg_ep_start_transfer
2203                                                     (core_if, &ep->dwc_ep);
2204                                         } else if (ep->dwc_ep.sent_zlp) {
2205                                                 /*
2206                                                  * This fragment of code should initiate 0
2207                                                  * length transfer in case if it is queued
2208                                                  * a transfer with size divisible to EPs max
2209                                                  * packet size and with usb_request zero field
2210                                                  * is set, which means that after data is transfered,
2211                                                  * it is also should be transfered
2212                                                  * a 0 length packet at the end. For Slave and
2213                                                  * Buffer DMA modes in this case SW has
2214                                                  * to initiate 2 transfers one with transfer size,
2215                                                  * and the second with 0 size. For Descriptor
2216                                                  * DMA mode SW is able to initiate a transfer,
2217                                                  * which will handle all the packets including
2218                                                  * the last  0 length.
2219                                                  */
2220                                                 ep->dwc_ep.sent_zlp = 0;
2221                                                 dwc_otg_ep_start_zl_transfer
2222                                                     (core_if, &ep->dwc_ep);
2223                                         } else {
2224                                                 is_last = 1;
2225                                         }
2226                                 } else {
2227                                         if (ep->dwc_ep.type ==
2228                                             DWC_OTG_EP_TYPE_ISOC) {
2229                                                 req->actual = 0;
2230                                                 dwc_otg_request_done(ep, req,
2231                                                                      0);
2232
2233                                                 ep->dwc_ep.start_xfer_buff = 0;
2234                                                 ep->dwc_ep.xfer_buff = 0;
2235                                                 ep->dwc_ep.xfer_len = 0;
2236
2237                                                 /* If there is a request in the queue start it. */
2238                                                 start_next_request(ep);
2239                                         } else
2240                                                 DWC_WARN
2241                                                     ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
2242                                                      ep->dwc_ep.num,
2243                                                      (ep->
2244                                                       dwc_ep.is_in ? "IN" :
2245                                                       "OUT"),
2246                                                      deptsiz.b.xfersize,
2247                                                      deptsiz.b.pktcnt);
2248                                 }
2249                         } else {
2250                                 dma_desc = ep->dwc_ep.desc_addr;
2251                                 byte_count = 0;
2252                                 ep->dwc_ep.sent_zlp = 0;
2253
2254 #ifdef DWC_UTE_CFI
2255                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
2256                                          ep->dwc_ep.buff_mode);
2257                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
2258                                         int residue;
2259
2260                                         residue = cfi_calc_desc_residue(ep);
2261                                         if (residue < 0)
2262                                                 return;
2263
2264                                         byte_count = residue;
2265                                 } else {
2266 #endif
2267                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
2268                                              ++i) {
2269                                                 desc_sts = dma_desc->status;
2270                                                 byte_count += desc_sts.b.bytes;
2271                                                 dma_desc++;
2272                                         }
2273 #ifdef DWC_UTE_CFI
2274                                 }
2275 #endif
2276                                 if (byte_count == 0) {
2277                                         ep->dwc_ep.xfer_count =
2278                                             ep->dwc_ep.total_len;
2279                                         is_last = 1;
2280                                 } else {
2281                                         DWC_WARN("Incomplete transfer\n");
2282                                 }
2283                         }
2284                 } else {
2285                         if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
2286                                 DWC_DEBUGPL(DBG_PCDV,
2287                                             "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
2288                                             ep->dwc_ep.num,
2289                                             ep->dwc_ep.is_in ? "IN" : "OUT",
2290                                             ep->dwc_ep.xfer_len,
2291                                             deptsiz.b.xfersize,
2292                                             deptsiz.b.pktcnt);
2293
2294                                 /*      Check if the whole transfer was completed,
2295                                  *      if no, setup transfer for next portion of data
2296                                  */
2297                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
2298                                         dwc_otg_ep_start_transfer(core_if,
2299                                                                   &ep->dwc_ep);
2300                                 } else if (ep->dwc_ep.sent_zlp) {
2301                                         /*
2302                                          * This fragment of code should initiate 0
2303                                          * length trasfer in case if it is queued
2304                                          * a trasfer with size divisible to EPs max
2305                                          * packet size and with usb_request zero field
2306                                          * is set, which means that after data is transfered,
2307                                          * it is also should be transfered
2308                                          * a 0 length packet at the end. For Slave and
2309                                          * Buffer DMA modes in this case SW has
2310                                          * to initiate 2 transfers one with transfer size,
2311                                          * and the second with 0 size. For Desriptor
2312                                          * DMA mode SW is able to initiate a transfer,
2313                                          * which will handle all the packets including
2314                                          * the last  0 legth.
2315                                          */
2316                                         ep->dwc_ep.sent_zlp = 0;
2317                                         dwc_otg_ep_start_zl_transfer(core_if,
2318                                                                      &ep->dwc_ep);
2319                                 } else {
2320                                         is_last = 1;
2321                                 }
2322                         } else {
2323                                 DWC_WARN
2324                                     ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
2325                                      ep->dwc_ep.num,
2326                                      (ep->dwc_ep.is_in ? "IN" : "OUT"),
2327                                      deptsiz.b.xfersize, deptsiz.b.pktcnt);
2328                         }
2329                 }
2330         } else {
2331                 dwc_otg_dev_out_ep_regs_t *out_ep_regs =
2332                     dev_if->out_ep_regs[ep->dwc_ep.num];
2333                 desc_sts.d32 = 0;
2334                 if (core_if->dma_enable) {
2335                         if (core_if->dma_desc_enable) {
2336                                 dma_desc = ep->dwc_ep.desc_addr;
2337                                 byte_count = 0;
2338                                 ep->dwc_ep.sent_zlp = 0;
2339
2340 #ifdef DWC_UTE_CFI
2341                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
2342                                          ep->dwc_ep.buff_mode);
2343                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
2344                                         int residue;
2345                                         residue = cfi_calc_desc_residue(ep);
2346                                         if (residue < 0)
2347                                                 return;
2348                                         byte_count = residue;
2349                                 } else {
2350 #endif
2351
2352                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
2353                                              ++i) {
2354                                                 desc_sts = dma_desc->status;
2355                                                 byte_count += desc_sts.b.bytes;
2356                                                 dma_desc++;
2357                                         }
2358
2359 #ifdef DWC_UTE_CFI
2360                                 }
2361 #endif
2362                                 /* Checking for interrupt Out transfers with not
2363                                  * dword aligned mps sizes
2364                                  */
2365                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
2366                                     (ep->dwc_ep.maxpacket % 4)) {
2367                                         ep->dwc_ep.xfer_count =
2368                                             ep->dwc_ep.total_len - byte_count;
2369                                         if ((ep->dwc_ep.xfer_len %
2370                                              ep->dwc_ep.maxpacket)
2371                                             && (ep->dwc_ep.xfer_len /
2372                                                 ep->dwc_ep.maxpacket <
2373                                                 MAX_DMA_DESC_CNT))
2374                                                 ep->dwc_ep.xfer_len -=
2375                                                     (ep->dwc_ep.desc_cnt -
2376                                                      1)*ep->dwc_ep.maxpacket +
2377                                                     ep->dwc_ep.xfer_len %
2378                                                     ep->dwc_ep.maxpacket;
2379                                         else
2380                                                 ep->dwc_ep.xfer_len -=
2381                                                     ep->dwc_ep.desc_cnt *
2382                                                     ep->dwc_ep.maxpacket;
2383                                         if (ep->dwc_ep.xfer_len > 0) {
2384                                                 dwc_otg_ep_start_transfer
2385                                                     (core_if, &ep->dwc_ep);
2386                                         } else {
2387                                                 is_last = 1;
2388                                         }
2389                                 } else {
2390                                         ep->dwc_ep.xfer_count =
2391                                             ep->dwc_ep.total_len - byte_count +
2392                                             ((4 -
2393                                               (ep->dwc_ep.
2394                                                total_len & 0x3)) & 0x3);
2395                                         is_last = 1;
2396                                 }
2397                         } else {
2398                                 deptsiz.d32 = 0;
2399                                 deptsiz.d32 =
2400                                     DWC_READ_REG32(&out_ep_regs->doeptsiz);
2401
2402                                 byte_count = (ep->dwc_ep.xfer_len -
2403                                               ep->dwc_ep.xfer_count -
2404                                               deptsiz.b.xfersize);
2405                                 ep->dwc_ep.xfer_buff += byte_count;
2406                                 ep->dwc_ep.dma_addr += byte_count;
2407                                 ep->dwc_ep.xfer_count += byte_count;
2408
2409                                 /*      Check if the whole transfer was completed,
2410                                  *      if no, setup transfer for next portion of data
2411                                  */
2412                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
2413                                         dwc_otg_ep_start_transfer(core_if,
2414                                                                   &ep->dwc_ep);
2415                                 } else if (ep->dwc_ep.sent_zlp) {
2416                                         /*
2417                                          * This fragment of code should initiate 0
2418                                          * length trasfer in case if it is queued
2419                                          * a trasfer with size divisible to EPs max
2420                                          * packet size and with usb_request zero field
2421                                          * is set, which means that after data is transfered,
2422                                          * it is also should be transfered
2423                                          * a 0 length packet at the end. For Slave and
2424                                          * Buffer DMA modes in this case SW has
2425                                          * to initiate 2 transfers one with transfer size,
2426                                          * and the second with 0 size. For Desriptor
2427                                          * DMA mode SW is able to initiate a transfer,
2428                                          * which will handle all the packets including
2429                                          * the last  0 legth.
2430                                          */
2431                                         ep->dwc_ep.sent_zlp = 0;
2432                                         dwc_otg_ep_start_zl_transfer(core_if,
2433                                                                      &ep->dwc_ep);
2434                                 } else {
2435                                         is_last = 1;
2436                                 }
2437                         }
2438                 } else {
2439                         /*      Check if the whole transfer was completed,
2440                          *      if no, setup transfer for next portion of data
2441                          */
2442                         if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
2443                                 dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
2444                         } else if (ep->dwc_ep.sent_zlp) {
2445                                 /*
2446                                  * This fragment of code should initiate 0
2447                                  * length transfer in case if it is queued
2448                                  * a transfer with size divisible to EPs max
2449                                  * packet size and with usb_request zero field
2450                                  * is set, which means that after data is transfered,
2451                                  * it is also should be transfered
2452                                  * a 0 length packet at the end. For Slave and
2453                                  * Buffer DMA modes in this case SW has
2454                                  * to initiate 2 transfers one with transfer size,
2455                                  * and the second with 0 size. For Descriptor
2456                                  * DMA mode SW is able to initiate a transfer,
2457                                  * which will handle all the packets including
2458                                  * the last  0 length.
2459                                  */
2460                                 ep->dwc_ep.sent_zlp = 0;
2461                                 dwc_otg_ep_start_zl_transfer(core_if,
2462                                                              &ep->dwc_ep);
2463                         } else {
2464                                 is_last = 1;
2465                         }
2466                 }
2467
2468                 DWC_DEBUGPL(DBG_PCDV,
2469                             "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
2470                             &out_ep_regs->doeptsiz, ep->dwc_ep.num,
2471                             ep->dwc_ep.is_in ? "IN" : "OUT",
2472                             ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
2473                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
2474         }
2475
2476         /* Complete the request */
2477         if (is_last) {
2478 #ifdef DWC_UTE_CFI
2479                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
2480                         req->actual = ep->dwc_ep.cfi_req_len - byte_count;
2481                 } else {
2482 #endif
2483                         req->actual = ep->dwc_ep.xfer_count;
2484 #ifdef DWC_UTE_CFI
2485                 }
2486 #endif
2487                 if (req->dw_align_buf) {
2488                         if (!ep->dwc_ep.is_in) {
2489                                 dwc_memcpy(req->buf, req->dw_align_buf,
2490                                            req->length);
2491                         }
2492                         DWC_DEV_DMA_FREE(req->length, req->dw_align_buf,
2493                                          req->dw_align_buf_dma);
2494                 }
2495
2496                 dwc_otg_request_done(ep, req, 0);
2497
2498                 ep->dwc_ep.start_xfer_buff = 0;
2499                 ep->dwc_ep.xfer_buff = 0;
2500                 ep->dwc_ep.xfer_len = 0;
2501
2502                 /* If there is a request in the queue start it. */
2503                 start_next_request(ep);
2504         }
2505 }
2506
2507 #ifdef DWC_EN_ISOC
2508
2509 /**
2510  * This function BNA interrupt for Isochronous EPs
2511  *
2512  */
2513 static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
2514 {
2515         dwc_ep_t *dwc_ep = &ep->dwc_ep;
2516         volatile uint32_t *addr;
2517         depctl_data_t depctl = {
2518         .d32 = 0};
2519         dwc_otg_pcd_t *pcd = ep->pcd;
2520         dwc_otg_dev_dma_desc_t *dma_desc;
2521         int i;
2522
2523         dma_desc =
2524             dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
2525
2526         if (dwc_ep->is_in) {
2527                 dev_dma_desc_sts_t sts = {
2528                 .d32 = 0};
2529                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
2530                         sts.d32 = dma_desc->status.d32;
2531                         sts.b_iso_in.bs = BS_HOST_READY;
2532                         dma_desc->status.d32 = sts.d32;
2533                 }
2534         } else {
2535                 dev_dma_desc_sts_t sts = {
2536                 .d32 = 0};
2537                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
2538                         sts.d32 = dma_desc->status.d32;
2539                         sts.b_iso_out.bs = BS_HOST_READY;
2540                         dma_desc->status.d32 = sts.d32;
2541                 }
2542         }
2543
2544         if (dwc_ep->is_in == 0) {
2545                 addr =
2546                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
2547                                                            num]->doepctl;
2548         } else {
2549                 addr =
2550                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
2551         }
2552         depctl.b.epena = 1;
2553         DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
2554 }
2555
2556 /**
2557  * This function sets latest iso packet information(non-PTI mode)
2558  *
2559  * @param core_if Programming view of DWC_otg controller.
2560  * @param ep The EP to start the transfer on.
2561  *
2562  */
2563 void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
2564 {
2565         deptsiz_data_t deptsiz = {
2566         .d32 = 0};
2567         dma_addr_t dma_addr;
2568         uint32_t offset;
2569
2570         if (ep->proc_buf_num)
2571                 dma_addr = ep->dma_addr1;
2572         else
2573                 dma_addr = ep->dma_addr0;
2574
2575         if (ep->is_in) {
2576                 deptsiz.d32 =
2577                     DWC_READ_REG32(&core_if->dev_if->
2578                                    in_ep_regs[ep->num]->dieptsiz);
2579                 offset = ep->data_per_frame;
2580         } else {
2581                 deptsiz.d32 =
2582                     DWC_READ_REG32(&core_if->dev_if->
2583                                    out_ep_regs[ep->num]->doeptsiz);
2584                 offset =
2585                     ep->data_per_frame +
2586                     (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
2587         }
2588
2589         if (!deptsiz.b.xfersize) {
2590                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
2591                 ep->pkt_info[ep->cur_pkt].offset =
2592                     ep->cur_pkt_dma_addr - dma_addr;
2593                 ep->pkt_info[ep->cur_pkt].status = 0;
2594         } else {
2595                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
2596                 ep->pkt_info[ep->cur_pkt].offset =
2597                     ep->cur_pkt_dma_addr - dma_addr;
2598                 ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
2599         }
2600         ep->cur_pkt_addr += offset;
2601         ep->cur_pkt_dma_addr += offset;
2602         ep->cur_pkt++;
2603 }
2604
2605 /**
2606  * This function sets latest iso packet information(DDMA mode)
2607  *
2608  * @param core_if Programming view of DWC_otg controller.
2609  * @param dwc_ep The EP to start the transfer on.
2610  *
2611  */
2612 static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if,
2613                                    dwc_ep_t *dwc_ep) {
2614         dwc_otg_dev_dma_desc_t *dma_desc;
2615         dev_dma_desc_sts_t sts = {
2616         .d32 = 0};
2617         iso_pkt_info_t *iso_packet;
2618         uint32_t data_per_desc;
2619         uint32_t offset;
2620         int i, j;
2621
2622         iso_packet = dwc_ep->pkt_info;
2623
2624         /** Reinit closed DMA Descriptors*/
2625         /** ISO OUT EP */
2626         if (dwc_ep->is_in == 0) {
2627                 dma_desc =
2628                     dwc_ep->iso_desc_addr +
2629                     dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
2630                 offset = 0;
2631
2632                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
2633                      i += dwc_ep->pkt_per_frm) {
2634                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
2635                                 data_per_desc =
2636                                     ((j + 1)*dwc_ep->maxpacket >
2637                                      dwc_ep->
2638                                      data_per_frame) ? dwc_ep->data_per_frame -
2639                                     j*dwc_ep->maxpacket : dwc_ep->maxpacket;
2640                                 data_per_desc +=
2641                                     (data_per_desc % 4) ? (4 -
2642                                                            data_per_desc %
2643                                                            4) : 0;
2644
2645                                 sts.d32 = dma_desc->status.d32;
2646
2647                                 /* Write status in iso_packet_decsriptor  */
2648                                 iso_packet->status =
2649                                     sts.b_iso_out.rxsts +
2650                                     (sts.b_iso_out.bs ^ BS_DMA_DONE);
2651                                 if (iso_packet->status) {
2652                                         iso_packet->status = -DWC_E_NO_DATA;
2653                                 }
2654
2655                                 /* Received data length */
2656                                 if (!sts.b_iso_out.rxbytes) {
2657                                         iso_packet->length =
2658                                             data_per_desc -
2659                                             sts.b_iso_out.rxbytes;
2660                                 } else {
2661                                         iso_packet->length =
2662                                             data_per_desc -
2663                                             sts.b_iso_out.rxbytes + (4 -
2664                                                                      dwc_ep->data_per_frame
2665                                                                      % 4);
2666                                 }
2667
2668                                 iso_packet->offset = offset;
2669
2670                                 offset += data_per_desc;
2671                                 dma_desc++;
2672                                 iso_packet++;
2673                         }
2674                 }
2675
2676                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
2677                         data_per_desc =
2678                             ((j + 1)*dwc_ep->maxpacket >
2679                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
2680                             j*dwc_ep->maxpacket : dwc_ep->maxpacket;
2681                         data_per_desc +=
2682                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
2683
2684                         sts.d32 = dma_desc->status.d32;
2685
2686                         /* Write status in iso_packet_decsriptor  */
2687                         iso_packet->status =
2688                             sts.b_iso_out.rxsts +
2689                             (sts.b_iso_out.bs ^ BS_DMA_DONE);
2690                         if (iso_packet->status) {
2691                                 iso_packet->status = -DWC_E_NO_DATA;
2692                         }
2693
2694                         /* Received data length */
2695                         iso_packet->length =
2696                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
2697
2698                         iso_packet->offset = offset;
2699
2700                         offset += data_per_desc;
2701                         iso_packet++;
2702                         dma_desc++;
2703                 }
2704
2705                 sts.d32 = dma_desc->status.d32;
2706
2707                 /* Write status in iso_packet_decsriptor  */
2708                 iso_packet->status =
2709                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
2710                 if (iso_packet->status) {
2711                         iso_packet->status = -DWC_E_NO_DATA;
2712                 }
2713                 /* Received data length */
2714                 if (!sts.b_iso_out.rxbytes) {
2715                         iso_packet->length =
2716                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
2717                 } else {
2718                         iso_packet->length =
2719                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
2720                             (4 - dwc_ep->data_per_frame % 4);
2721                 }
2722
2723                 iso_packet->offset = offset;
2724         } else {
2725 /** ISO IN EP */
2726
2727                 dma_desc =
2728                     dwc_ep->iso_desc_addr +
2729                     dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
2730
2731                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
2732                         sts.d32 = dma_desc->status.d32;
2733
2734                         /* Write status in iso packet descriptor */
2735                         iso_packet->status =
2736                             sts.b_iso_in.txsts +
2737                             (sts.b_iso_in.bs ^ BS_DMA_DONE);
2738                         if (iso_packet->status != 0) {
2739                                 iso_packet->status = -DWC_E_NO_DATA;
2740
2741                         }
2742                         /* Bytes has been transfered */
2743                         iso_packet->length =
2744                             dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
2745
2746                         dma_desc++;
2747                         iso_packet++;
2748                 }
2749
2750                 sts.d32 = dma_desc->status.d32;
2751                 while (sts.b_iso_in.bs == BS_DMA_BUSY) {
2752                         sts.d32 = dma_desc->status.d32;
2753                 }
2754
2755                 /* Write status in iso packet descriptor ??? do be done with ERROR codes */
2756                 iso_packet->status =
2757                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
2758                 if (iso_packet->status != 0) {
2759                         iso_packet->status = -DWC_E_NO_DATA;
2760                 }
2761
2762                 /* Bytes has been transfered */
2763                 iso_packet->length =
2764                     dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
2765         }
2766 }
2767
2768 /**
2769  * This function reinitialize DMA Descriptors for Isochronous transfer
2770  *
2771  * @param core_if Programming view of DWC_otg controller.
2772  * @param dwc_ep The EP to start the transfer on.
2773  *
2774  */
2775 static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
2776 {
2777         int i, j;
2778         dwc_otg_dev_dma_desc_t *dma_desc;
2779         dma_addr_t dma_ad;
2780         volatile uint32_t *addr;
2781         dev_dma_desc_sts_t sts = {
2782         .d32 = 0};
2783         uint32_t data_per_desc;
2784
2785         if (dwc_ep->is_in == 0) {
2786                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
2787         } else {
2788                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
2789         }
2790
2791         if (dwc_ep->proc_buf_num == 0) {
2792                 /** Buffer 0 descriptors setup */
2793                 dma_ad = dwc_ep->dma_addr0;
2794         } else {
2795                 /** Buffer 1 descriptors setup */
2796                 dma_ad = dwc_ep->dma_addr1;
2797         }
2798
2799         /** Reinit closed DMA Descriptors*/
2800         /** ISO OUT EP */
2801         if (dwc_ep->is_in == 0) {
2802                 dma_desc =
2803                     dwc_ep->iso_desc_addr +
2804                     dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
2805
2806                 sts.b_iso_out.bs = BS_HOST_READY;
2807                 sts.b_iso_out.rxsts = 0;
2808                 sts.b_iso_out.l = 0;
2809                 sts.b_iso_out.sp = 0;
2810                 sts.b_iso_out.ioc = 0;
2811                 sts.b_iso_out.pid = 0;
2812                 sts.b_iso_out.framenum = 0;
2813
2814                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
2815                      i += dwc_ep->pkt_per_frm) {
2816                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
2817                                 data_per_desc =
2818                                     ((j + 1)*dwc_ep->maxpacket >
2819                                      dwc_ep->
2820                                      data_per_frame) ? dwc_ep->data_per_frame -
2821                                     j*dwc_ep->maxpacket : dwc_ep->maxpacket;
2822                                 data_per_desc +=
2823                                     (data_per_desc % 4) ? (4 -
2824                                                            data_per_desc %
2825                                                            4) : 0;
2826                                 sts.b_iso_out.rxbytes = data_per_desc;
2827                                 dma_desc->buf = dma_ad;
2828                                 dma_desc->status.d32 = sts.d32;
2829
2830                                 dma_ad += data_per_desc;
2831                                 dma_desc++;
2832                         }
2833                 }
2834
2835                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
2836
2837                         data_per_desc =
2838                             ((j + 1)*dwc_ep->maxpacket >
2839                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
2840                             j*dwc_ep->maxpacket : dwc_ep->maxpacket;
2841                         data_per_desc +=
2842                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
2843                         sts.b_iso_out.rxbytes = data_per_desc;
2844
2845                         dma_desc->buf = dma_ad;
2846                         dma_desc->status.d32 = sts.d32;
2847
2848                         dma_desc++;
2849                         dma_ad += data_per_desc;
2850                 }
2851
2852                 sts.b_iso_out.ioc = 1;
2853                 sts.b_iso_out.l = dwc_ep->proc_buf_num;
2854
2855                 data_per_desc =
2856                     ((j + 1)*dwc_ep->maxpacket >
2857                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
2858                     j*dwc_ep->maxpacket : dwc_ep->maxpacket;
2859                 data_per_desc +=
2860                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
2861                 sts.b_iso_out.rxbytes = data_per_desc;
2862
2863                 dma_desc->buf = dma_ad;
2864                 dma_desc->status.d32 = sts.d32;
2865         } else {
2866 /** ISO IN EP */
2867
2868                 dma_desc =
2869                     dwc_ep->iso_desc_addr +
2870                     dwc_ep->desc_cnt*dwc_ep->proc_buf_num;
2871
2872                 sts.b_iso_in.bs = BS_HOST_READY;
2873                 sts.b_iso_in.txsts = 0;
2874                 sts.b_iso_in.sp = 0;
2875                 sts.b_iso_in.ioc = 0;
2876                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
2877                 sts.b_iso_in.framenum = dwc_ep->next_frame;
2878                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
2879                 sts.b_iso_in.l = 0;
2880
2881                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
2882                         dma_desc->buf = dma_ad;
2883                         dma_desc->status.d32 = sts.d32;
2884
2885                         sts.b_iso_in.framenum += dwc_ep->bInterval;
2886                         dma_ad += dwc_ep->data_per_frame;
2887                         dma_desc++;
2888                 }
2889
2890                 sts.b_iso_in.ioc = 1;
2891                 sts.b_iso_in.l = dwc_ep->proc_buf_num;
2892
2893                 dma_desc->buf = dma_ad;
2894                 dma_desc->status.d32 = sts.d32;
2895
2896                 dwc_ep->next_frame =
2897                     sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
2898         }
2899         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
2900 }
2901
2902 /**
2903  * This function is to handle Iso EP transfer complete interrupt
2904  * in case Iso out packet was dropped
2905  *
2906  * @param core_if Programming view of DWC_otg controller.
2907  * @param dwc_ep The EP for wihich transfer complete was asserted
2908  *
2909  */
2910 static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if,
2911                                            dwc_ep_t *dwc_ep) {
2912         uint32_t dma_addr;
2913         uint32_t drp_pkt;
2914         uint32_t drp_pkt_cnt;
2915         deptsiz_data_t deptsiz = {
2916         .d32 = 0};
2917         depctl_data_t depctl = {
2918         .d32 = 0};
2919         int i;
2920
2921         deptsiz.d32 =
2922             DWC_READ_REG32(&core_if->dev_if->
2923                            out_ep_regs[dwc_ep->num]->doeptsiz);
2924
2925         drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
2926         drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
2927
2928         /* Setting dropped packets status */
2929         for (i = 0; i < drp_pkt_cnt; ++i) {
2930                 dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
2931                 drp_pkt++;
2932                 deptsiz.b.pktcnt--;
2933         }
2934
2935         if (deptsiz.b.pktcnt > 0) {
2936                 deptsiz.b.xfersize =
2937                     dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
2938                                         deptsiz.b.pktcnt)*dwc_ep->maxpacket;
2939         } else {
2940                 deptsiz.b.xfersize = 0;
2941                 deptsiz.b.pktcnt = 0;
2942         }
2943
2944         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
2945                         deptsiz.d32);
2946
2947         if (deptsiz.b.pktcnt > 0) {
2948                 if (dwc_ep->proc_buf_num) {
2949                         dma_addr =
2950                             dwc_ep->dma_addr1 + dwc_ep->xfer_len -
2951                             deptsiz.b.xfersize;
2952                 } else {
2953                         dma_addr =
2954                             dwc_ep->dma_addr0 + dwc_ep->xfer_len -
2955                             deptsiz.b.xfersize;;
2956                 }
2957
2958                 DWC_WRITE_REG32(&core_if->dev_if->
2959                                 out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
2960
2961                 /** Re-enable endpoint, clear nak  */
2962                 depctl.d32 = 0;
2963                 depctl.b.epena = 1;
2964                 depctl.b.cnak = 1;
2965
2966                 DWC_MODIFY_REG32(&core_if->dev_if->
2967                                  out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
2968                                  depctl.d32);
2969                 return 0;
2970         } else {
2971                 return 1;
2972         }
2973 }
2974
2975 /**
2976  * This function sets iso packets information(PTI mode)
2977  *
2978  * @param core_if Programming view of DWC_otg controller.
2979  * @param ep The EP to start the transfer on.
2980  *
2981  */
2982 static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
2983 {
2984         int i, j;
2985         dma_addr_t dma_ad;
2986         iso_pkt_info_t *packet_info = ep->pkt_info;
2987         uint32_t offset;
2988         uint32_t frame_data;
2989         deptsiz_data_t deptsiz;
2990
2991         if (ep->proc_buf_num == 0) {
2992                 /** Buffer 0 descriptors setup */
2993                 dma_ad = ep->dma_addr0;
2994         } else {
2995                 /** Buffer 1 descriptors setup */
2996                 dma_ad = ep->dma_addr1;
2997         }
2998
2999         if (ep->is_in) {
3000                 deptsiz.d32 =
3001                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3002                                    dieptsiz);
3003         } else {
3004                 deptsiz.d32 =
3005                     DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
3006                                    doeptsiz);
3007         }
3008
3009         if (!deptsiz.b.xfersize) {
3010                 offset = 0;
3011                 for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
3012                         frame_data = ep->data_per_frame;
3013                         for (j = 0; j < ep->pkt_per_frm; ++j) {
3014
3015                                 /* Packet status - is not set as initially
3016                                  * it is set to 0 and if packet was sent
3017                                  successfully, status field will remain 0*/
3018
3019                                 /* Bytes has been transfered */
3020                                 packet_info->length =
3021                                     (ep->maxpacket <
3022                                      frame_data) ? ep->maxpacket : frame_data;
3023
3024                                 /* Received packet offset */
3025                                 packet_info->offset = offset;
3026                                 offset += packet_info->length;
3027                                 frame_data -= packet_info->length;
3028
3029                                 packet_info++;
3030                         }
3031                 }
3032                 return 1;
3033         } else {
3034                 /* This is a workaround for in case of Transfer Complete with
3035                  * PktDrpSts interrupts merging - in this case Transfer complete
3036                  * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
3037                  * set and with DOEPTSIZ register non zero. Investigations showed,
3038                  * that this happens when Out packet is dropped, but because of
3039                  * interrupts merging during first interrupt handling PktDrpSts
3040                  * bit is cleared and for next merged interrupts it is not reset.
3041                  * In this case SW hadles the interrupt as if PktDrpSts bit is set.
3042                  */
3043                 if (ep->is_in) {
3044                         return 1;
3045                 } else {
3046                         return handle_iso_out_pkt_dropped(core_if, ep);
3047                 }
3048         }
3049 }
3050
3051 /**
3052  * This function is to handle Iso EP transfer complete interrupt
3053  *
3054  * @param pcd The PCD
3055  * @param ep The EP for which transfer complete was asserted
3056  *
3057  */
3058 static void complete_iso_ep(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
3059 {
3060         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
3061         dwc_ep_t *dwc_ep = &ep->dwc_ep;
3062         uint8_t is_last = 0;
3063
3064         if (ep->dwc_ep.next_frame == 0xffffffff) {
3065                 DWC_WARN("Next frame is not set!\n");
3066                 return;
3067         }
3068
3069         if (core_if->dma_enable) {
3070                 if (core_if->dma_desc_enable) {
3071                         set_ddma_iso_pkts_info(core_if, dwc_ep);
3072                         reinit_ddma_iso_xfer(core_if, dwc_ep);
3073                         is_last = 1;
3074                 } else {
3075                         if (core_if->pti_enh_enable) {
3076                                 if (set_iso_pkts_info(core_if, dwc_ep)) {
3077                                         dwc_ep->proc_buf_num =
3078                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
3079                                         dwc_otg_iso_ep_start_buf_transfer
3080                                             (core_if, dwc_ep);
3081                                         is_last = 1;
3082                                 }
3083                         } else {
3084                                 set_current_pkt_info(core_if, dwc_ep);
3085                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
3086                                         is_last = 1;
3087                                         dwc_ep->cur_pkt = 0;
3088                                         dwc_ep->proc_buf_num =
3089                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
3090                                         if (dwc_ep->proc_buf_num) {
3091                                                 dwc_ep->cur_pkt_addr =
3092                                                     dwc_ep->xfer_buff1;
3093                                                 dwc_ep->cur_pkt_dma_addr =
3094                                                     dwc_ep->dma_addr1;
3095                                         } else {
3096                                                 dwc_ep->cur_pkt_addr =
3097                                                     dwc_ep->xfer_buff0;
3098                                                 dwc_ep->cur_pkt_dma_addr =
3099                                                     dwc_ep->dma_addr0;
3100                                         }
3101
3102                                 }
3103                                 dwc_otg_iso_ep_start_frm_transfer(core_if,
3104                                                                   dwc_ep);
3105                         }
3106                 }
3107         } else {
3108                 set_current_pkt_info(core_if, dwc_ep);
3109                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
3110                         is_last = 1;
3111                         dwc_ep->cur_pkt = 0;
3112                         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
3113                         if (dwc_ep->proc_buf_num) {
3114                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
3115                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
3116                         } else {
3117                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
3118                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
3119                         }
3120
3121                 }
3122                 dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
3123         }
3124         if (is_last)
3125                 dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
3126 }
3127 #endif /* DWC_EN_ISOC */
3128
3129 /**
3130  * This function handle BNA interrupt for Non Isochronous EPs
3131  *
3132  */
3133 static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t *ep)
3134 {
3135         dwc_ep_t *dwc_ep = &ep->dwc_ep;
3136         volatile uint32_t *addr;
3137         depctl_data_t depctl = {
3138         .d32 = 0};
3139         dwc_otg_pcd_t *pcd = ep->pcd;
3140         dwc_otg_dev_dma_desc_t *dma_desc;
3141         dev_dma_desc_sts_t sts = {
3142         .d32 = 0};
3143         dwc_otg_core_if_t *core_if = ep->pcd->core_if;
3144         int i, start;
3145
3146         if (!dwc_ep->desc_cnt)
3147                 DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
3148                          (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
3149
3150         if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
3151             && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
3152                 uint32_t doepdma;
3153                 dwc_otg_dev_out_ep_regs_t *out_regs =
3154                     core_if->dev_if->out_ep_regs[dwc_ep->num];
3155                 doepdma = DWC_READ_REG32(&(out_regs->doepdma));
3156                 start =
3157                     (doepdma -
3158                      dwc_ep->dma_desc_addr) / sizeof(dwc_otg_dev_dma_desc_t);
3159                 dma_desc = &(dwc_ep->desc_addr[start]);
3160         } else {
3161                 start = 0;
3162                 dma_desc = dwc_ep->desc_addr;
3163         }
3164
3165         for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
3166                 sts.d32 = dma_desc->status.d32;
3167                 sts.b.bs = BS_HOST_READY;
3168                 dma_desc->status.d32 = sts.d32;
3169         }
3170
3171         if (dwc_ep->is_in == 0) {
3172                 addr =
3173                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
3174                     doepctl;
3175         } else {
3176                 addr =
3177                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
3178         }
3179         depctl.b.epena = 1;
3180         depctl.b.cnak = 1;
3181         DWC_MODIFY_REG32(addr, 0, depctl.d32);
3182 }
3183
3184 /**
3185  * This function handles EP0 Control transfers.
3186  *
3187  * The state of the control transfers are tracked in
3188  * <code>ep0state</code>.
3189  */
3190 static void handle_ep0(dwc_otg_pcd_t *pcd)
3191 {
3192         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
3193         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
3194         dev_dma_desc_sts_t desc_sts;
3195         deptsiz0_data_t deptsiz;
3196         uint32_t byte_count;
3197
3198 #ifdef DEBUG_EP0
3199         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
3200         print_ep0_state(pcd);
3201 #endif
3202
3203         switch (pcd->ep0state) {
3204         case EP0_DISCONNECT:
3205                 break;
3206
3207         case EP0_IDLE:
3208                 pcd->request_config = 0;
3209
3210                 pcd_setup(pcd);
3211                 break;
3212
3213         case EP0_IN_DATA_PHASE:
3214 #ifdef DEBUG_EP0
3215                 DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
3216                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
3217                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
3218 #endif
3219
3220                 if (core_if->dma_enable != 0) {
3221                         /*
3222                          * For EP0 we can only program 1 packet at a time so we
3223                          * need to do the make calculations after each complete.
3224                          * Call write_packet to make the calculations, as in
3225                          * slave mode, and use those values to determine if we
3226                          * can complete.
3227                          */
3228                         if (core_if->dma_desc_enable == 0) {
3229                                 deptsiz.d32 =
3230                                     DWC_READ_REG32(&core_if->
3231                                                    dev_if->in_ep_regs[0]->
3232                                                    dieptsiz);
3233                                 byte_count =
3234                                     ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
3235                         } else {
3236                                 desc_sts =
3237                                     core_if->dev_if->in_desc_addr->status;
3238                                 byte_count =
3239                                     ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
3240                         }
3241                         ep0->dwc_ep.xfer_count += byte_count;
3242                         ep0->dwc_ep.xfer_buff += byte_count;
3243                         ep0->dwc_ep.dma_addr += byte_count;
3244                 }
3245                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
3246                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
3247                                                       &ep0->dwc_ep);
3248                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
3249                 } else if (ep0->dwc_ep.sent_zlp) {
3250                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
3251                                                       &ep0->dwc_ep);
3252                         ep0->dwc_ep.sent_zlp = 0;
3253                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
3254                 } else {
3255                         ep0_complete_request(ep0);
3256                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
3257                 }
3258                 break;
3259         case EP0_OUT_DATA_PHASE:
3260 #ifdef DEBUG_EP0
3261                 DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
3262                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
3263                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
3264 #endif
3265                 if (core_if->dma_enable != 0) {
3266                         if (core_if->dma_desc_enable == 0) {
3267                                 deptsiz.d32 =
3268                                     DWC_READ_REG32(&core_if->
3269                                                    dev_if->out_ep_regs[0]->
3270                                                    doeptsiz);
3271                                 byte_count =
3272                                     ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
3273                         } else {
3274                                 desc_sts =
3275                                     core_if->dev_if->out_desc_addr->status;
3276                                 byte_count =
3277                                     ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
3278                         }
3279                         ep0->dwc_ep.xfer_count += byte_count;
3280                         ep0->dwc_ep.xfer_buff += byte_count;
3281                         ep0->dwc_ep.dma_addr += byte_count;
3282                 }
3283                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
3284                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
3285                                                       &ep0->dwc_ep);
3286                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
3287                 } else if (ep0->dwc_ep.sent_zlp) {
3288                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
3289                                                       &ep0->dwc_ep);
3290                         ep0->dwc_ep.sent_zlp = 0;
3291                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
3292                 } else {
3293                         ep0_complete_request(ep0);
3294                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
3295                 }
3296                 break;
3297
3298         case EP0_IN_STATUS_PHASE:
3299         case EP0_OUT_STATUS_PHASE:
3300                 DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
3301                 ep0_complete_request(ep0);
3302                 pcd->ep0state = EP0_IDLE;
3303                 ep0->stopped = 1;
3304                 ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
3305
3306                 /* Prepare for more SETUP Packets */
3307                 if (core_if->dma_enable) {
3308                         ep0_out_start(core_if, pcd);
3309                 }
3310                 break;
3311
3312         case EP0_STALL:
3313                 DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
3314                 break;
3315         }
3316 #ifdef DEBUG_EP0
3317         print_ep0_state(pcd);
3318 #endif
3319 }
3320
3321 /**
3322  * Restart transfer
3323  */
3324 static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
3325 {
3326         dwc_otg_core_if_t *core_if;
3327         dwc_otg_dev_if_t *dev_if;
3328         deptsiz_data_t dieptsiz = {
3329         .d32 = 0};
3330         dwc_otg_pcd_ep_t *ep;
3331
3332         ep = get_in_ep(pcd, epnum);
3333
3334 #ifdef DWC_EN_ISOC
3335         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
3336                 return;
3337         }
3338 #endif /* DWC_EN_ISOC  */
3339
3340         core_if = GET_CORE_IF(pcd);
3341         dev_if = core_if->dev_if;
3342
3343         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
3344
3345         DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
3346                     " stopped=%d\n", ep->dwc_ep.xfer_buff,
3347                     ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
3348         /*
3349          * If xfersize is 0 and pktcnt in not 0, resend the last packet.
3350          */
3351         if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
3352             ep->dwc_ep.start_xfer_buff != 0) {
3353                 if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
3354                         ep->dwc_ep.xfer_count = 0;
3355                         ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
3356                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
3357                 } else {
3358                         ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
3359                         /* convert packet size to dwords. */
3360                         ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
3361                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
3362                 }
3363                 ep->stopped = 0;
3364                 DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
3365                             "xfer_len=%0x stopped=%d\n",
3366                             ep->dwc_ep.xfer_buff,
3367                             ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
3368                             ep->stopped);
3369                 if (epnum == 0) {
3370                         dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
3371                 } else {
3372                         dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
3373                 }
3374         }
3375 }
3376
3377 /*
3378  * This function create new nextep sequnce based on Learn Queue.
3379  *
3380  * @param core_if Programming view of DWC_otg controller
3381  */
3382 void predict_nextep_seq(dwc_otg_core_if_t *core_if)
3383 {
3384         dwc_otg_device_global_regs_t *dev_global_regs =
3385             core_if->dev_if->dev_global_regs;
3386         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
3387         /* Number of Token Queue Registers */
3388         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
3389         dtknq1_data_t dtknqr1;
3390         uint32_t in_tkn_epnums[4];
3391         uint8_t seqnum[MAX_EPS_CHANNELS];
3392         uint8_t intkn_seq[TOKEN_Q_DEPTH];
3393         grstctl_t resetctl = {
3394         .d32 = 0};
3395         uint8_t temp;
3396         int ndx = 0;
3397         int start = 0;
3398         int end = 0;
3399         int sort_done = 0;
3400         int i = 0;
3401         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
3402
3403         DWC_DEBUGPL(DBG_PCD, "dev_token_q_depth=%d\n", TOKEN_Q_DEPTH);
3404
3405         /* Read the DTKNQ Registers */
3406         for (i = 0; i < DTKNQ_REG_CNT; i++) {
3407                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
3408                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
3409                             in_tkn_epnums[i]);
3410                 if (addr == &dev_global_regs->dvbusdis) {
3411                         addr = &dev_global_regs->dtknqr3_dthrctl;
3412                 } else {
3413                         ++addr;
3414                 }
3415
3416         }
3417
3418         /* Copy the DTKNQR1 data to the bit field. */
3419         dtknqr1.d32 = in_tkn_epnums[0];
3420         if (dtknqr1.b.wrap_bit) {
3421                 ndx = dtknqr1.b.intknwptr;
3422                 end = ndx - 1;
3423                 if (end < 0)
3424                         end = TOKEN_Q_DEPTH - 1;
3425         } else {
3426                 ndx = 0;
3427                 end = dtknqr1.b.intknwptr - 1;
3428                 if (end < 0)
3429                         end = 0;
3430         }
3431         start = ndx;
3432
3433         /* Fill seqnum[] by initial values: EP number + 31 */
3434         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3435                 seqnum[i] = i + 31;
3436         }
3437
3438         /* Fill intkn_seq[] from in_tkn_epnums[0] */
3439         for (i = 0; i < 6; i++)
3440                 intkn_seq[i] = (in_tkn_epnums[0] >> ((7 - i) * 4)) & 0xf;
3441
3442         if (TOKEN_Q_DEPTH > 6) {
3443                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
3444                 for (i = 6; i < 14; i++)
3445                         intkn_seq[i] =
3446                             (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
3447         }
3448
3449         if (TOKEN_Q_DEPTH > 14) {
3450                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
3451                 for (i = 14; i < 22; i++)
3452                         intkn_seq[i] =
3453                             (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
3454         }
3455
3456         if (TOKEN_Q_DEPTH > 22) {
3457                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
3458                 for (i = 22; i < 30; i++)
3459                         intkn_seq[i] =
3460                             (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
3461         }
3462
3463         DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
3464                     start, end);
3465         for (i = 0; i < TOKEN_Q_DEPTH; i++)
3466                 DWC_DEBUGPL(DBG_PCDV, "%d\n", intkn_seq[i]);
3467
3468         /* Update seqnum based on intkn_seq[] */
3469         i = 0;
3470         do {
3471                 seqnum[intkn_seq[ndx]] = i;
3472                 ndx++;
3473                 i++;
3474                 if (ndx == TOKEN_Q_DEPTH)
3475                         ndx = 0;
3476         } while (i < TOKEN_Q_DEPTH);
3477
3478         /* Mark non active EP's in seqnum[] by 0xff */
3479         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3480                 if (core_if->nextep_seq[i] == 0xff)
3481                         seqnum[i] = 0xff;
3482         }
3483
3484         /* Sort seqnum[] */
3485         sort_done = 0;
3486         while (!sort_done) {
3487                 sort_done = 1;
3488                 for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
3489                         if (seqnum[i] > seqnum[i + 1]) {
3490                                 temp = seqnum[i];
3491                                 seqnum[i] = seqnum[i + 1];
3492                                 seqnum[i + 1] = temp;
3493                                 sort_done = 0;
3494                         }
3495                 }
3496         }
3497
3498         ndx = start + seqnum[0];
3499         if (ndx >= TOKEN_Q_DEPTH)
3500                 ndx = ndx % TOKEN_Q_DEPTH;
3501         core_if->first_in_nextep_seq = intkn_seq[ndx];
3502
3503         /* Update seqnum[] by EP numbers  */
3504         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3505                 ndx = start + i;
3506                 if (seqnum[i] < 31) {
3507                         ndx = start + seqnum[i];
3508                         if (ndx >= TOKEN_Q_DEPTH)
3509                                 ndx = ndx % TOKEN_Q_DEPTH;
3510                         seqnum[i] = intkn_seq[ndx];
3511                 } else {
3512                         if (seqnum[i] < 0xff) {
3513                                 seqnum[i] = seqnum[i] - 31;
3514                         } else {
3515                                 break;
3516                         }
3517                 }
3518         }
3519
3520         /* Update nextep_seq[] based on seqnum[] */
3521         for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
3522                 if (seqnum[i] != 0xff) {
3523                         if (seqnum[i + 1] != 0xff) {
3524                                 core_if->nextep_seq[seqnum[i]] = seqnum[i + 1];
3525                         } else {
3526                                 core_if->nextep_seq[seqnum[i]] =
3527                                     core_if->first_in_nextep_seq;
3528                                 break;
3529                         }
3530                 } else {
3531                         break;
3532                 }
3533         }
3534
3535         DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3536                     __func__, core_if->first_in_nextep_seq);
3537         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3538                 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
3539         }
3540
3541         /* Flush the Learning Queue */
3542         resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
3543         resetctl.b.intknqflsh = 1;
3544         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
3545
3546 }
3547
3548 /**
3549  * handle the IN EP disable interrupt.
3550  */
3551 static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
3552                                              const uint32_t epnum)
3553 {
3554         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
3555         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3556         deptsiz_data_t dieptsiz = {
3557         .d32 = 0};
3558         dctl_data_t dctl = {
3559         .d32 = 0};
3560         dwc_otg_pcd_ep_t *ep;
3561         dwc_ep_t *dwc_ep;
3562         gintmsk_data_t gintmsk_data;
3563         depctl_data_t depctl;
3564         uint32_t diepdma;
3565         uint32_t remain_to_transfer = 0;
3566         uint8_t i;
3567         uint32_t xfer_size;
3568
3569         ep = get_in_ep(pcd, epnum);
3570         dwc_ep = &ep->dwc_ep;
3571
3572         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
3573                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
3574                 complete_ep(ep);
3575                 return;
3576         }
3577
3578         DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
3579                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
3580         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
3581         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
3582
3583         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
3584                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
3585
3586         if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
3587                 if (ep->stopped) {
3588                         if (core_if->en_multiple_tx_fifo)
3589                                 /* Flush the Tx FIFO */
3590                                 dwc_otg_flush_tx_fifo(core_if,
3591                                                       dwc_ep->tx_fifo_num);
3592                         /* Clear the Global IN NP NAK */
3593                         dctl.d32 = 0;
3594                         dctl.b.cgnpinnak = 1;
3595                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl,
3596                                          dctl.d32, dctl.d32);
3597                         /* Restart the transaction */
3598                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
3599                                 restart_transfer(pcd, epnum);
3600                         }
3601                 } else {
3602                         /* Restart the transaction */
3603                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
3604                                 restart_transfer(pcd, epnum);
3605                         }
3606                         DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
3607                 }
3608                 return;
3609         }
3610
3611         if (core_if->start_predict > 2) {
3612                 /* NP IN EP */
3613                 core_if->start_predict--;
3614                 return;
3615         }
3616
3617         core_if->start_predict--;
3618
3619         if (core_if->start_predict == 1) {
3620                 /* All NP IN Ep's disabled now */
3621                 predict_nextep_seq(core_if);
3622
3623                 /* Update all active IN EP's NextEP field based of nextep_seq[] */
3624                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3625                         depctl.d32 =
3626                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
3627                         if (core_if->nextep_seq[i] != 0xff) {
3628                                 /* Active NP IN EP */
3629                                 depctl.b.nextep = core_if->nextep_seq[i];
3630                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
3631                                                 depctl.d32);
3632                         }
3633                 }
3634                 /* Flush Shared NP TxFIFO */
3635                 dwc_otg_flush_tx_fifo(core_if, 0);
3636                 /* Rewind buffers */
3637                 if (!core_if->dma_desc_enable) {
3638                         i = core_if->first_in_nextep_seq;
3639                         do {
3640                                 ep = get_in_ep(pcd, i);
3641                                 dieptsiz.d32 =
3642                                     DWC_READ_REG32(&dev_if->
3643                                                    in_ep_regs[i]->dieptsiz);
3644                                 xfer_size =
3645                                     ep->dwc_ep.total_len -
3646                                     ep->dwc_ep.xfer_count;
3647                                 if (xfer_size > ep->dwc_ep.maxxfer)
3648                                         xfer_size = ep->dwc_ep.maxxfer;
3649                                 depctl.d32 =
3650                                     DWC_READ_REG32(&dev_if->
3651                                                    in_ep_regs[i]->diepctl);
3652                                 if (dieptsiz.b.pktcnt != 0) {
3653                                         if (xfer_size == 0) {
3654                                                 remain_to_transfer = 0;
3655                                         } else {
3656                                                 if ((xfer_size %
3657                                                      ep->dwc_ep.maxpacket) ==
3658                                                     0) {
3659                                                         remain_to_transfer =
3660                                                             dieptsiz.b.pktcnt *
3661                                                             ep->
3662                                                             dwc_ep.maxpacket;
3663                                                 } else {
3664                                                         remain_to_transfer =
3665                                                             ((dieptsiz.
3666                                                               b.pktcnt -
3667                                                               1) *
3668                                                              ep->
3669                                                              dwc_ep.maxpacket)
3670                                                             +
3671                                                             (xfer_size %
3672                                                              ep->
3673                                                              dwc_ep.maxpacket);
3674                                                 }
3675                                         }
3676                                         diepdma =
3677                                             DWC_READ_REG32(&dev_if->in_ep_regs
3678                                                            [i]->diepdma);
3679                                         dieptsiz.b.xfersize =
3680                                             remain_to_transfer;
3681                                         DWC_WRITE_REG32(&dev_if->
3682                                                         in_ep_regs[i]->dieptsiz,
3683                                                         dieptsiz.d32);
3684                                         diepdma =
3685                                             ep->dwc_ep.dma_addr + (xfer_size -
3686                                                                    remain_to_transfer);
3687                                         DWC_WRITE_REG32(&dev_if->
3688                                                         in_ep_regs[i]->diepdma,
3689                                                         diepdma);
3690                                 }
3691                                 i = core_if->nextep_seq[i];
3692                         } while (i != core_if->first_in_nextep_seq);
3693                 } else {        /* dma_desc_enable */
3694                         DWC_PRINTF("%s Learning Queue not supported in DDMA\n",
3695                                    __func__);
3696                 }
3697
3698                 /* Restart transfers in predicted sequences */
3699                 i = core_if->first_in_nextep_seq;
3700                 do {
3701                         dieptsiz.d32 =
3702                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
3703                         depctl.d32 =
3704                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
3705                         if (dieptsiz.b.pktcnt != 0) {
3706                                 depctl.d32 =
3707                                     DWC_READ_REG32(&dev_if->
3708                                                    in_ep_regs[i]->diepctl);
3709                                 depctl.b.epena = 1;
3710                                 depctl.b.cnak = 1;
3711                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
3712                                                 depctl.d32);
3713                         }
3714                         i = core_if->nextep_seq[i];
3715                 } while (i != core_if->first_in_nextep_seq);
3716
3717                 /* Clear the global non-periodic IN NAK handshake */
3718                 dctl.d32 = 0;
3719                 dctl.b.cgnpinnak = 1;
3720                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32,
3721                                  dctl.d32);
3722
3723                 /* Unmask EP Mismatch interrupt */
3724                 gintmsk_data.d32 = 0;
3725                 gintmsk_data.b.epmismatch = 1;
3726                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
3727                                  gintmsk_data.d32);
3728
3729                 core_if->start_predict = 0;
3730
3731         }
3732 }
3733
3734 /**
3735  * Handler for the IN EP timeout handshake interrupt.
3736  */
3737 static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
3738                                              const uint32_t epnum)
3739 {
3740         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
3741         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3742
3743 #ifdef DEBUG
3744         deptsiz_data_t dieptsiz = {
3745         .d32 = 0};
3746         uint32_t num = 0;
3747 #endif
3748         dctl_data_t dctl = {
3749         .d32 = 0};
3750         dwc_otg_pcd_ep_t *ep;
3751
3752         gintmsk_data_t intr_mask = {
3753         .d32 = 0};
3754
3755         ep = get_in_ep(pcd, epnum);
3756
3757         /* Disable the NP Tx Fifo Empty Interrrupt */
3758         if (!core_if->dma_enable) {
3759                 intr_mask.b.nptxfempty = 1;
3760                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
3761                                  intr_mask.d32, 0);
3762         }
3763         /** @todo NGS Check EP type.
3764          * Implement for Periodic EPs */
3765         /*
3766          * Non-periodic EP
3767          */
3768         /* Enable the Global IN NAK Effective Interrupt */
3769         intr_mask.b.ginnakeff = 1;
3770         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
3771
3772         /* Set Global IN NAK */
3773         dctl.b.sgnpinnak = 1;
3774         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3775
3776         ep->stopped = 1;
3777
3778 #ifdef DEBUG
3779         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
3780         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
3781                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
3782 #endif
3783
3784 #ifdef DISABLE_PERIODIC_EP
3785         /*
3786          * Set the NAK bit for this EP to
3787          * start the disable process.
3788          */
3789         diepctl.d32 = 0;
3790         diepctl.b.snak = 1;
3791         DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
3792                          diepctl.d32);
3793         ep->disabling = 1;
3794         ep->stopped = 1;
3795 #endif
3796 }
3797
3798 /**
3799  * Handler for the IN EP NAK interrupt.
3800  */
3801 static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
3802                                             const uint32_t epnum)
3803 {
3804         /** @todo implement ISR */
3805         dwc_otg_core_if_t *core_if;
3806         diepmsk_data_t intr_mask = {
3807         .d32 = 0};
3808
3809         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
3810         core_if = GET_CORE_IF(pcd);
3811         intr_mask.b.nak = 1;
3812
3813         if (core_if->multiproc_int_enable) {
3814                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3815                                  diepeachintmsk[epnum], intr_mask.d32, 0);
3816         } else {
3817                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
3818                                  intr_mask.d32, 0);
3819         }
3820
3821         return 1;
3822 }
3823
3824 /**
3825  * Handler for the OUT EP Babble interrupt.
3826  */
3827 static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
3828                                                 const uint32_t epnum)
3829 {
3830         /** @todo implement ISR */
3831         dwc_otg_core_if_t *core_if;
3832         doepmsk_data_t intr_mask = {
3833         .d32 = 0};
3834
3835         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
3836                    "OUT EP Babble");
3837         core_if = GET_CORE_IF(pcd);
3838         intr_mask.b.babble = 1;
3839
3840         if (core_if->multiproc_int_enable) {
3841                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3842                                  doepeachintmsk[epnum], intr_mask.d32, 0);
3843         } else {
3844                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
3845                                  intr_mask.d32, 0);
3846         }
3847
3848         return 1;
3849 }
3850
3851 /**
3852  * Handler for the OUT EP NAK interrupt.
3853  */
3854 static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
3855                                              const uint32_t epnum)
3856 {
3857         /** @todo implement ISR */
3858         dwc_otg_core_if_t *core_if;
3859         doepmsk_data_t intr_mask = {
3860         .d32 = 0};
3861
3862         DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n",
3863                     "OUT EP NAK");
3864         core_if = GET_CORE_IF(pcd);
3865         intr_mask.b.nak = 1;
3866
3867         if (core_if->multiproc_int_enable) {
3868                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3869                                  doepeachintmsk[epnum], intr_mask.d32, 0);
3870         } else {
3871                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
3872                                  intr_mask.d32, 0);
3873         }
3874
3875         return 1;
3876 }
3877
3878 /**
3879  * Handler for the OUT EP NYET interrupt.
3880  */
3881 static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
3882                                               const uint32_t epnum)
3883 {
3884         /** @todo implement ISR */
3885         dwc_otg_core_if_t *core_if;
3886         doepmsk_data_t intr_mask = {
3887         .d32 = 0};
3888
3889         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
3890         core_if = GET_CORE_IF(pcd);
3891         intr_mask.b.nyet = 1;
3892
3893         if (core_if->multiproc_int_enable) {
3894                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3895                                  doepeachintmsk[epnum], intr_mask.d32, 0);
3896         } else {
3897                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
3898                                  intr_mask.d32, 0);
3899         }
3900
3901         return 1;
3902 }
3903
3904 /**
3905  * This interrupt indicates that an IN EP has a pending Interrupt.
3906  * The sequence for handling the IN EP interrupt is shown below:
3907  * -#   Read the Device All Endpoint Interrupt register
3908  * -#   Repeat the following for each IN EP interrupt bit set (from
3909  *              LSB to MSB).
3910  * -#   Read the Device Endpoint Interrupt (DIEPINTn) register
3911  * -#   If "Transfer Complete" call the request complete function
3912  * -#   If "Endpoint Disabled" complete the EP disable procedure.
3913  * -#   If "AHB Error Interrupt" log error
3914  * -#   If "Time-out Handshake" log error
3915  * -#   If "IN Token Received when TxFIFO Empty" write packet to Tx
3916  *              FIFO.
3917  * -#   If "IN Token EP Mismatch" (disable, this is handled by EP
3918  *              Mismatch Interrupt)
3919  */
3920 static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
3921 {
3922 #define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr) \
3923 do { \
3924                 diepint_data_t diepint = {.d32 = 0}; \
3925                 diepint.b.__intr = 1; \
3926                 DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
3927                 diepint.d32); \
3928 } while (0)
3929
3930         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
3931         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3932         diepint_data_t diepint = {
3933         .d32 = 0};
3934         depctl_data_t depctl = {
3935         .d32 = 0};
3936         uint32_t ep_intr;
3937         uint32_t epnum = 0;
3938         dwc_otg_pcd_ep_t *ep;
3939         dwc_ep_t *dwc_ep;
3940         gintmsk_data_t intr_mask = {
3941         .d32 = 0};
3942         dctl_data_t dctl = {
3943         .d32 = 0};
3944
3945         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
3946
3947         /* Read in the device interrupt bits */
3948         ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
3949
3950         /* Service the Device IN interrupts for each endpoint */
3951         while (ep_intr) {
3952                 if (ep_intr & 0x1) {
3953                         uint32_t empty_msk;
3954                         /* Get EP pointer */
3955                         ep = get_in_ep(pcd, epnum);
3956                         dwc_ep = &ep->dwc_ep;
3957
3958                         depctl.d32 =
3959                             DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
3960                         empty_msk =
3961                             DWC_READ_REG32(&dev_if->
3962                                            dev_global_regs->dtknqr4_fifoemptymsk);
3963
3964                         DWC_DEBUGPL(DBG_PCDV,
3965                                     "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
3966                                     epnum, empty_msk, depctl.d32);
3967
3968                         DWC_DEBUGPL(DBG_PCD,
3969                                     "EP%d-%s: type=%d, mps=%d\n",
3970                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
3971                                     dwc_ep->type, dwc_ep->maxpacket);
3972
3973                         diepint.d32 =
3974                             dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
3975
3976                         DWC_DEBUGPL(DBG_PCDV,
3977                                     "EP %d Interrupt Register - 0x%x\n", epnum,
3978                                     diepint.d32);
3979                         /* Transfer complete */
3980                         if (diepint.b.xfercompl) {
3981                                 /* Disable the NP Tx FIFO Empty
3982                                  * Interrupt */
3983                                 if (core_if->en_multiple_tx_fifo == 0) {
3984                                         intr_mask.b.nptxfempty = 1;
3985                                         DWC_MODIFY_REG32
3986                                             (&core_if->
3987                                              core_global_regs->gintmsk,
3988                                              intr_mask.d32, 0);
3989                                 } else {
3990                                         /* Disable the Tx FIFO Empty Interrupt for this EP */
3991                                         uint32_t fifoemptymsk =
3992                                             0x1 << dwc_ep->num;
3993                                         DWC_MODIFY_REG32(&core_if->
3994                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3995                                                          fifoemptymsk, 0);
3996                                 }
3997                                 /* Clear the bit in DIEPINTn for this interrupt */
3998                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
3999
4000                                 /* Complete the transfer */
4001                                 if (epnum == 0) {
4002                                         handle_ep0(pcd);
4003                                 }
4004 #ifdef DWC_EN_ISOC
4005                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
4006                                         if (!ep->stopped)
4007                                                 complete_iso_ep(pcd, ep);
4008                                 }
4009 #endif /* DWC_EN_ISOC */
4010 #ifdef DWC_UTE_PER_IO
4011                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
4012                                         if (!ep->stopped)
4013                                                 complete_xiso_ep(ep);
4014                                 }
4015 #endif /* DWC_UTE_PER_IO */
4016                                 else {
4017                                         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC
4018                                             && dwc_ep->bInterval > 1) {
4019                                                 dwc_ep->frame_num +=
4020                                                     dwc_ep->bInterval;
4021                                                 if (dwc_ep->frame_num > 0x3FFF) {
4022                                                         dwc_ep->frm_overrun = 1;
4023                                                         dwc_ep->frame_num &=
4024                                                             0x3FFF;
4025                                                 } else
4026                                                         dwc_ep->frm_overrun = 0;
4027                                         }
4028                                         complete_ep(ep);
4029                                         if (diepint.b.nak)
4030                                                 CLEAR_IN_EP_INTR(core_if, epnum,
4031                                                                  nak);
4032                                 }
4033                         }
4034                         /* Endpoint disable      */
4035                         if (diepint.b.epdisabled) {
4036                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
4037                                             epnum);
4038                                 handle_in_ep_disable_intr(pcd, epnum);
4039
4040                                 /* Clear the bit in DIEPINTn for this interrupt */
4041                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
4042                         }
4043                         /* AHB Error */
4044                         if (diepint.b.ahberr) {
4045                                 DWC_ERROR("EP%d IN AHB Error\n", epnum);
4046                                 /* Clear the bit in DIEPINTn for this interrupt */
4047                                 DWC_ERROR("EP%d DEPDMA=0x%08x \n",
4048                                           epnum,
4049                                           core_if->dev_if->
4050                                           in_ep_regs[epnum]->diepdma);
4051                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
4052                                 dctl.d32 =
4053                                     DWC_READ_REG32(&core_if->
4054                                                    dev_if->dev_global_regs->
4055                                                    dctl);
4056                                 dctl.b.sftdiscon = 1;
4057                                 DWC_WRITE_REG32(&core_if->
4058                                                 dev_if->dev_global_regs->dctl,
4059                                                 dctl.d32);
4060                                 dwc_otg_disable_global_interrupts(core_if);
4061                                 ep->pcd->vbus_status = 0;
4062                                 if (ep->pcd->conn_status) {
4063                                         ep->pcd->conn_status = 0;
4064                                 }
4065                                 DWC_SPINUNLOCK(pcd->lock);
4066                                 cil_pcd_stop(core_if);
4067                                 DWC_SPINLOCK(pcd->lock);
4068                         }
4069                         /* TimeOUT Handshake (non-ISOC IN EPs) */
4070                         if (diepint.b.timeout) {
4071                                 DWC_ERROR("EP%d IN Time-out\n", epnum);
4072                                 handle_in_ep_timeout_intr(pcd, epnum);
4073
4074                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
4075                         }
4076                         /** IN Token received with TxF Empty */
4077                         if (diepint.b.intktxfemp) {
4078                                 DWC_DEBUGPL(DBG_ANY,
4079                                             "EP%d IN TKN TxFifo Empty\n",
4080                                             epnum);
4081                                 if (!ep->stopped && epnum != 0) {
4082
4083                                         diepmsk_data_t diepmsk = {
4084                                         .d32 = 0};
4085                                         diepmsk.b.intktxfemp = 1;
4086
4087                                         if (core_if->multiproc_int_enable) {
4088                                                 DWC_MODIFY_REG32
4089                                                     (&dev_if->
4090                                                      dev_global_regs->diepeachintmsk
4091                                                      [epnum], diepmsk.d32, 0);
4092                                         } else {
4093                                                 DWC_MODIFY_REG32
4094                                                     (&dev_if->
4095                                                      dev_global_regs->diepmsk,
4096                                                      diepmsk.d32, 0);
4097                                         }
4098                                 } else if (core_if->dma_desc_enable
4099                                            && epnum == 0
4100                                            && pcd->ep0state ==
4101                                            EP0_OUT_STATUS_PHASE) {
4102                                         /* EP0 IN set STALL */
4103                                         depctl.d32 =
4104                                             DWC_READ_REG32(&dev_if->in_ep_regs
4105                                                            [epnum]->diepctl);
4106
4107                                         /* set the disable and stall bits */
4108                                         if (depctl.b.epena) {
4109                                                 depctl.b.epdis = 1;
4110                                         }
4111                                         depctl.b.stall = 1;
4112                                         DWC_WRITE_REG32(&dev_if->in_ep_regs
4113                                                         [epnum]->diepctl,
4114                                                         depctl.d32);
4115                                 }
4116                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
4117                         }
4118                         /** IN Token Received with EP mismatch */
4119                         if (diepint.b.intknepmis) {
4120                                 DWC_DEBUGPL(DBG_ANY,
4121                                             "EP%d IN TKN EP Mismatch\n", epnum);
4122                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
4123                         }
4124                         /** IN Endpoint NAK Effective */
4125                         if (diepint.b.inepnakeff) {
4126                                 DWC_DEBUGPL(DBG_ANY,
4127                                             "EP%d IN EP NAK Effective\n",
4128                                             epnum);
4129                                 /* Periodic EP */
4130                                 if (ep->disabling) {
4131                                         depctl.d32 = 0;
4132                                         depctl.b.snak = 1;
4133                                         depctl.b.epdis = 1;
4134                                         DWC_MODIFY_REG32(&dev_if->in_ep_regs
4135                                                          [epnum]->diepctl,
4136                                                          depctl.d32,
4137                                                          depctl.d32);
4138                                 }
4139                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
4140
4141                         }
4142
4143                         /** IN EP Tx FIFO Empty Intr */
4144                         if (diepint.b.emptyintr) {
4145                                 DWC_DEBUGPL(DBG_ANY,
4146                                             "EP%d Tx FIFO Empty Intr \n",
4147                                             epnum);
4148                                 write_empty_tx_fifo(pcd, epnum);
4149
4150                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
4151
4152                         }
4153
4154                         /** IN EP BNA Intr */
4155                         if (diepint.b.bna) {
4156                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
4157                                 if (core_if->dma_desc_enable) {
4158 #ifdef DWC_EN_ISOC
4159                                         if (dwc_ep->type ==
4160                                             DWC_OTG_EP_TYPE_ISOC) {
4161                                                 /*
4162                                                  * This checking is performed to prevent first "false" BNA
4163                                                  * handling occuring right after reconnect
4164                                                  */
4165                                                 if (dwc_ep->next_frame !=
4166                                                     0xffffffff)
4167                                                         dwc_otg_pcd_handle_iso_bna
4168                                                             (ep);
4169                                         } else
4170 #endif /* DWC_EN_ISOC */
4171                                         {
4172                                                 dwc_otg_pcd_handle_noniso_bna
4173                                                     (ep);
4174                                         }
4175                                 }
4176                         }
4177                         /* NAK Interrutp */
4178                         if (diepint.b.nak) {
4179                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
4180                                             epnum);
4181                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
4182                                         depctl_data_t depctl;
4183                                         if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
4184                                                 ep->dwc_ep.frame_num =
4185                                                     core_if->frame_num;
4186                                                 if (ep->dwc_ep.bInterval > 1) {
4187                                                         depctl.d32 = 0;
4188                                                         depctl.d32 =
4189                                                             DWC_READ_REG32
4190                                                             (&dev_if->in_ep_regs
4191                                                              [epnum]->diepctl);
4192                                                         if (ep->
4193                                                             dwc_ep.frame_num &
4194                                                             0x1) {
4195                                                                 depctl.
4196                                                                     b.setd1pid =
4197                                                                     1;
4198                                                                 depctl.
4199                                                                     b.setd0pid =
4200                                                                     0;
4201                                                         } else {
4202                                                                 depctl.
4203                                                                     b.setd0pid =
4204                                                                     1;
4205                                                                 depctl.
4206                                                                     b.setd1pid =
4207                                                                     0;
4208                                                         }
4209                                                         DWC_WRITE_REG32
4210                                                             (&dev_if->in_ep_regs
4211                                                              [epnum]->diepctl,
4212                                                              depctl.d32);
4213                                                 }
4214                                                 start_next_request(ep);
4215                                         }
4216                                         ep->dwc_ep.frame_num +=
4217                                             ep->dwc_ep.bInterval;
4218                                         if (dwc_ep->frame_num > 0x3FFF) {
4219                                                 dwc_ep->frm_overrun = 1;
4220                                                 dwc_ep->frame_num &= 0x3FFF;
4221                                         } else
4222                                                 dwc_ep->frm_overrun = 0;
4223                                 }
4224
4225                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
4226                         }
4227                 }
4228                 epnum++;
4229                 ep_intr >>= 1;
4230         }
4231
4232         return 1;
4233 #undef CLEAR_IN_EP_INTR
4234 }
4235
4236 /**
4237  * This interrupt indicates that an OUT EP has a pending Interrupt.
4238  * The sequence for handling the OUT EP interrupt is shown below:
4239  * -#   Read the Device All Endpoint Interrupt register
4240  * -#   Repeat the following for each OUT EP interrupt bit set (from
4241  *              LSB to MSB).
4242  * -#   Read the Device Endpoint Interrupt (DOEPINTn) register
4243  * -#   If "Transfer Complete" call the request complete function
4244  * -#   If "Endpoint Disabled" complete the EP disable procedure.
4245  * -#   If "AHB Error Interrupt" log error
4246  * -#   If "Setup Phase Done" process Setup Packet (See Standard USB
4247  *              Command Processing)
4248  */
4249 static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
4250 {
4251 #define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr) \
4252 do { \
4253                 doepint_data_t doepint = {.d32 = 0}; \
4254                 doepint.b.__intr = 1; \
4255                 DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
4256                 doepint.d32); \
4257 } while (0)
4258
4259         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
4260         uint32_t ep_intr;
4261         doepint_data_t doepint = {
4262         .d32 = 0};
4263         uint32_t epnum = 0;
4264         dwc_otg_pcd_ep_t *ep;
4265         dwc_ep_t *dwc_ep;
4266         dctl_data_t dctl = {
4267         .d32 = 0};
4268         gintmsk_data_t gintmsk = {
4269         .d32 = 0};
4270
4271         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
4272
4273         /* Read in the device interrupt bits */
4274         ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
4275
4276         while (ep_intr) {
4277                 if (ep_intr & 0x1) {
4278                         /* Get EP pointer */
4279                         ep = get_out_ep(pcd, epnum);
4280                         dwc_ep = &ep->dwc_ep;
4281
4282 #ifdef VERBOSE
4283                         DWC_DEBUGPL(DBG_PCDV,
4284                                     "EP%d-%s: type=%d, mps=%d\n",
4285                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
4286                                     dwc_ep->type, dwc_ep->maxpacket);
4287 #endif
4288                         doepint.d32 =
4289                             dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
4290                         /* Transfer complete */
4291                         if (doepint.b.xfercompl) {
4292
4293                                 if (epnum == 0) {
4294                                         /* Clear the bit in DOEPINTn for this interrupt */
4295                                         CLEAR_OUT_EP_INTR(core_if, epnum,
4296                                                           xfercompl);
4297                                         if (core_if->snpsid >=
4298                                             OTG_CORE_REV_3_00a) {
4299                                                 DWC_DEBUGPL(DBG_PCDV,
4300                                                             "in xfer xomplete DOEPINT=%x doepint=%x\n",
4301                                                             DWC_READ_REG32
4302                                                             (&core_if->
4303                                                              dev_if->out_ep_regs
4304                                                              [0]->doepint),
4305                                                             doepint.d32);
4306                                                 DWC_DEBUGPL(DBG_PCDV,
4307                                                             "DOEPCTL=%x \n",
4308                                                             DWC_READ_REG32
4309                                                             (&core_if->
4310                                                              dev_if->out_ep_regs
4311                                                              [0]->doepctl));
4312
4313                                                 if (core_if->snpsid >=
4314                                                     OTG_CORE_REV_3_00a
4315                                                     && core_if->dma_enable ==
4316                                                     0) {
4317                                                         doepint_data_t doepint;
4318                                                         doepint.d32 =
4319                                                             DWC_READ_REG32
4320                                                             (&core_if->dev_if->
4321                                                              out_ep_regs[0]->
4322                                                              doepint);
4323                                                         if (pcd->ep0state ==
4324                                                             EP0_IDLE
4325                                                             && doepint.b.sr) {
4326                                                                 CLEAR_OUT_EP_INTR
4327                                                                     (core_if,
4328                                                                      epnum, sr);
4329                                                                 goto exit_xfercompl;
4330                                                         }
4331                                                 }
4332                                                 /* In case of DDMA  look at SR bit to go to the Data Stage */
4333                                                 if (core_if->dma_desc_enable) {
4334                                                         dev_dma_desc_sts_t
4335                                                             status = {
4336                                                         .d32 = 0};
4337                                                         if (pcd->ep0state ==
4338                                                             EP0_IDLE) {
4339                                                                 status.d32 =
4340                                                                     core_if->dev_if->setup_desc_addr
4341                                                                     [core_if->
4342                                                                      dev_if->setup_desc_index]->status.
4343                                                                     d32;
4344                                                                 if (pcd->data_terminated) {
4345                                                                         pcd->data_terminated
4346                                                                             = 0;
4347                                                                         status.d32
4348                                                                             =
4349                                                                             core_if->dev_if->out_desc_addr->status.d32;
4350                                                                         dwc_memcpy
4351                                                                             (&pcd->setup_pkt->req,
4352                                                                              pcd->backup_buf,
4353                                                                              8);
4354                                                                 }
4355                                                                 if (status.b.sr) {
4356                                                                         if (doepint.b.setup) {
4357                                                                                 DWC_DEBUGPL
4358                                                                                     (DBG_PCDV,
4359                                                                                      "DMA DESC EP0_IDLE SR=1 setup=1\n");
4360                                                                                 /* Already started data stage, clear setup */
4361                                                                                 CLEAR_OUT_EP_INTR
4362                                                                                     (core_if,
4363                                                                                      epnum,
4364                                                                                      setup);
4365                                                                                 doepint.b.setup
4366                                                                                     =
4367                                                                                     0;
4368                                                                                 handle_ep0
4369                                                                                     (pcd);
4370                                                                                 /* Prepare for more setup packets */
4371                                                                                 if (pcd->ep0state == EP0_IN_STATUS_PHASE || pcd->ep0state == EP0_IN_DATA_PHASE) {
4372                                                                                         ep0_out_start
4373                                                                                             (core_if,
4374                                                                                              pcd);
4375                                                                                 }
4376
4377                                                                                 goto exit_xfercompl;
4378                                                                         } else {
4379                                                                                 /* Prepare for more setup packets */
4380                                                                                 DWC_DEBUGPL
4381                                                                                     (DBG_PCDV,
4382                                                                                      "EP0_IDLE SR=1 setup=0 new setup comes\n");
4383                                                                                 ep0_out_start
4384                                                                                     (core_if,
4385                                                                                      pcd);
4386                                                                         }
4387                                                                 }
4388                                                         } else {
4389                                                                 dwc_otg_pcd_request_t
4390                                                                     *req;
4391                                                                 dev_dma_desc_sts_t
4392                                                                     status = {
4393                                                                 .d32 = 0};
4394                                                                 diepint_data_t
4395                                                                     diepint0;
4396                                                                 diepint0.d32 =
4397                                                                     DWC_READ_REG32
4398                                                                     (&core_if->dev_if->
4399                                                                      in_ep_regs
4400                                                                      [0]->diepint);
4401
4402                                                                 if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
4403                                                                         DWC_ERROR
4404                                                                             ("EP0 is stalled/disconnected\n");
4405                                                                 }
4406
4407                                                                 /* Clear IN xfercompl if set */
4408                                                                 if (diepint0.
4409                                                                     b.xfercompl
4410                                                                     &&
4411                                                                     (pcd->ep0state
4412                                                                      ==
4413                                                                      EP0_IN_STATUS_PHASE
4414                                                                      ||
4415                                                                      pcd->ep0state
4416                                                                      ==
4417                                                                      EP0_IN_DATA_PHASE)) {
4418                                                                         DWC_WRITE_REG32
4419                                                                             (&core_if->dev_if->
4420                                                                              in_ep_regs
4421                                                                              [0]->diepint,
4422                                                                              diepint0.d32);
4423                                                                 }
4424
4425                                                                 status.d32 =
4426                                                                     core_if->dev_if->setup_desc_addr
4427                                                                     [core_if->
4428                                                                      dev_if->setup_desc_index]->status.
4429                                                                     d32;
4430
4431                                                                 if (ep->
4432                                                                     dwc_ep.xfer_count
4433                                                                     !=
4434                                                                     ep->
4435                                                                     dwc_ep.total_len
4436                                                                     &&
4437                                                                     (pcd->ep0state
4438                                                                      ==
4439                                                                      EP0_OUT_DATA_PHASE))
4440                                                                         status.d32
4441                                                                             =
4442                                                                             core_if->dev_if->out_desc_addr->status.d32;
4443                                                                 if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
4444                                                                         status.d32
4445                                                                             =
4446                                                                             core_if->dev_if->
4447                                                                             out_desc_addr->status.d32;
4448
4449                                                                 if (status.b.sr) {
4450                                                                         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
4451                                                                                 DWC_DEBUGPL
4452                                                                                     (DBG_PCDV,
4453                                                                                      "Request queue empty!!\n");
4454                                                                         } else {
4455                                                                                 DWC_DEBUGPL
4456                                                                                     (DBG_PCDV,
4457                                                                                      "complete req!!\n");
4458                                                                                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
4459                                                                                 if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && pcd->ep0state == EP0_OUT_DATA_PHASE) {
4460                                                                                         /* Read arrived setup packet from req->buf */
4461                                                                                         dwc_memcpy
4462                                                                                             (&pcd->setup_pkt->req,
4463                                                                                              req->buf
4464                                                                                              +
4465                                                                                              ep->dwc_ep.xfer_count,
4466                                                                                              8);
4467                                                                                 }
4468                                                                                 req->actual
4469                                                                                     =
4470                                                                                     ep->dwc_ep.xfer_count;
4471                                                                                 dwc_otg_request_done
4472                                                                                     (ep,
4473                                                                                      req,
4474                                                                                      -ECONNRESET);
4475                                                                                 ep->dwc_ep.start_xfer_buff = 0;
4476                                                                                 ep->dwc_ep.xfer_buff = 0;
4477                                                                                 ep->dwc_ep.xfer_len = 0;
4478                                                                         }
4479                                                                         pcd->ep0state
4480                                                                             =
4481                                                                             EP0_IDLE;
4482                                                                         if (doepint.b.setup) {
4483                                                                                 DWC_DEBUGPL
4484                                                                                     (DBG_PCDV,
4485                                                                                      "EP0_IDLE SR=1 setup=1\n");
4486                                                                                 /* Data stage started, clear setup */
4487                                                                                 CLEAR_OUT_EP_INTR
4488                                                                                     (core_if,
4489                                                                                      epnum,
4490                                                                                      setup);
4491                                                                                 doepint.b.setup
4492                                                                                     =
4493                                                                                     0;
4494                                                                                 handle_ep0
4495                                                                                     (pcd);
4496                                                                                 /* Prepare for setup packets if ep0in was enabled */
4497                                                                                 if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
4498                                                                                         ep0_out_start
4499                                                                                             (core_if,
4500                                                                                              pcd);
4501                                                                                 }
4502
4503                                                                                 goto exit_xfercompl;
4504                                                                         } else {
4505                                                                                 /* Prepare for more setup packets */
4506                                                                                 DWC_DEBUGPL
4507                                                                                     (DBG_PCDV,
4508                                                                                      "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
4509                                                                                 ep0_out_start
4510                                                                                     (core_if,
4511                                                                                      pcd);
4512                                                                         }
4513                                                                 }
4514                                                         }
4515                                                 }
4516                                                 if (core_if->snpsid >=
4517                                                     OTG_CORE_REV_3_00a
4518                                                     && core_if->dma_enable
4519                                                     && core_if->dma_desc_enable
4520                                                     == 0) {
4521                                                         doepint_data_t
4522                                                             doepint_temp = {
4523                                                         .d32 = 0};
4524                                                         deptsiz0_data_t
4525                                                             doeptsize0 = {
4526                                                         .d32 = 0};
4527                                                         doepint_temp.d32 =
4528                                                             DWC_READ_REG32
4529                                                             (&core_if->dev_if->
4530                                                              out_ep_regs[ep->
4531                                                                          dwc_ep.
4532                                                                          num]->doepint);
4533                                                         doeptsize0.d32 =
4534                                                             DWC_READ_REG32
4535                                                             (&core_if->dev_if->
4536                                                              out_ep_regs[ep->
4537                                                                          dwc_ep.
4538                                                                          num]->doeptsiz);
4539                                                         if (((ep->
4540                                                               dwc_ep.xfer_count
4541                                                               ==
4542                                                               ep->
4543                                                               dwc_ep.total_len
4544                                                               || doeptsize0.
4545                                                               b.xfersize == 64)
4546                                                              && pcd->ep0state ==
4547                                                              EP0_OUT_DATA_PHASE
4548                                                              && doepint.
4549                                                              b.stsphsercvd)
4550                                                             || (doeptsize0.
4551                                                                 b.xfersize == 24
4552                                                                 && pcd->ep0state
4553                                                                 ==
4554                                                                 EP0_IN_STATUS_PHASE)){
4555                                                                 CLEAR_OUT_EP_INTR
4556                                                                     (core_if,
4557                                                                      epnum,
4558                                                                      xfercompl);
4559                                                                 DWC_DEBUGPL
4560                                                                     (DBG_PCDV,
4561                                                                      "WA for xfercompl along with stsphs \n");
4562                                                                 doepint.
4563                                                                     b.xfercompl
4564                                                                     = 0;
4565                                                                 ep0_out_start
4566                                                                     (core_if,
4567                                                                      pcd);
4568                                                                 goto exit_xfercompl;
4569                                                         }
4570
4571                                                         if (pcd->ep0state ==
4572                                                             EP0_IDLE) {
4573                                                                 if (doepint_temp.b.sr) {
4574                                                                         CLEAR_OUT_EP_INTR
4575                                                                             (core_if,
4576                                                                              epnum,
4577                                                                              sr);
4578                                                                 }
4579                                                                 /* Delay is needed for core to update setup
4580                                                                  * packet count from 3 to 2 after receiving
4581                                                                  * setup packet*/
4582                                                                 dwc_udelay(100);
4583                                                                 doepint.d32 =
4584                                                                     DWC_READ_REG32
4585                                                                     (&core_if->dev_if->
4586                                                                      out_ep_regs
4587                                                                      [0]->doepint);
4588                                                                 if (doeptsize0.b.supcnt == 3) {
4589                                                                         DWC_DEBUGPL
4590                                                                             (DBG_ANY,
4591                                                                              "Rolling over!!!!!!!\n");
4592                                                                         ep->dwc_ep.stp_rollover = 1;
4593                                                                 }
4594                                                                 if (doepint.
4595                                                                     b.setup) {
4596 retry:
4597                                                                         /* Already started data stage, clear setup */
4598                                                                         CLEAR_OUT_EP_INTR(core_if, epnum, setup);
4599                                                                         doepint.b.setup
4600                                                                             = 0;
4601                                                                         handle_ep0
4602                                                                             (pcd);
4603                                                                         ep->dwc_ep.stp_rollover = 0;
4604                                                                         /* Prepare for more setup packets */
4605                                                                         if (pcd->ep0state == EP0_IN_STATUS_PHASE || pcd->ep0state == EP0_IN_DATA_PHASE) {
4606                                                                                 depctl_data_t
4607                                                                                     depctl
4608                                                                                     = {
4609                                                                                 .d32 = 0};
4610                                                                                 depctl.b.cnak
4611                                                                                     =
4612                                                                                     1;
4613                                                                                 ep0_out_start
4614                                                                                     (core_if,
4615                                                                                      pcd);
4616                                                                                 /* Core not updating setup packet count
4617                                                                                  * in case of PET testing - @TODO vahrama
4618                                                                                  * to check with HW team further */
4619                                                                                 if (!core_if->otg_ver) {
4620                                                                                         DWC_MODIFY_REG32
4621                                                                                             (&core_if->dev_if->
4622                                                                                              out_ep_regs
4623                                                                                              [0]->doepctl,
4624                                                                                              0,
4625                                                                                              depctl.d32);
4626                                                                                 }
4627                                                                         }
4628                                                                         goto exit_xfercompl;
4629                                                                 } else {
4630                                                                         /* Prepare for more setup packets */
4631                                                                         DWC_DEBUGPL
4632                                                                             (DBG_ANY,
4633                                                                              "EP0_IDLE SR=1 setup=0 new setup comes\n");
4634                                                                         doepint.d32
4635                                                                             =
4636                                                                             DWC_READ_REG32
4637                                                                             (&core_if->dev_if->
4638                                                                              out_ep_regs
4639                                                                              [0]->doepint);
4640                                                                         if (doepint.b.setup)
4641                                                                                 goto retry;
4642                                                                         ep0_out_start
4643                                                                             (core_if,
4644                                                                              pcd);
4645                                                                 }
4646                                                         } else {
4647                                                                 dwc_otg_pcd_request_t
4648                                                                     *req;
4649                                                                 diepint_data_t
4650                                                                     diepint0 = {
4651                                                                 .d32 = 0};
4652                                                                 doepint_data_t
4653                                                                     doepint_temp
4654                                                                     = {
4655                                                                 .d32 = 0};
4656                                                                 depctl_data_t
4657                                                                     diepctl0;
4658                                                                 diepint0.d32 =
4659                                                                     DWC_READ_REG32
4660                                                                     (&core_if->dev_if->
4661                                                                      in_ep_regs
4662                                                                      [0]->diepint);
4663                                                                 diepctl0.d32 =
4664                                                                     DWC_READ_REG32
4665                                                                     (&core_if->dev_if->
4666                                                                      in_ep_regs
4667                                                                      [0]->diepctl);
4668
4669                                                                 if (pcd->ep0state == EP0_IN_DATA_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
4670                                                                         if (diepint0.b.xfercompl) {
4671                                                                                 DWC_WRITE_REG32
4672                                                                                     (&core_if->dev_if->
4673                                                                                      in_ep_regs
4674                                                                                      [0]->diepint,
4675                                                                                      diepint0.d32);
4676                                                                         }
4677                                                                         if (diepctl0.b.epena) {
4678                                                                                 diepint_data_t
4679                                                                                     diepint
4680                                                                                     = {
4681                                                                                 .d32 = 0};
4682                                                                                 diepctl0.b.snak
4683                                                                                     =
4684                                                                                     1;
4685                                                                                 DWC_WRITE_REG32
4686                                                                                     (&core_if->dev_if->
4687                                                                                      in_ep_regs
4688                                                                                      [0]->diepctl,
4689                                                                                      diepctl0.d32);
4690                                                                                 do {
4691                                                                                         dwc_udelay
4692                                                                                             (10);
4693                                                                                         diepint.d32
4694                                                                                             =
4695                                                                                             DWC_READ_REG32
4696                                                                                             (&core_if->dev_if->
4697                                                                                              in_ep_regs
4698                                                                                              [0]->diepint);
4699                                                                                 } while (!diepint.b.inepnakeff);
4700                                                                                 diepint.b.inepnakeff
4701                                                                                     =
4702                                                                                     1;
4703                                                                                 DWC_WRITE_REG32
4704                                                                                     (&core_if->dev_if->
4705                                                                                      in_ep_regs
4706                                                                                      [0]->diepint,
4707                                                                                      diepint.d32);
4708                                                                                 diepctl0.d32
4709                                                                                     =
4710                                                                                     0;
4711                                                                                 diepctl0.b.epdis
4712                                                                                     =
4713                                                                                     1;
4714                                                                                 DWC_WRITE_REG32
4715                                                                                     (&core_if->dev_if->in_ep_regs
4716                                                                                      [0]->diepctl,
4717                                                                                      diepctl0.d32);
4718                                                                                 do {
4719                                                                                         dwc_udelay
4720                                                                                             (10);
4721                                                                                         diepint.d32
4722                                                                                             =
4723                                                                                             DWC_READ_REG32
4724                                                                                             (&core_if->dev_if->
4725                                                                                              in_ep_regs
4726                                                                                              [0]->diepint);
4727                                                                                 } while (!diepint.b.epdisabled);
4728                                                                                 diepint.b.epdisabled
4729                                                                                     =
4730                                                                                     1;
4731                                                                                 DWC_WRITE_REG32
4732                                                                                     (&core_if->dev_if->in_ep_regs
4733                                                                                      [0]->diepint,
4734                                                                                      diepint.d32);
4735                                                                         }
4736                                                                 }
4737                                                                 doepint_temp.d32
4738                                                                     =
4739                                                                     DWC_READ_REG32
4740                                                                     (&core_if->dev_if->
4741                                                                      out_ep_regs
4742                                                                      [ep->dwc_ep.num]->doepint);
4743                                                                 if (doepint_temp.b.sr) {
4744                                                                         CLEAR_OUT_EP_INTR
4745                                                                             (core_if,
4746                                                                              epnum,
4747                                                                              sr);
4748                                                                         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
4749                                                                                 DWC_DEBUGPL
4750                                                                                     (DBG_PCDV,
4751                                                                                      "Request queue empty!!\n");
4752                                                                         } else {
4753                                                                                 DWC_DEBUGPL
4754                                                                                     (DBG_PCDV,
4755                                                                                      "complete req!!\n");
4756                                                                                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
4757                                                                                 if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && pcd->ep0state == EP0_OUT_DATA_PHASE) {
4758                                                                                         /* Read arrived setup packet from req->buf */
4759                                                                                         dwc_memcpy
4760                                                                                             (&pcd->setup_pkt->req,
4761                                                                                              req->buf
4762                                                                                              +
4763                                                                                              ep->dwc_ep.xfer_count,
4764                                                                                              8);
4765                                                                                 }
4766                                                                                 req->actual
4767                                                                                     =
4768                                                                                     ep->dwc_ep.xfer_count;
4769                                                                                 dwc_otg_request_done
4770                                                                                     (ep,
4771                                                                                      req,
4772                                                                                      -ECONNRESET);
4773                                                                                 ep->dwc_ep.start_xfer_buff = 0;
4774                                                                                 ep->dwc_ep.xfer_buff = 0;
4775                                                                                 ep->dwc_ep.xfer_len = 0;
4776                                                                         }
4777                                                                         pcd->ep0state
4778                                                                             =
4779                                                                             EP0_IDLE;
4780                                                                         if (doepint.b.setup) {
4781                                                                                 DWC_DEBUGPL
4782                                                                                     (DBG_PCDV,
4783                                                                                      "EP0_IDLE SR=1 setup=1\n");
4784                                                                                 /* Data stage started, clear setup */
4785                                                                                 CLEAR_OUT_EP_INTR
4786                                                                                     (core_if,
4787                                                                                      epnum,
4788                                                                                      setup);
4789                                                                                 doepint.b.setup
4790                                                                                     =
4791                                                                                     0;
4792                                                                                 handle_ep0
4793                                                                                     (pcd);
4794                                                                                 /* Prepare for setup packets if ep0in was enabled */
4795                                                                                 if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
4796                                                                                         depctl_data_t
4797                                                                                             depctl
4798                                                                                             = {
4799                                                                                         .d32 = 0};
4800                                                                                         depctl.b.cnak
4801                                                                                             =
4802                                                                                             1;
4803                                                                                         ep0_out_start
4804                                                                                             (core_if,
4805                                                                                              pcd);
4806                                                                                         /* Core not updating setup packet count
4807                                                                                          * in case of PET testing - @TODO vahrama
4808                                                                                          * to check with HW team further */
4809                                                                                         if (!core_if->otg_ver) {
4810                                                                                                 DWC_MODIFY_REG32
4811                                                                                                     (&core_if->dev_if->
4812                                                                                                      out_ep_regs
4813                                                                                                      [0]->doepctl,
4814                                                                                                      0,
4815                                                                                                      depctl.d32);
4816                                                                                         }
4817                                                                                 }
4818                                                                                 goto exit_xfercompl;
4819                                                                         } else {
4820                                                                                 /* Prepare for more setup packets */
4821                                                                                 DWC_DEBUGPL
4822                                                                                     (DBG_PCDV,
4823                                                                                      "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
4824                                                                                 ep0_out_start
4825                                                                                     (core_if,
4826                                                                                      pcd);
4827                                                                         }
4828                                                                 }
4829                                                         }
4830                                                 }
4831                                                 if (core_if->dma_enable == 0
4832                                                     || pcd->ep0state !=
4833                                                     EP0_IDLE)
4834                                                         handle_ep0(pcd);
4835 exit_xfercompl:
4836                                                 DWC_DEBUGPL(DBG_PCDV,
4837                                                             "after DOEPINT=%x doepint=%x\n",
4838                                                             dwc_otg_read_dev_out_ep_intr
4839                                                             (core_if, dwc_ep),
4840                                                             doepint.d32);
4841                                         } else {
4842                                                 if (core_if->dma_desc_enable ==
4843                                                     0
4844                                                     || pcd->ep0state !=
4845                                                     EP0_IDLE)
4846                                                         handle_ep0(pcd);
4847                                         }
4848 #ifdef DWC_EN_ISOC
4849                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
4850                                         if (doepint.b.pktdrpsts == 0) {
4851                                                 /* Clear the bit in DOEPINTn for this interrupt */
4852                                                 CLEAR_OUT_EP_INTR(core_if,
4853                                                                   epnum,
4854                                                                   xfercompl);
4855                                                 complete_iso_ep(pcd, ep);
4856                                         } else {
4857
4858                                                 doepint_data_t doepint = {
4859                                                 .d32 = 0};
4860                                                 doepint.b.xfercompl = 1;
4861                                                 doepint.b.pktdrpsts = 1;
4862                                                 DWC_WRITE_REG32
4863                                                     (&core_if->
4864                                                      dev_if->out_ep_regs
4865                                                      [epnum]->doepint,
4866                                                      doepint.d32);
4867                                                 if (handle_iso_out_pkt_dropped
4868                                                     (core_if, dwc_ep)) {
4869                                                         complete_iso_ep(pcd,
4870                                                                         ep);
4871                                                 }
4872                                         }
4873 #endif /* DWC_EN_ISOC */
4874 #ifdef DWC_UTE_PER_IO
4875                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
4876                                         CLEAR_OUT_EP_INTR(core_if, epnum,
4877                                                           xfercompl);
4878                                         if (!ep->stopped)
4879                                                 complete_xiso_ep(ep);
4880 #endif /* DWC_UTE_PER_IO */
4881                                 } else {
4882                                         /* Clear the bit in DOEPINTn for this interrupt */
4883                                         CLEAR_OUT_EP_INTR(core_if, epnum,
4884                                                           xfercompl);
4885
4886                                         if (core_if->core_params->dev_out_nak) {
4887                                                 DWC_TIMER_CANCEL(pcd->
4888                                                                  core_if->ep_xfer_timer
4889                                                                  [epnum]);
4890                                                 pcd->
4891                                                     core_if->ep_xfer_info
4892                                                     [epnum].state = 0;
4893 #ifdef DEBUG
4894                                                 print_memory_payload(pcd,
4895                                                                      dwc_ep);
4896 #endif
4897                                         }
4898                                         complete_ep(ep);
4899                                 }
4900
4901                         }
4902
4903                         if (doepint.b.stsphsercvd) {
4904                                 deptsiz0_data_t deptsiz;
4905                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
4906                                 deptsiz.d32 =
4907                                     DWC_READ_REG32(&core_if->dev_if->
4908                                                    out_ep_regs[0]->doeptsiz);
4909                                 if ((core_if->dma_desc_enable)
4910                                     || (core_if->dma_enable
4911                                         && core_if->snpsid >=
4912                                         OTG_CORE_REV_3_00a)) {
4913                                         do_setup_in_status_phase(pcd);
4914                                 }
4915                         }
4916
4917                         /* Endpoint disable      */
4918                         if (doepint.b.epdisabled) {
4919
4920                                 /* Clear the bit in DOEPINTn for this interrupt */
4921                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
4922                                 if (core_if->core_params->dev_out_nak) {
4923 #ifdef DEBUG
4924                                         print_memory_payload(pcd, dwc_ep);
4925 #endif
4926                                         /* In case of timeout condition */
4927                                         if (core_if->
4928                                             ep_xfer_info[epnum].state == 2) {
4929                                                 dctl.d32 =
4930                                                     DWC_READ_REG32
4931                                                     (&core_if->dev_if->
4932                                                      dev_global_regs->dctl);
4933                                                 dctl.b.cgoutnak = 1;
4934                                                 DWC_WRITE_REG32
4935                                                     (&core_if->dev_if->dev_global_regs->dctl,
4936                                                      dctl.d32);
4937                                                 /* Unmask goutnakeff interrupt which was masked
4938                                                  * during handle nak out interrupt */
4939                                                 gintmsk.b.goutnakeff = 1;
4940                                                 DWC_MODIFY_REG32
4941                                                     (&core_if->core_global_regs->gintmsk,
4942                                                      0, gintmsk.d32);
4943
4944                                                 complete_ep(ep);
4945                                         }
4946                                 }
4947                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
4948                                         dctl_data_t dctl;
4949                                         gintmsk_data_t intr_mask = {
4950                                         .d32 = 0};
4951                                         dwc_otg_pcd_request_t *req = 0;
4952
4953                                         dctl.d32 =
4954                                             DWC_READ_REG32(&core_if->dev_if->
4955                                                            dev_global_regs->dctl);
4956                                         dctl.b.cgoutnak = 1;
4957                                         DWC_WRITE_REG32(&core_if->
4958                                                         dev_if->dev_global_regs->
4959                                                         dctl, dctl.d32);
4960
4961                                         intr_mask.d32 = 0;
4962                                         intr_mask.b.incomplisoout = 1;
4963
4964                                         /* Get any pending requests */
4965                                         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
4966                                                 req =
4967                                                     DWC_CIRCLEQ_FIRST
4968                                                     (&ep->queue);
4969                                                 if (!req) {
4970                                                         DWC_PRINTF
4971                                                             ("complete_ep 0x%p, req = NULL!\n",
4972                                                              ep);
4973                                                 } else {
4974                                                         dwc_otg_request_done(ep,
4975                                                                              req,
4976                                                                              0);
4977                                                         start_next_request(ep);
4978                                                 }
4979                                         } else {
4980                                                 DWC_PRINTF
4981                                                     ("complete_ep 0x%p, ep->queue empty!\n",
4982                                                      ep);
4983                                         }
4984                                 }
4985                         }
4986                         /* AHB Error */
4987                         if (doepint.b.ahberr) {
4988                                 DWC_ERROR("EP%d OUT AHB Error\n", epnum);
4989                                 DWC_ERROR("EP%d DEPDMA=0x%08x \n",
4990                                           epnum,
4991                                           core_if->dev_if->
4992                                           out_ep_regs[epnum]->doepdma);
4993                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
4994                         }
4995                         /* Setup Phase Done (contorl EPs) */
4996                         if (doepint.b.setup) {
4997 #ifdef DEBUG_EP0
4998                                 DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
4999                                             epnum);
5000 #endif
5001                                 CLEAR_OUT_EP_INTR(core_if, epnum, setup);
5002
5003                                 handle_ep0(pcd);
5004                         }
5005
5006                         /** OUT EP BNA Intr */
5007                         if (doepint.b.bna) {
5008                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
5009                                 if (core_if->dma_desc_enable) {
5010 #ifdef DWC_EN_ISOC
5011                                         if (dwc_ep->type ==
5012                                             DWC_OTG_EP_TYPE_ISOC) {
5013                                                 /*
5014                                                  * This checking is performed to prevent first "false" BNA
5015                                                  * handling occuring right after reconnect
5016                                                  */
5017                                                 if (dwc_ep->next_frame !=
5018                                                     0xffffffff)
5019                                                         dwc_otg_pcd_handle_iso_bna
5020                                                             (ep);
5021                                         } else
5022 #endif /* DWC_EN_ISOC */
5023                                         {
5024                                                 dwc_otg_pcd_handle_noniso_bna
5025                                                     (ep);
5026                                         }
5027                                 }
5028                         }
5029                         /* Babble Interrupt */
5030                         if (doepint.b.babble) {
5031                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
5032                                             epnum);
5033                                 handle_out_ep_babble_intr(pcd, epnum);
5034
5035                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
5036                         }
5037                         if (doepint.b.outtknepdis) {
5038                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
5039                                         disabled\n",
5040                                             epnum);
5041                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
5042                                         doepmsk_data_t doepmsk = {
5043                                         .d32 = 0};
5044                                         ep->dwc_ep.frame_num =
5045                                             core_if->frame_num;
5046                                         if (ep->dwc_ep.bInterval > 1) {
5047                                                 depctl_data_t depctl;
5048                                                 depctl.d32 =
5049                                                     DWC_READ_REG32
5050                                                     (&core_if->dev_if->
5051                                                      out_ep_regs
5052                                                      [epnum]->doepctl);
5053                                                 if (ep->dwc_ep.frame_num & 0x1) {
5054                                                         depctl.b.setd1pid = 1;
5055                                                         depctl.b.setd0pid = 0;
5056                                                 } else {
5057                                                         depctl.b.setd0pid = 1;
5058                                                         depctl.b.setd1pid = 0;
5059                                                 }
5060                                                 DWC_WRITE_REG32
5061                                                     (&core_if->dev_if->
5062                                                      out_ep_regs
5063                                                      [epnum]->doepctl,
5064                                                      depctl.d32);
5065                                         }
5066                                         start_next_request(ep);
5067                                         doepmsk.b.outtknepdis = 1;
5068                                         DWC_MODIFY_REG32(&core_if->
5069                                                          dev_if->dev_global_regs->doepmsk,
5070                                                          doepmsk.d32, 0);
5071                                 }
5072                                 CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
5073                         }
5074
5075                         /* NAK Interrutp */
5076                         if (doepint.b.nak) {
5077                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
5078                                 handle_out_ep_nak_intr(pcd, epnum);
5079
5080                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
5081                         }
5082                         /* NYET Interrutp */
5083                         if (doepint.b.nyet) {
5084                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
5085                                 handle_out_ep_nyet_intr(pcd, epnum);
5086
5087                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
5088                         }
5089                 }
5090
5091                 epnum++;
5092                 ep_intr >>= 1;
5093         }
5094
5095         return 1;
5096
5097 #undef CLEAR_OUT_EP_INTR
5098 }
5099
5100 static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr,
5101                          uint8_t frm_overrun)
5102 {
5103         int retval = 0;
5104         if (!frm_overrun && curr_fr >= trgt_fr)
5105                 retval = 1;
5106         else if (frm_overrun
5107                  && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
5108                 retval = 1;
5109         return retval;
5110 }
5111
5112 /**
5113  * Incomplete ISO IN Transfer Interrupt.
5114  * This interrupt indicates one of the following conditions occurred
5115  * while transmitting an ISOC transaction.
5116  * - Corrupted IN Token for ISOC EP.
5117  * - Packet not complete in FIFO.
5118  * The follow actions will be taken:
5119  *      -#      Determine the EP
5120  *      -#      Set incomplete flag in dwc_ep structure
5121  *      -#      Disable EP; when "Endpoint Disabled" interrupt is received
5122  *              Flush FIFO
5123  */
5124 int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
5125 {
5126         gintsts_data_t gintsts;
5127
5128 #ifdef DWC_EN_ISOC
5129         dwc_otg_dev_if_t *dev_if;
5130         deptsiz_data_t deptsiz = {
5131         .d32 = 0};
5132         depctl_data_t depctl = {
5133         .d32 = 0};
5134         dsts_data_t dsts = {
5135         .d32 = 0};
5136         dwc_ep_t *dwc_ep;
5137         int i;
5138
5139         dev_if = GET_CORE_IF(pcd)->dev_if;
5140
5141         for (i = 1; i <= dev_if->num_in_eps; ++i) {
5142                 dwc_ep = &pcd->in_ep[i].dwc_ep;
5143                 if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
5144                         deptsiz.d32 =
5145                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
5146                         depctl.d32 =
5147                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
5148
5149                         if (depctl.b.epdis && deptsiz.d32) {
5150                                 set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
5151                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
5152                                         dwc_ep->cur_pkt = 0;
5153                                         dwc_ep->proc_buf_num =
5154                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
5155
5156                                         if (dwc_ep->proc_buf_num) {
5157                                                 dwc_ep->cur_pkt_addr =
5158                                                     dwc_ep->xfer_buff1;
5159                                                 dwc_ep->cur_pkt_dma_addr =
5160                                                     dwc_ep->dma_addr1;
5161                                         } else {
5162                                                 dwc_ep->cur_pkt_addr =
5163                                                     dwc_ep->xfer_buff0;
5164                                                 dwc_ep->cur_pkt_dma_addr =
5165                                                     dwc_ep->dma_addr0;
5166                                         }
5167
5168                                 }
5169
5170                                 dsts.d32 =
5171                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
5172                                                    dev_global_regs->dsts);
5173                                 dwc_ep->next_frame = dsts.b.soffn;
5174
5175                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
5176                                                                   (pcd),
5177                                                                   dwc_ep);
5178                         }
5179                 }
5180         }
5181
5182 #else
5183         depctl_data_t depctl = {
5184         .d32 = 0};
5185         dwc_ep_t *dwc_ep;
5186         dwc_otg_dev_if_t *dev_if;
5187         int i;
5188         dev_if = GET_CORE_IF(pcd)->dev_if;
5189
5190         DWC_DEBUGPL(DBG_PCD, "Incomplete ISO IN \n");
5191
5192         for (i = 1; i <= dev_if->num_in_eps; ++i) {
5193                 dwc_ep = &pcd->in_ep[i - 1].dwc_ep;
5194                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
5195                 if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
5196                         if (drop_transfer
5197                             (dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
5198                              dwc_ep->frm_overrun)) {
5199                                 depctl.d32 =
5200                                     DWC_READ_REG32(&dev_if->
5201                                                    in_ep_regs[i]->diepctl);
5202                                 depctl.b.snak = 1;
5203                                 depctl.b.epdis = 1;
5204                                 DWC_MODIFY_REG32(&dev_if->
5205                                                  in_ep_regs[i]->diepctl,
5206                                                  depctl.d32, depctl.d32);
5207                         }
5208                 }
5209         }
5210
5211         /*intr_mask.b.incomplisoin = 1;
5212            DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
5213            intr_mask.d32, 0);    */
5214 #endif /* DWC_EN_ISOC */
5215
5216         /* Clear interrupt */
5217         gintsts.d32 = 0;
5218         gintsts.b.incomplisoin = 1;
5219         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
5220                         gintsts.d32);
5221
5222         return 1;
5223 }
5224
5225 /**
5226  * Incomplete ISO OUT Transfer Interrupt.
5227  *
5228  * This interrupt indicates that the core has dropped an ISO OUT
5229  * packet. The following conditions can be the cause:
5230  * - FIFO Full, the entire packet would not fit in the FIFO.
5231  * - CRC Error
5232  * - Corrupted Token
5233  * The follow actions will be taken:
5234  *      -#      Determine the EP
5235  *      -#      Set incomplete flag in dwc_ep structure
5236  *      -#      Read any data from the FIFO
5237  *      -#      Disable EP. When "Endpoint Disabled" interrupt is received
5238  *              re-enable EP.
5239  */
5240 int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
5241 {
5242
5243         gintsts_data_t gintsts;
5244
5245 #ifdef DWC_EN_ISOC
5246         dwc_otg_dev_if_t *dev_if;
5247         deptsiz_data_t deptsiz = {
5248         .d32 = 0};
5249         depctl_data_t depctl = {
5250         .d32 = 0};
5251         dsts_data_t dsts = {
5252         .d32 = 0};
5253         dwc_ep_t *dwc_ep;
5254         int i;
5255
5256         dev_if = GET_CORE_IF(pcd)->dev_if;
5257
5258         for (i = 1; i <= dev_if->num_out_eps; ++i) {
5259                 dwc_ep = &pcd->in_ep[i].dwc_ep;
5260                 if (pcd->out_ep[i].dwc_ep.active &&
5261                     pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
5262                         deptsiz.d32 =
5263                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
5264                         depctl.d32 =
5265                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
5266
5267                         if (depctl.b.epdis && deptsiz.d32) {
5268                                 set_current_pkt_info(GET_CORE_IF(pcd),
5269                                                      &pcd->out_ep[i].dwc_ep);
5270                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
5271                                         dwc_ep->cur_pkt = 0;
5272                                         dwc_ep->proc_buf_num =
5273                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
5274
5275                                         if (dwc_ep->proc_buf_num) {
5276                                                 dwc_ep->cur_pkt_addr =
5277                                                     dwc_ep->xfer_buff1;
5278                                                 dwc_ep->cur_pkt_dma_addr =
5279                                                     dwc_ep->dma_addr1;
5280                                         } else {
5281                                                 dwc_ep->cur_pkt_addr =
5282                                                     dwc_ep->xfer_buff0;
5283                                                 dwc_ep->cur_pkt_dma_addr =
5284                                                     dwc_ep->dma_addr0;
5285                                         }
5286
5287                                 }
5288
5289                                 dsts.d32 =
5290                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
5291                                                    dev_global_regs->dsts);
5292                                 dwc_ep->next_frame = dsts.b.soffn;
5293
5294                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
5295                                                                   (pcd),
5296                                                                   dwc_ep);
5297                         }
5298                 }
5299         }
5300 #else
5301         /** @todo implement ISR */
5302         gintmsk_data_t intr_mask = {
5303         .d32 = 0};
5304         dwc_otg_core_if_t *core_if;
5305         deptsiz_data_t deptsiz = {
5306         .d32 = 0};
5307         depctl_data_t depctl = {
5308         .d32 = 0};
5309         dctl_data_t dctl = {
5310         .d32 = 0};
5311         dwc_ep_t *dwc_ep = NULL;
5312         int i;
5313         core_if = GET_CORE_IF(pcd);
5314
5315         for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
5316                 dwc_ep = &pcd->out_ep[i].dwc_ep;
5317                 depctl.d32 =
5318                     DWC_READ_REG32(&core_if->dev_if->
5319                                    out_ep_regs[dwc_ep->num]->doepctl);
5320                 if (depctl.b.epena
5321                     && depctl.b.dpid == (core_if->frame_num & 0x1)) {
5322                         core_if->dev_if->isoc_ep = dwc_ep;
5323                         deptsiz.d32 =
5324                             DWC_READ_REG32(&core_if->
5325                                            dev_if->out_ep_regs[dwc_ep->num]->
5326                                            doeptsiz);
5327                         break;
5328                 }
5329         }
5330         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
5331         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
5332         intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
5333
5334         if (!intr_mask.b.goutnakeff) {
5335                 /* Unmask it */
5336                 intr_mask.b.goutnakeff = 1;
5337                 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk,
5338                                 intr_mask.d32);
5339         }
5340         if (!gintsts.b.goutnakeff) {
5341                 dctl.b.sgoutnak = 1;
5342         }
5343         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
5344
5345         depctl.d32 =
5346             DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
5347         if (depctl.b.epena) {
5348                 depctl.b.epdis = 1;
5349                 depctl.b.snak = 1;
5350         }
5351         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
5352                         depctl.d32);
5353
5354         intr_mask.d32 = 0;
5355         intr_mask.b.incomplisoout = 1;
5356
5357 #endif /* DWC_EN_ISOC */
5358
5359         /* Clear interrupt */
5360         gintsts.d32 = 0;
5361         gintsts.b.incomplisoout = 1;
5362         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
5363                         gintsts.d32);
5364
5365         return 1;
5366 }
5367
5368 /**
5369  * This function handles the Global IN NAK Effective interrupt.
5370  *
5371  */
5372 int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
5373 {
5374         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
5375         depctl_data_t diepctl = {
5376         .d32 = 0};
5377         gintmsk_data_t intr_mask = {
5378         .d32 = 0};
5379         gintsts_data_t gintsts;
5380         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
5381         int i;
5382
5383         DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
5384
5385         /* Disable all active IN EPs */
5386         for (i = 0; i <= dev_if->num_in_eps; i++) {
5387                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
5388                 if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
5389                         if (core_if->start_predict > 0)
5390                                 core_if->start_predict++;
5391                         diepctl.b.epdis = 1;
5392                         diepctl.b.snak = 1;
5393                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl,
5394                                         diepctl.d32);
5395                 }
5396         }
5397
5398         /* Disable the Global IN NAK Effective Interrupt */
5399         intr_mask.b.ginnakeff = 1;
5400         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
5401                          intr_mask.d32, 0);
5402
5403         /* Clear interrupt */
5404         gintsts.d32 = 0;
5405         gintsts.b.ginnakeff = 1;
5406         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
5407                         gintsts.d32);
5408
5409         return 1;
5410 }
5411
5412 /**
5413  * OUT NAK Effective.
5414  *
5415  */
5416 int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
5417 {
5418         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
5419         gintmsk_data_t intr_mask = {
5420         .d32 = 0};
5421         gintsts_data_t gintsts;
5422         depctl_data_t doepctl;
5423         int i;
5424
5425         /* Disable the Global OUT NAK Effective Interrupt */
5426         intr_mask.b.goutnakeff = 1;
5427         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
5428                          intr_mask.d32, 0);
5429
5430         /* If DEV OUT NAK enabled */
5431         if (pcd->core_if->core_params->dev_out_nak) {
5432                 /* Run over all out endpoints to determine the ep number on
5433                  * which the timeout has happened
5434                  */
5435                 for (i = 0; i <= dev_if->num_out_eps; i++) {
5436                         if (pcd->core_if->ep_xfer_info[i].state == 2)
5437                                 break;
5438                 }
5439                 if (i > dev_if->num_out_eps) {
5440                         dctl_data_t dctl;
5441                         dctl.d32 =
5442                             DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
5443                         dctl.b.cgoutnak = 1;
5444                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
5445                                         dctl.d32);
5446                         goto out;
5447                 }
5448
5449                 /* Disable the endpoint */
5450                 doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
5451                 if (doepctl.b.epena) {
5452                         doepctl.b.epdis = 1;
5453                         doepctl.b.snak = 1;
5454                 }
5455                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
5456                 return 1;
5457         }
5458         /* We come here from Incomplete ISO OUT handler */
5459         if (dev_if->isoc_ep) {
5460                 dwc_ep_t *dwc_ep = (dwc_ep_t *) dev_if->isoc_ep;
5461                 uint32_t epnum = dwc_ep->num;
5462                 doepint_data_t doepint;
5463                 doepint.d32 =
5464                     DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
5465                 dev_if->isoc_ep = NULL;
5466                 doepctl.d32 =
5467                     DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
5468                 DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
5469                 if (doepctl.b.epena) {
5470                         doepctl.b.epdis = 1;
5471                         doepctl.b.snak = 1;
5472                 }
5473                 DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
5474                                 doepctl.d32);
5475                 return 1;
5476         } else
5477                 DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
5478                            "Global OUT NAK Effective\n");
5479
5480 out:
5481         /* Clear interrupt */
5482         gintsts.d32 = 0;
5483         gintsts.b.goutnakeff = 1;
5484         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
5485                         gintsts.d32);
5486
5487         return 1;
5488 }
5489
5490 /**
5491  * PCD interrupt handler.
5492  *
5493  * The PCD handles the device interrupts.  Many conditions can cause a
5494  * device interrupt. When an interrupt occurs, the device interrupt
5495  * service routine determines the cause of the interrupt and
5496  * dispatches handling to the appropriate function. These interrupt
5497  * handling functions are described below.
5498  *
5499  * All interrupt registers are processed from LSB to MSB.
5500  *
5501  */
5502 int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
5503 {
5504         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
5505 #ifdef VERBOSE
5506         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5507 #endif
5508         gintsts_data_t gintr_status;
5509         int32_t retval = 0;
5510
5511         if (dwc_otg_check_haps_status(core_if) == -1) {
5512                 DWC_WARN("HAPS is disconnected");
5513                 return retval;
5514         }
5515
5516         /* Exit from ISR if core is hibernated */
5517         if (core_if->hibernation_suspend == 1) {
5518                 return retval;
5519         }
5520 #ifdef VERBOSE
5521         DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
5522                     __func__,
5523                     DWC_READ_REG32(&global_regs->gintsts),
5524                     DWC_READ_REG32(&global_regs->gintmsk));
5525 #endif
5526
5527         if (dwc_otg_is_device_mode(core_if)) {
5528                 DWC_SPINLOCK(pcd->lock);
5529 #ifdef VERBOSE
5530                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
5531                             __func__,
5532                             DWC_READ_REG32(&global_regs->gintsts),
5533                             DWC_READ_REG32(&global_regs->gintmsk));
5534 #endif
5535
5536                 gintr_status.d32 = dwc_otg_read_core_intr(core_if);
5537
5538                 DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
5539                             __func__, gintr_status.d32);
5540
5541                 if (gintr_status.b.sofintr) {
5542                         retval |= dwc_otg_pcd_handle_sof_intr(pcd);
5543                 }
5544                 if (gintr_status.b.rxstsqlvl) {
5545                         retval |=
5546                             dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
5547                 }
5548                 if (gintr_status.b.nptxfempty) {
5549                         retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
5550                 }
5551                 if (gintr_status.b.goutnakeff) {
5552                         retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
5553                 }
5554                 if (gintr_status.b.i2cintr) {
5555                         retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
5556                 }
5557                 if (gintr_status.b.erlysuspend) {
5558                         retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
5559                 }
5560                 if (gintr_status.b.usbreset) {
5561                         retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
5562                         pcd->conn_status = -1;
5563                 }
5564                 if (gintr_status.b.enumdone) {
5565                         retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
5566                 }
5567                 if (gintr_status.b.isooutdrop) {
5568                         retval |=
5569                             dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
5570                             (pcd);
5571                 }
5572                 if (gintr_status.b.eopframe) {
5573                         retval |=
5574                             dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
5575                 }
5576                 if (gintr_status.b.inepint) {
5577                         if (!core_if->multiproc_int_enable) {
5578                                 retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
5579                         }
5580                 }
5581                 if (gintr_status.b.outepintr) {
5582                         if (!core_if->multiproc_int_enable) {
5583                                 retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
5584                         }
5585                 }
5586                 if (gintr_status.b.epmismatch) {
5587                         retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
5588                 }
5589                 if (gintr_status.b.fetsusp) {
5590                         retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
5591                 }
5592                 if (gintr_status.b.ginnakeff) {
5593                         retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
5594                 }
5595                 if (gintr_status.b.incomplisoin) {
5596                         retval |=
5597                             dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
5598                 }
5599                 if (gintr_status.b.incomplisoout) {
5600                         retval |=
5601                             dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
5602                 }
5603
5604                 /* In MPI mode Device Endpoints interrupts are asserted
5605                  * without setting outepintr and inepint bits set, so these
5606                  * Interrupt handlers are called without checking these bit-fields
5607                  */
5608                 if (core_if->multiproc_int_enable) {
5609                         retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
5610                         retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
5611                 }
5612 #ifdef VERBOSE
5613                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
5614                             DWC_READ_REG32(&global_regs->gintsts));
5615 #endif
5616                 DWC_SPINUNLOCK(pcd->lock);
5617         }
5618         return retval;
5619 }
5620
5621 #endif /* DWC_HOST_ONLY */