1 /*==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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14 * redistribute this Software in source and binary forms, with or without
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file contains Descriptor DMA support implementation for host mode.
39 #include "dwc_otg_hcd.h"
40 #include "dwc_otg_regs.h"
42 static inline uint8_t frame_list_idx(uint16_t frame)
45 ret = frame & (MAX_FRLIST_EN_NUM - 1);
49 static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc,
54 DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
55 MAX_DMA_DESC_NUM_GENERIC) - 1);
58 static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc,
63 DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
64 MAX_DMA_DESC_NUM_GENERIC) - 1);
67 static inline uint16_t max_desc_num(dwc_otg_qh_t *qh)
69 return (((qh->ep_type == UE_ISOCHRONOUS)
70 && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
71 ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
74 static inline uint16_t frame_incr_val(dwc_otg_qh_t *qh)
76 return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
77 ? ((qh->interval + 8 - 1) / 8)
81 static int desc_list_alloc(dwc_otg_qh_t *qh)
85 qh->desc_list = (dwc_otg_host_dma_desc_t *)
86 DWC_DMA_ALLOC_ATOMIC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
90 retval = -DWC_E_NO_MEMORY;
91 DWC_ERROR("%s: DMA descriptor list allocation failed\n",
96 dwc_memset(qh->desc_list, 0x00,
97 sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
100 (uint32_t *) DWC_ALLOC_ATOMIC(sizeof(uint32_t) * max_desc_num(qh));
103 retval = -DWC_E_NO_MEMORY;
105 ("%s: Failed to allocate array for descriptors' size actual values\n",
113 static void desc_list_free(dwc_otg_qh_t *qh)
116 DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
118 qh->desc_list = NULL;
122 DWC_FREE(qh->n_bytes);
127 static int frame_list_alloc(dwc_otg_hcd_t *hcd)
133 hcd->frame_list = DWC_DMA_ALLOC_ATOMIC(4 * MAX_FRLIST_EN_NUM,
134 &hcd->frame_list_dma);
135 if (!hcd->frame_list) {
136 retval = -DWC_E_NO_MEMORY;
137 DWC_ERROR("%s: Frame List allocation failed\n", __func__);
140 dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
145 static void frame_list_free(dwc_otg_hcd_t *hcd)
147 if (!hcd->frame_list)
150 DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list,
151 hcd->frame_list_dma);
152 hcd->frame_list = NULL;
155 static void per_sched_enable(dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
161 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
163 if (hcfg.b.perschedena) {
164 /* already enabled */
168 DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
169 hcd->frame_list_dma);
171 switch (fr_list_en) {
188 hcfg.b.perschedena = 1;
190 DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
191 DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg,
196 static void per_sched_disable(dwc_otg_hcd_t *hcd)
201 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
203 if (!hcfg.b.perschedena) {
204 /* already disabled */
207 hcfg.b.perschedena = 0;
209 DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
210 DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg,
215 * Activates/Deactivates FrameList entries for the channel
216 * based on endpoint servicing period.
218 void update_frame_list(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
224 DWC_ERROR("qh->channel = %p", qh->channel);
229 DWC_ERROR("------hcd = %p", hcd);
233 if (!hcd->frame_list) {
234 DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
239 inc = frame_incr_val(qh);
240 if (qh->ep_type == UE_ISOCHRONOUS)
241 i = frame_list_idx(qh->sched_frame);
248 hcd->frame_list[j] |= (1 << hc->hc_num);
250 hcd->frame_list[j] &= ~(1 << hc->hc_num);
251 j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
256 if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
258 /* TODO - check this */
259 inc = (8 + qh->interval - 1) / qh->interval;
260 for (i = 0; i < inc; i++) {
262 j = j << qh->interval;
270 void dump_frame_list(dwc_otg_hcd_t *hcd)
273 DWC_PRINTF("--FRAME LIST (hex) --\n");
274 for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
275 DWC_PRINTF("%x\t", hcd->frame_list[i]);
279 DWC_PRINTF("\n----\n");
284 static void release_channel_ddma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
286 dwc_hc_t *hc = qh->channel;
287 if (dwc_qh_is_non_per(qh))
288 hcd->non_periodic_channels--;
290 update_frame_list(hcd, qh, 0);
293 * The condition is added to prevent double cleanup try in case of device
294 * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
297 dwc_otg_hc_cleanup(hcd->core_if, hc);
298 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
306 dwc_memset(qh->desc_list, 0x00,
307 sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
312 * Initializes a QH structure's Descriptor DMA related members.
313 * Allocates memory for descriptor list.
314 * On first periodic QH, allocates memory for FrameList
315 * and enables periodic scheduling.
317 * @param hcd The HCD state structure for the DWC OTG controller.
318 * @param qh The QH to init.
320 * @return 0 if successful, negative error code otherwise.
322 int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
328 ("SPLIT Transfers are not supported in Descriptor DMA.\n");
332 retval = desc_list_alloc(qh);
335 && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
336 if (!hcd->frame_list) {
337 retval = frame_list_alloc(hcd);
338 /* Enable periodic schedule on first periodic QH */
340 per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
350 * Frees descriptor list memory associated with the QH.
351 * If QH is periodic and the last, frees FrameList memory
352 * and disables periodic scheduling.
354 * @param hcd The HCD state structure for the DWC OTG controller.
355 * @param qh The QH to init.
357 void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
362 * Channel still assigned due to some reasons.
363 * Seen on Isoc URB dequeue. Channel halted but no subsequent
364 * ChHalted interrupt to release the channel. Afterwards
365 * when it comes here from endpoint disable routine
366 * channel remains assigned.
369 release_channel_ddma(hcd, qh);
371 if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
372 && !hcd->periodic_channels && hcd->frame_list) {
374 per_sched_disable(hcd);
375 frame_list_free(hcd);
379 static uint8_t frame_to_desc_idx(dwc_otg_qh_t *qh, uint16_t frame_idx)
383 if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
385 * Descriptor set(8 descriptors) index
386 * which is 8-aligned.
388 ret = (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
390 ret = frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1);
397 * Determine starting frame for Isochronous transfer.
398 * Few frames skipped to prevent race condition with HC.
400 static uint8_t calc_starting_frame(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh,
401 uint8_t *skip_frames)
404 hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
406 /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
409 * skip_frames is used to limit activated descriptors number
410 * to avoid the situation when HC services the last activated
411 * descriptor firstly.
413 * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
414 * corresponding to curr_frame+1, the descriptor corresponding to frame 2
415 * will be fetched. If the number of descriptors is max=64 (or greather) the
416 * list will be fully programmed with Active descriptors and it is possible
417 * case(rare) that the latest descriptor(considering rollback) corresponding
418 * to frame 2 will be serviced first. HS case is more probable because, in fact,
419 * up to 11 uframes(16 in the code) may be skipped.
421 if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
423 * Consider uframe counter also, to start xfer asap.
424 * If half of the frame elapsed skip 2 frames otherwise
426 * Starting descriptor index must be 8-aligned, so
427 * if the current frame is near to complete the next one
428 * is skipped as well.
431 if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
432 *skip_frames = 2 * 8;
434 dwc_frame_num_inc(hcd->frame_number, *skip_frames);
436 *skip_frames = 1 * 8;
438 dwc_frame_num_inc(hcd->frame_number, *skip_frames);
441 frame = dwc_full_frame_num(frame);
444 * Two frames are skipped for FS - the current and the next.
445 * But for descriptor programming, 1 frame(descriptor) is enough,
449 frame = dwc_frame_num_inc(hcd->frame_number, 2);
456 * Calculate initial descriptor index for isochronous transfer
457 * based on scheduled frame.
459 static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
461 uint16_t frame = 0, fr_idx, fr_idx_tmp;
462 uint8_t skip_frames = 0;
464 * With current ISOC processing algorithm the channel is being
465 * released when no more QTDs in the list(qh->ntd == 0).
466 * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
468 * So qh->channel != NULL branch is not used and just not removed from the
469 * source file. It is required for another possible approach which is,
470 * do not disable and release the channel when ISOC session completed,
471 * just move QH to inactive schedule until new QTD arrives.
472 * On new QTD, the QH moved back to 'ready' schedule,
473 * starting frame and therefore starting desc_index are recalculated.
474 * In this case channel is released only on ep_disable.
477 /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
479 frame = calc_starting_frame(hcd, qh, &skip_frames);
481 * Calculate initial descriptor index based on FrameList current bitmap
482 * and servicing period.
484 fr_idx_tmp = frame_list_idx(frame);
486 (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
488 % frame_incr_val(qh);
489 fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
491 qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
492 fr_idx = frame_list_idx(qh->sched_frame);
495 qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
500 #define ISOC_URB_GIVEBACK_ASAP
502 #define MAX_ISOC_XFER_SIZE_FS 1023
503 #define MAX_ISOC_XFER_SIZE_HS 3072
504 #define DESCNUM_THRESHOLD 4
506 static void init_isoc_dma_desc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh,
509 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
511 dwc_otg_host_dma_desc_t *dma_desc;
512 uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
518 ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
519 if (skip_frames && !qh->channel)
520 ntd_max = ntd_max - skip_frames / qh->interval;
524 DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
525 MAX_ISOC_XFER_SIZE_FS;
527 DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
528 while ((qh->ntd < ntd_max)
529 && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) {
531 dma_desc = &qh->desc_list[idx];
532 dwc_memset(dma_desc, 0x00,
533 sizeof(dwc_otg_host_dma_desc_t));
536 &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
538 if (frame_desc->length > max_xfer_size)
539 qh->n_bytes[idx] = max_xfer_size;
541 qh->n_bytes[idx] = frame_desc->length;
542 dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
543 dma_desc->status.b_isoc.a = 1;
544 dma_desc->status.b_isoc.sts = 0;
546 dma_desc->buf = qtd->urb->dma + frame_desc->offset;
550 qtd->isoc_frame_index_last++;
552 #ifdef ISOC_URB_GIVEBACK_ASAP
554 * Set IOC for each descriptor corresponding to the
555 * last frame of the URB.
557 if (qtd->isoc_frame_index_last ==
558 qtd->urb->packet_count)
559 dma_desc->status.b_isoc.ioc = 1;
562 idx = desclist_idx_inc(idx, inc, qh->dev_speed);
571 #ifdef ISOC_URB_GIVEBACK_ASAP
572 /* Set IOC for the last descriptor if descriptor list is full */
573 if (qh->ntd == ntd_max) {
574 idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
575 qh->desc_list[idx].status.b_isoc.ioc = 1;
579 * Set IOC bit only for one descriptor.
580 * Always try to be ahead of HW processing,
581 * i.e. on IOC generation driver activates next descriptors but
582 * core continues to process descriptors followed the one with IOC set.
585 if (n_desc > DESCNUM_THRESHOLD) {
587 * Move IOC "up". Required even if there is only one QTD
588 * in the list, cause QTDs migth continue to be queued,
589 * but during the activation it was only one queued.
590 * Actually more than one QTD might be in the list if this function called
591 * from XferCompletion - QTDs was queued during HW processing of the previous
595 dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2),
599 * Set the IOC for the latest descriptor
600 * if either number of descriptor is not greather than threshold
601 * or no more new descriptors activated.
603 idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
606 qh->desc_list[idx].status.b_isoc.ioc = 1;
610 static void init_non_isoc_dma_desc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
614 dwc_otg_host_dma_desc_t *dma_desc;
616 int num_packets, len, n_desc = 0;
621 * Start with hc->xfer_buff initialized in
622 * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
623 * this pointer re-assigned to the buffer of the currently processed QTD.
624 * For non-SG request there is always one QTD active.
627 DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
630 /* SG request - more than 1 QTDs */
632 (uint8_t *) qtd->urb->dma + qtd->urb->actual_length;
634 qtd->urb->length - qtd->urb->actual_length;
640 dma_desc = &qh->desc_list[n_desc];
643 if (len > MAX_DMA_DESC_SIZE)
644 len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
649 (len + hc->max_packet -
652 /* Need 1 packet for transfer length of 0. */
655 /* Always program an integral # of max packets for IN transfers. */
656 len = num_packets*hc->max_packet;
659 dma_desc->status.b.n_bytes = len;
661 qh->n_bytes[n_desc] = len;
663 if ((qh->ep_type == UE_CONTROL)
664 && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
665 dma_desc->status.b.sup = 1; /* Setup Packet */
667 dma_desc->status.b.a = 1; /* Active descriptor */
668 dma_desc->status.b.sts = 0;
671 ((unsigned long)hc->xfer_buff & 0xffffffff);
674 * Last descriptor(or single) of IN transfer
675 * with actual size less than MaxPacket.
677 if (len > hc->xfer_len) {
680 hc->xfer_buff += len;
686 } while ((hc->xfer_len > 0)
687 && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
691 if (qh->ep_type == UE_CONTROL)
694 if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
699 /* Request Transfer Complete interrupt for the last descriptor */
700 qh->desc_list[n_desc - 1].status.b.ioc = 1;
701 /* End of List indicator */
702 qh->desc_list[n_desc - 1].status.b.eol = 1;
709 * For Control and Bulk endpoints initializes descriptor list
710 * and starts the transfer.
712 * For Interrupt and Isochronous endpoints initializes descriptor list
713 * then updates FrameList, marking appropriate entries as active.
714 * In case of Isochronous, the starting descriptor index is calculated based
715 * on the scheduled frame, but only on the first transfer descriptor within a session.
716 * Then starts the transfer via enabling the channel.
717 * For Isochronous endpoint the channel is not halted on XferComplete
718 * interrupt so remains assigned to the endpoint(QH) until session is done.
720 * @param hcd The HCD state structure for the DWC OTG controller.
721 * @param qh The QH to init.
723 * @return 0 if successful, negative error code otherwise.
725 void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
727 /* Channel is already assigned */
728 dwc_hc_t *hc = qh->channel;
729 uint8_t skip_frames = 0;
731 switch (hc->ep_type) {
732 case DWC_OTG_EP_TYPE_CONTROL:
733 case DWC_OTG_EP_TYPE_BULK:
734 init_non_isoc_dma_desc(hcd, qh);
736 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
738 case DWC_OTG_EP_TYPE_INTR:
739 init_non_isoc_dma_desc(hcd, qh);
741 update_frame_list(hcd, qh, 1);
742 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
744 case DWC_OTG_EP_TYPE_ISOC:
747 skip_frames = recalc_initial_desc_idx(hcd, qh);
749 init_isoc_dma_desc(hcd, qh, skip_frames);
751 if (!hc->xfer_started) {
753 update_frame_list(hcd, qh, 1);
756 * Always set to max, instead of actual size.
757 * Otherwise ntd will be changed with
758 * channel being enabled. Not recommended.
761 hc->ntd = max_desc_num(qh);
762 /* Enable channel only once for ISOC */
763 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
773 static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd,
775 dwc_otg_hc_regs_t *hc_regs,
776 dwc_otg_halt_status_e halt_status)
778 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
779 dwc_otg_qtd_t *qtd, *qtd_tmp;
781 dwc_otg_host_dma_desc_t *dma_desc;
782 uint16_t idx, remain;
788 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
789 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list,
793 } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
794 (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
796 * Channel is halted in these error cases.
797 * Considered as serious issues.
798 * Complete all URBs marking all frames as failed,
799 * irrespective whether some of the descriptors(frames) succeeded or no.
800 * Pass error code to completion routine as well, to
801 * update urb->status, some of class drivers might use it to stop
802 * queing transfer requests.
804 int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
808 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list,
810 for (idx = 0; idx < qtd->urb->packet_count; idx++) {
811 frame_desc = &qtd->urb->iso_descs[idx];
812 frame_desc->status = err;
814 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
815 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
820 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list,
823 if (!qtd->in_process)
830 dma_desc = &qh->desc_list[idx];
833 &qtd->urb->iso_descs[qtd->isoc_frame_index];
835 hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
837 if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
839 * XactError or, unable to complete all the transactions
840 * in the scheduled micro-frame/frame,
841 * both indicated by DMA_DESC_STS_PKTERR.
843 qtd->urb->error_count++;
844 frame_desc->actual_length =
845 qh->n_bytes[idx] - remain;
846 frame_desc->status = -DWC_E_PROTOCOL;
850 frame_desc->actual_length =
851 qh->n_bytes[idx] - remain;
852 frame_desc->status = 0;
855 if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
857 * urb->status is not used for isoc transfers here.
858 * The individual frame_desc status are used instead.
861 hcd->fops->complete(hcd, qtd->urb->priv,
863 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
866 * This check is necessary because urb_dequeue can be called
867 * from urb complete callback(sound driver example).
868 * All pending URBs are dequeued there, so no need for
869 * further processing.
871 if (hc->halt_status ==
872 DWC_OTG_HC_XFER_URB_DEQUEUE) {
882 /* Stop if IOC requested descriptor reached */
883 if (dma_desc->status.b_isoc.ioc) {
885 desclist_idx_inc(idx, qh->interval,
890 idx = desclist_idx_inc(idx, qh->interval, hc->speed);
894 } while (idx != qh->td_first);
900 uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t *hcd,
903 dwc_otg_host_dma_desc_t *dma_desc,
904 dwc_otg_halt_status_e halt_status,
905 uint32_t n_bytes, uint8_t *xfer_done)
908 uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
909 dwc_otg_hcd_urb_t *urb = qtd->urb;
911 if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
912 urb->status = -DWC_E_IO;
915 if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
916 switch (halt_status) {
917 case DWC_OTG_HC_XFER_STALL:
918 urb->status = -DWC_E_PIPE;
920 case DWC_OTG_HC_XFER_BABBLE_ERR:
921 urb->status = -DWC_E_OVERFLOW;
923 case DWC_OTG_HC_XFER_XACT_ERR:
924 urb->status = -DWC_E_PROTOCOL;
928 ("%s: Unhandled descriptor error status (%d)\n",
929 __func__, halt_status);
935 if (dma_desc->status.b.a == 1) {
936 DWC_DEBUGPL(DBG_HCDV,
937 "Active descriptor encountered on channel %d\n",
942 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
943 if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
944 urb->actual_length += n_bytes - remain;
945 if (remain || urb->actual_length == urb->length) {
947 * For Control Data stage do not set urb->status=0 to prevent
948 * URB callback. Set it when Status phase done. See below.
953 } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
957 /* No handling for SETUP stage */
960 urb->actual_length += n_bytes - remain;
961 if (remain || urb->actual_length == urb->length) {
970 static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t *hcd,
972 dwc_otg_hc_regs_t *hc_regs,
973 dwc_otg_halt_status_e halt_status)
975 dwc_otg_hcd_urb_t *urb = NULL;
976 dwc_otg_qtd_t *qtd, *qtd_tmp;
978 dwc_otg_host_dma_desc_t *dma_desc;
979 uint32_t n_bytes, n_desc, i, qtd_n_desc;
980 uint8_t failed = 0, xfer_done;
985 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
986 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list,
993 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
999 qtd_n_desc = qtd->n_desc;
1000 for (i = 0; i < qtd_n_desc; i++) {
1001 dma_desc = &qh->desc_list[n_desc];
1003 n_bytes = qh->n_bytes[n_desc];
1006 update_non_isoc_urb_state_ddma(hcd, hc, qtd,
1008 halt_status, n_bytes,
1013 && (urb->status != -DWC_E_IN_PROGRESS))) {
1015 hcd->fops->complete(hcd, urb->priv, urb,
1017 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
1021 } else if (qh->ep_type == UE_CONTROL) {
1022 if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
1023 if (urb->length > 0) {
1024 qtd->control_phase =
1025 DWC_OTG_CONTROL_DATA;
1027 qtd->control_phase =
1028 DWC_OTG_CONTROL_STATUS;
1030 DWC_DEBUGPL(DBG_HCDV,
1031 " Control setup transaction done\n");
1032 } else if (qtd->control_phase ==
1033 DWC_OTG_CONTROL_DATA) {
1035 qtd->control_phase =
1036 DWC_OTG_CONTROL_STATUS;
1037 DWC_DEBUGPL(DBG_HCDV,
1038 " Control data transfer done\n");
1039 } else if (i + 1 == qtd->n_desc) {
1041 * Last descriptor for Control data stage which is
1042 * not completed yet.
1044 dwc_otg_hcd_save_data_toggle(hc,
1058 if (qh->ep_type != UE_CONTROL) {
1060 * Resetting the data toggle for bulk
1061 * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
1063 if (halt_status == DWC_OTG_HC_XFER_STALL)
1064 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
1066 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1069 if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
1071 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1074 * Got a NYET on the last transaction of the transfer. It
1075 * means that the endpoint should be in the PING state at the
1076 * beginning of the next transfer.
1079 clear_hc_int(hc_regs, nyet);
1087 * This function is called from interrupt handlers.
1088 * Scans the descriptor list, updates URB's status and
1089 * calls completion routine for the URB if it's done.
1090 * Releases the channel to be used by other transfers.
1091 * In case of Isochronous endpoint the channel is not halted until
1092 * the end of the session, i.e. QTD list is empty.
1093 * If periodic channel released the FrameList is updated accordingly.
1095 * Calls transaction selection routines to activate pending transfers.
1097 * @param hcd The HCD state structure for the DWC OTG controller.
1098 * @param hc Host channel, the transfer is completed on.
1099 * @param hc_regs Host channel registers.
1100 * @param halt_status Reason the channel is being halted,
1101 * or just XferComplete for isochronous transfer
1103 void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd,
1105 dwc_otg_hc_regs_t *hc_regs,
1106 dwc_otg_halt_status_e halt_status)
1108 uint8_t continue_isoc_xfer = 0;
1109 dwc_otg_transaction_type_e tr_type;
1110 dwc_otg_qh_t *qh = hc->qh;
1112 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1114 complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
1116 /* Release the channel if halted or session completed */
1117 if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
1118 DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
1120 /* Halt the channel if session completed */
1121 if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
1122 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
1125 release_channel_ddma(hcd, qh);
1126 dwc_otg_hcd_qh_remove(hcd, qh);
1128 /* Keep in assigned schedule to continue transfer */
1129 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1130 &qh->qh_list_entry);
1131 continue_isoc_xfer = 1;
1134 /** @todo Consider the case when period exceeds FrameList size.
1135 * Frame Rollover interrupt should be used.
1138 /* Scan descriptor list to complete the URB(s), then release the channel */
1139 complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
1141 release_channel_ddma(hcd, qh);
1142 dwc_otg_hcd_qh_remove(hcd, qh);
1144 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
1145 /* Add back to inactive non-periodic schedule on normal completion */
1146 dwc_otg_hcd_qh_add(hcd, qh);
1150 tr_type = dwc_otg_hcd_select_transactions(hcd);
1151 if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
1152 if (continue_isoc_xfer) {
1153 if (tr_type == DWC_OTG_TRANSACTION_NONE) {
1154 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
1155 } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
1156 tr_type = DWC_OTG_TRANSACTION_ALL;
1159 dwc_otg_hcd_queue_transactions(hcd, tr_type);
1163 #endif /* DWC_DEVICE_ONLY */