1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
90 .name = "rk3036-usb20otg",
91 .pdata = &usb20otg_pdata_rk3036,
94 .name = "rk3126-usb20otg",
95 .pdata = &usb20otg_pdata_rk3126,
101 #ifdef CONFIG_USB20_HOST
102 static struct usb20host_pdata_id usb20host_pdata[] = {
104 .name = "rk3188-usb20host",
105 .pdata = &usb20host_pdata_rk3188,
108 .name = "rk3288-usb20host",
109 .pdata = &usb20host_pdata_rk3288,
112 .name = "rk3036-usb20host",
113 .pdata = &usb20host_pdata_rk3036,
116 .name = "rk3126-usb20host",
117 .pdata = &usb20host_pdata_rk3126,
123 #ifdef CONFIG_RK_USB_UART
124 static u32 usb_to_uart_status;
126 /*-------------------------------------------------------------------------*/
127 /* Encapsulate the module parameter settings */
129 struct dwc_otg_driver_module_params {
133 int32_t dma_desc_enable;
134 int32_t dma_burst_size;
136 int32_t host_support_fs_ls_low_power;
137 int32_t host_ls_low_power_phy_clk;
138 int32_t enable_dynamic_fifo;
139 int32_t data_fifo_size;
140 int32_t dev_rx_fifo_size;
141 int32_t dev_nperio_tx_fifo_size;
142 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
143 int32_t host_rx_fifo_size;
144 int32_t host_nperio_tx_fifo_size;
145 int32_t host_perio_tx_fifo_size;
146 int32_t max_transfer_size;
147 int32_t max_packet_count;
148 int32_t host_channels;
149 int32_t dev_endpoints;
151 int32_t phy_utmi_width;
152 int32_t phy_ulpi_ddr;
153 int32_t phy_ulpi_ext_vbus;
157 int32_t en_multiple_tx_fifo;
158 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
160 uint32_t tx_thr_length;
161 uint32_t rx_thr_length;
166 int32_t baseline_besl;
169 int32_t ahb_thr_ratio;
179 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
181 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
183 .dma_desc_enable = 0,
184 .dma_burst_size = -1,
186 .host_support_fs_ls_low_power = -1,
187 .host_ls_low_power_phy_clk = -1,
188 .enable_dynamic_fifo = 1,
189 .data_fifo_size = -1,
190 .dev_rx_fifo_size = 0x120,
191 .dev_nperio_tx_fifo_size = 0x10,
192 .dev_perio_tx_fifo_size = {
193 /* dev_perio_tx_fifo_size_1 */
211 .host_rx_fifo_size = -1,
212 .host_nperio_tx_fifo_size = -1,
213 .host_perio_tx_fifo_size = -1,
214 .max_transfer_size = -1,
215 .max_packet_count = -1,
219 .phy_utmi_width = -1,
221 .phy_ulpi_ext_vbus = -1,
225 .en_multiple_tx_fifo = -1,
226 .dev_tx_fifo_size = {
227 /* dev_tx_fifo_size */
265 #ifdef CONFIG_USB20_HOST
266 static struct dwc_otg_driver_module_params dwc_host_module_params = {
268 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
270 .dma_desc_enable = 0,
271 .dma_burst_size = -1,
273 .host_support_fs_ls_low_power = -1,
274 .host_ls_low_power_phy_clk = -1,
275 .enable_dynamic_fifo = -1,
276 .data_fifo_size = -1,
277 .dev_rx_fifo_size = -1,
278 .dev_nperio_tx_fifo_size = -1,
279 .dev_perio_tx_fifo_size = {
280 /* dev_perio_tx_fifo_size_1 */
298 .host_rx_fifo_size = -1,
299 .host_nperio_tx_fifo_size = -1,
300 .host_perio_tx_fifo_size = -1,
301 .max_transfer_size = -1,
302 .max_packet_count = -1,
306 .phy_utmi_width = -1,
308 .phy_ulpi_ext_vbus = -1,
312 .en_multiple_tx_fifo = -1,
313 .dev_tx_fifo_size = {
314 /* dev_tx_fifo_size */
354 * This function shows the Driver Version.
356 static ssize_t version_show(struct device_driver *dev, char *buf)
358 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
362 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
365 * Global Debug Level Mask.
367 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
370 * This function shows the driver Debug Level.
372 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
374 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
378 * This function stores the driver Debug Level.
380 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
383 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
387 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
390 extern void hcd_start(dwc_otg_core_if_t *core_if);
391 extern struct usb_hub *g_dwc_otg_root_hub20;
392 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
394 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
396 dwc_otg_device_t *otg_dev = core_if->otg_dev;
397 dctl_data_t dctl = {.d32 = 0 };
400 if (core_if->op_state == A_HOST) {
401 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
404 core_if->op_state = A_HOST;
406 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
407 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
408 dctl.b.sftdiscon = 1;
409 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
411 local_irq_save(flags);
412 cil_pcd_stop(core_if);
414 * Initialize the Core for Host mode.
417 dwc_otg_core_init(core_if);
418 dwc_otg_enable_global_interrupts(core_if);
419 cil_hcd_start(core_if);
420 local_irq_restore(flags);
423 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
425 dwc_otg_device_t *otg_dev = core_if->otg_dev;
428 local_irq_save(flags);
430 if (core_if->op_state == B_PERIPHERAL) {
432 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
435 core_if->op_state = B_PERIPHERAL;
436 cil_hcd_stop(core_if);
437 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
438 otg_dev->pcd->phy_suspend = 1;
439 otg_dev->pcd->vbus_status = 0;
440 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
442 /* Reset the Controller */
443 dwc_otg_core_reset(core_if);
445 dwc_otg_core_init(core_if);
446 dwc_otg_disable_global_interrupts(core_if);
447 cil_pcd_start(core_if);
449 local_irq_restore(flags);
452 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
454 gusbcfg_data_t usbcfg = {.d32 = 0 };
455 printk("!!!dwc_otg_set_force_mode\n");
456 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
458 case USB_MODE_FORCE_HOST:
459 usbcfg.b.force_host_mode = 1;
460 usbcfg.b.force_dev_mode = 0;
462 case USB_MODE_FORCE_DEVICE:
463 usbcfg.b.force_host_mode = 0;
464 usbcfg.b.force_dev_mode = 1;
466 case USB_MODE_NORMAL:
467 usbcfg.b.force_host_mode = 0;
468 usbcfg.b.force_dev_mode = 0;
471 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
474 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
476 dwc_otg_device_t *otg_dev = g_otgdev;
477 dwc_otg_core_if_t *core_if = otg_dev->core_if;
479 return sprintf(buf, "%d\n", core_if->usb_mode);
482 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
485 int new_mode = simple_strtoul(buf, NULL, 16);
486 dwc_otg_device_t *otg_dev = g_otgdev;
487 dwc_otg_core_if_t *core_if;
488 struct dwc_otg_platform_data *pldata;
493 core_if = otg_dev->core_if;
494 pldata = otg_dev->pldata;
496 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
498 if (core_if->usb_mode == new_mode) {
502 if (pldata->phy_status == USB_PHY_SUSPEND) {
503 pldata->clock_enable(pldata, 1);
504 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
508 case USB_MODE_FORCE_HOST:
509 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
511 core_if->usb_mode = new_mode;
512 dwc_otg_force_host(core_if);
513 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
514 core_if->usb_mode = new_mode;
515 if (dwc_otg_is_host_mode(core_if))
516 dwc_otg_set_force_mode(core_if, new_mode);
518 dwc_otg_force_host(core_if);
522 case USB_MODE_FORCE_DEVICE:
523 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
524 core_if->usb_mode = new_mode;
525 dwc_otg_force_device(core_if);
526 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
527 core_if->usb_mode = new_mode;
528 if (dwc_otg_is_device_mode(core_if))
529 dwc_otg_set_force_mode(core_if, new_mode);
531 dwc_otg_force_device(core_if);
535 case USB_MODE_NORMAL:
536 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
537 core_if->usb_mode = new_mode;
538 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
539 dwc_otg_set_force_mode(core_if, new_mode);
541 if (dwc_otg_is_host_mode(core_if)) {
542 dwc_otg_force_host(core_if);
544 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
546 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
547 core_if->usb_mode = new_mode;
548 dwc_otg_set_force_mode(core_if, new_mode);
550 if (dwc_otg_is_device_mode(core_if)) {
551 dwc_otg_force_device(core_if);
562 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
563 force_usb_mode_store);
565 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
568 dwc_otg_device_t *otg_dev = g_otgdev;
569 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
570 return sprintf(_buf, "%d\n", _pcd->conn_en);
574 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
575 const char *_buf, size_t _count)
577 int enable = simple_strtoul(_buf, NULL, 10);
578 dwc_otg_device_t *otg_dev = g_otgdev;
579 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
580 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
582 _pcd->conn_en = enable;
586 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
587 dwc_otg_conn_en_store);
589 /* used for product vbus power control, SDK not need.
590 * If dwc_otg is host mode, enable vbus power.
591 * If dwc_otg is device mode, disable vbus power.
592 * return 1 - host mode, 0 - device mode.
594 int dwc_otg_usb_state(void)
596 dwc_otg_device_t *otg_dev = g_otgdev;
599 /* op_state is A_HOST */
600 if (1 == otg_dev->core_if->op_state)
602 /* op_state is B_PERIPHERAL */
603 else if (4 == otg_dev->core_if->op_state)
608 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
612 EXPORT_SYMBOL(dwc_otg_usb_state);
614 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
616 dwc_otg_device_t *otg_dev = g_otgdev;
619 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
621 return sprintf(_buf, "%d\n", 0);
624 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
626 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
628 dwc_otg_device_t *otg_dev = g_otgdev;
629 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
630 return sprintf(_buf, "%d\n", _pcd->vbus_status);
633 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
636 * This function is called during module intialization
637 * to pass module parameters to the DWC_OTG CORE.
639 static int set_parameters(dwc_otg_core_if_t *core_if,
640 struct dwc_otg_driver_module_params module_params)
645 if (module_params.otg_cap != -1) {
647 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
649 if (module_params.dma_enable != -1) {
651 dwc_otg_set_param_dma_enable(core_if,
652 module_params.dma_enable);
654 if (module_params.dma_desc_enable != -1) {
656 dwc_otg_set_param_dma_desc_enable(core_if,
657 module_params.dma_desc_enable);
659 if (module_params.opt != -1) {
660 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
662 if (module_params.dma_burst_size != -1) {
664 dwc_otg_set_param_dma_burst_size(core_if,
665 module_params.dma_burst_size);
667 if (module_params.host_support_fs_ls_low_power != -1) {
669 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
670 module_params.host_support_fs_ls_low_power);
672 if (module_params.enable_dynamic_fifo != -1) {
674 dwc_otg_set_param_enable_dynamic_fifo(core_if,
675 module_params.enable_dynamic_fifo);
677 if (module_params.data_fifo_size != -1) {
679 dwc_otg_set_param_data_fifo_size(core_if,
680 module_params.data_fifo_size);
682 if (module_params.dev_rx_fifo_size != -1) {
684 dwc_otg_set_param_dev_rx_fifo_size(core_if,
685 module_params.dev_rx_fifo_size);
687 if (module_params.dev_nperio_tx_fifo_size != -1) {
689 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
690 module_params.dev_nperio_tx_fifo_size);
692 if (module_params.host_rx_fifo_size != -1) {
694 dwc_otg_set_param_host_rx_fifo_size(core_if,
698 if (module_params.host_nperio_tx_fifo_size != -1) {
700 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
701 module_params.host_nperio_tx_fifo_size);
703 if (module_params.host_perio_tx_fifo_size != -1) {
705 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
706 module_params.host_perio_tx_fifo_size);
708 if (module_params.max_transfer_size != -1) {
710 dwc_otg_set_param_max_transfer_size(core_if,
711 module_params.max_transfer_size);
713 if (module_params.max_packet_count != -1) {
715 dwc_otg_set_param_max_packet_count(core_if,
716 module_params.max_packet_count);
718 if (module_params.host_channels != -1) {
720 dwc_otg_set_param_host_channels(core_if,
721 module_params.host_channels);
723 if (module_params.dev_endpoints != -1) {
725 dwc_otg_set_param_dev_endpoints(core_if,
726 module_params.dev_endpoints);
728 if (module_params.phy_type != -1) {
730 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
732 if (module_params.speed != -1) {
733 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
735 if (module_params.host_ls_low_power_phy_clk != -1) {
737 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
738 module_params.host_ls_low_power_phy_clk);
740 if (module_params.phy_ulpi_ddr != -1) {
742 dwc_otg_set_param_phy_ulpi_ddr(core_if,
743 module_params.phy_ulpi_ddr);
745 if (module_params.phy_ulpi_ext_vbus != -1) {
747 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
748 module_params.phy_ulpi_ext_vbus);
750 if (module_params.phy_utmi_width != -1) {
752 dwc_otg_set_param_phy_utmi_width(core_if,
753 module_params.phy_utmi_width);
755 if (module_params.ulpi_fs_ls != -1) {
757 dwc_otg_set_param_ulpi_fs_ls(core_if,
758 module_params.ulpi_fs_ls);
760 if (module_params.ts_dline != -1) {
762 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
764 if (module_params.i2c_enable != -1) {
766 dwc_otg_set_param_i2c_enable(core_if,
767 module_params.i2c_enable);
769 if (module_params.en_multiple_tx_fifo != -1) {
771 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
772 module_params.en_multiple_tx_fifo);
774 for (i = 0; i < 15; i++) {
775 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
777 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
778 module_params.dev_perio_tx_fifo_size
783 for (i = 0; i < 15; i++) {
784 if (module_params.dev_tx_fifo_size[i] != -1) {
785 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
786 module_params.dev_tx_fifo_size
790 if (module_params.thr_ctl != -1) {
792 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
794 if (module_params.mpi_enable != -1) {
796 dwc_otg_set_param_mpi_enable(core_if,
797 module_params.mpi_enable);
799 if (module_params.pti_enable != -1) {
801 dwc_otg_set_param_pti_enable(core_if,
802 module_params.pti_enable);
804 if (module_params.lpm_enable != -1) {
806 dwc_otg_set_param_lpm_enable(core_if,
807 module_params.lpm_enable);
809 if (module_params.besl_enable != -1) {
811 dwc_otg_set_param_besl_enable(core_if,
812 module_params.besl_enable);
814 if (module_params.baseline_besl != -1) {
816 dwc_otg_set_param_baseline_besl(core_if,
817 module_params.baseline_besl);
819 if (module_params.deep_besl != -1) {
821 dwc_otg_set_param_deep_besl(core_if,
822 module_params.deep_besl);
824 if (module_params.ic_usb_cap != -1) {
826 dwc_otg_set_param_ic_usb_cap(core_if,
827 module_params.ic_usb_cap);
829 if (module_params.tx_thr_length != -1) {
831 dwc_otg_set_param_tx_thr_length(core_if,
835 if (module_params.rx_thr_length != -1) {
837 dwc_otg_set_param_rx_thr_length(core_if,
838 module_params.rx_thr_length);
840 if (module_params.ahb_thr_ratio != -1) {
842 dwc_otg_set_param_ahb_thr_ratio(core_if,
846 if (module_params.power_down != -1) {
848 dwc_otg_set_param_power_down(core_if,
849 module_params.power_down);
851 if (module_params.reload_ctl != -1) {
853 dwc_otg_set_param_reload_ctl(core_if,
854 module_params.reload_ctl);
857 if (module_params.dev_out_nak != -1) {
859 dwc_otg_set_param_dev_out_nak(core_if,
860 module_params.dev_out_nak);
863 if (module_params.cont_on_bna != -1) {
865 dwc_otg_set_param_cont_on_bna(core_if,
866 module_params.cont_on_bna);
869 if (module_params.ahb_single != -1) {
871 dwc_otg_set_param_ahb_single(core_if,
872 module_params.ahb_single);
875 if (module_params.otg_ver != -1) {
877 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
879 if (module_params.adp_enable != -1) {
881 dwc_otg_set_param_adp_enable(core_if,
882 module_params.adp_enable);
888 * This function is the top level interrupt handler for the Common
889 * (Device and host modes) interrupts.
891 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
893 int32_t retval = IRQ_NONE;
895 retval = dwc_otg_handle_common_intr(dev);
897 /* S3C2410X_CLEAR_EINTPEND(); */
899 return IRQ_RETVAL(retval);
902 #ifdef CONFIG_USB20_HOST
904 * This function is called when a lm_device is unregistered with the
905 * dwc_otg_driver. This happens, for example, when the rmmod command is
906 * executed. The device may or may not be electrically present. If it is
907 * present, the driver stops device processing. Any resources used on behalf
908 * of this device are freed.
912 static int host20_driver_remove(struct platform_device *_dev)
915 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
916 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
919 /* Memory allocation for the dwc_otg_device failed. */
920 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
923 #ifndef DWC_DEVICE_ONLY
927 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
932 #ifndef DWC_HOST_ONLY
936 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
944 if (otg_dev->common_irq_installed) {
945 /* free_irq(_dev->irq, otg_dev); */
946 free_irq(platform_get_irq(_dev, 0), otg_dev);
948 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
953 if (otg_dev->core_if) {
954 dwc_otg_cil_remove(otg_dev->core_if);
956 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
961 * Remove the device attributes
963 dwc_otg_attr_remove(_dev);
968 if (otg_dev->os_dep.base) {
969 iounmap(otg_dev->os_dep.base);
974 * Clear the drvdata pointer.
977 dwc_set_device_platform_data(_dev, 0);
982 static const struct of_device_id usb20_host_of_match[] = {
984 .compatible = "rockchip,rk3188_usb20_host",
985 .data = &usb20host_pdata[RK3188_USB_CTLR],
988 .compatible = "rockchip,rk3288_usb20_host",
989 .data = &usb20host_pdata[RK3288_USB_CTLR],
992 .compatible = "rockchip,rk3036_usb20_host",
993 .data = &usb20host_pdata[RK3036_USB_CTLR],
996 .compatible = "rockchip,rk3126_usb20_host",
997 .data = &usb20host_pdata[RK3126_USB_CTLR],
1002 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
1005 * This function is called when an lm_device is bound to a
1006 * dwc_otg_driver. It creates the driver components required to
1007 * control the device (CIL, HCD, and PCD) and it initializes the
1008 * device. The driver components are stored in a dwc_otg_device
1009 * structure. A reference to the dwc_otg_device is saved in the
1010 * lm_device. This allows the driver to access the dwc_otg_device
1011 * structure on subsequent calls to driver methods for this device.
1013 * @param _dev Bus device
1015 static int host20_driver_probe(struct platform_device *_dev)
1019 struct resource *res_base;
1020 dwc_otg_device_t *dwc_otg_device;
1021 struct device *dev = &_dev->dev;
1022 struct device_node *node = _dev->dev.of_node;
1023 struct dwc_otg_platform_data *pldata;
1024 struct usb20host_pdata_id *p;
1025 const struct of_device_id *match =
1026 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
1029 p = (struct usb20host_pdata_id *)match->data;
1031 dev_err(dev, "usb20host match failed\n");
1035 dev->platform_data = p->pdata;
1036 pldata = dev->platform_data;
1040 dev_err(dev, "device node not found\n");
1044 if (pldata->hw_init)
1047 if (pldata->clock_init) {
1048 pldata->clock_init(pldata);
1049 pldata->clock_enable(pldata, 1);
1052 if (pldata->phy_suspend)
1053 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1055 if (pldata->soft_reset)
1056 pldata->soft_reset(pldata, RST_POR);
1058 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1060 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1062 if (!dwc_otg_device) {
1063 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1068 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1069 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1072 * Map the DWC_otg Core memory into virtual address space.
1075 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1077 if (!dwc_otg_device->os_dep.base) {
1078 dev_err(&_dev->dev, "ioremap() failed\n");
1079 DWC_FREE(dwc_otg_device);
1083 dev_dbg(&_dev->dev, "base=0x%08x\n",
1084 (unsigned)dwc_otg_device->os_dep.base);
1087 * Initialize driver data to point to the global DWC_otg
1091 dwc_set_device_platform_data(_dev, dwc_otg_device);
1092 pldata->privdata = dwc_otg_device;
1093 dwc_otg_device->pldata = (void *)pldata;
1095 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1097 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1099 if (!dwc_otg_device->core_if) {
1100 dev_err(&_dev->dev, "CIL initialization failed!\n");
1105 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1108 * Attempt to ensure this device is really a DWC_otg Controller.
1109 * Read and verify the SNPSID register contents. The value should be
1110 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1111 * as in "OTG version 2.XX" or "OTG version 3.XX".
1114 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1116 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1118 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1119 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1125 * Validate parameter values.
1127 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1133 * Create Device Attributes in sysfs
1135 dwc_otg_attr_create(_dev);
1138 * Disable the global interrupt until all the interrupt
1139 * handlers are installed.
1141 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1144 * Install the interrupt handler for the common interrupts before
1145 * enabling common interrupts in core_init below.
1147 irq = platform_get_irq(_dev, 0);
1148 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1149 retval = request_irq(irq, dwc_otg_common_irq,
1150 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1152 DWC_ERROR("request of irq%d failed\n", irq);
1156 dwc_otg_device->common_irq_installed = 1;
1160 * Initialize the DWC_otg core.
1161 * In order to reduce the time of initialization,
1162 * we do core soft reset after connection detected.
1164 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1167 * Initialize the HCD
1169 retval = host20_hcd_init(_dev);
1171 DWC_ERROR("hcd_init failed\n");
1172 dwc_otg_device->hcd = NULL;
1176 clk_set_rate(pldata->phyclk_480m, 480000000);
1178 * Enable the global interrupt after all the interrupt
1179 * handlers are installed if there is no ADP support else
1180 * perform initial actions required for Internal ADP logic.
1182 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1183 if (pldata->phy_status == USB_PHY_ENABLED) {
1184 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1186 pldata->clock_enable(pldata, 0);
1188 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1190 dwc_otg_adp_start(dwc_otg_device->core_if,
1191 dwc_otg_is_host_mode(dwc_otg_device->
1197 host20_driver_remove(_dev);
1199 if (pldata->clock_enable)
1200 pldata->clock_enable(pldata, 0);
1206 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1212 static int dwc_otg_driver_resume(struct platform_device *_dev)
1217 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1219 struct device *dev = &_dev->dev;
1220 dwc_otg_device_t *otg_dev = dev->platform_data;
1221 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1222 dctl_data_t dctl = {.d32 = 0 };
1224 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1225 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1226 if (dwc_otg_is_host_mode(core_if)) {
1227 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1228 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1230 /* soft disconnect */
1232 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1233 dctl.b.sftdiscon = 1;
1234 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1237 /* Clear any pending interrupts */
1238 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1243 * This structure defines the methods to be called by a bus driver
1244 * during the lifecycle of a device on that bus. Both drivers and
1245 * devices are registered with a bus driver. The bus driver matches
1246 * devices to drivers based on information in the device and driver
1249 * The probe function is called when the bus driver matches a device
1250 * to this driver. The remove function is called when a device is
1251 * unregistered with the bus driver.
1253 #ifdef CONFIG_USB20_HOST
1254 static struct platform_driver dwc_host_driver = {
1256 .name = (char *)dwc_host20_driver_name,
1257 .of_match_table = of_match_ptr(usb20_host_of_match),
1259 .probe = host20_driver_probe,
1260 .remove = host20_driver_remove,
1261 .suspend = dwc_otg_driver_suspend,
1262 .resume = dwc_otg_driver_resume,
1266 #ifdef CONFIG_USB20_OTG
1268 * This function is called when a lm_device is unregistered with the
1269 * dwc_otg_driver. This happens, for example, when the rmmod command is
1270 * executed. The device may or may not be electrically present. If it is
1271 * present, the driver stops device processing. Any resources used on behalf
1272 * of this device are freed.
1276 static int otg20_driver_remove(struct platform_device *_dev)
1279 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1280 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1283 /* Memory allocation for the dwc_otg_device failed. */
1284 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1287 #ifndef DWC_DEVICE_ONLY
1291 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1296 #ifndef DWC_HOST_ONLY
1300 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1307 if (otg_dev->common_irq_installed) {
1308 /* free_irq(_dev->irq, otg_dev); */
1309 free_irq(platform_get_irq(_dev, 0), otg_dev);
1311 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1316 if (otg_dev->core_if) {
1317 dwc_otg_cil_remove(otg_dev->core_if);
1319 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1324 * Remove the device attributes
1326 dwc_otg_attr_remove(_dev);
1329 * Return the memory.
1331 if (otg_dev->os_dep.base)
1332 iounmap(otg_dev->os_dep.base);
1336 * Clear the drvdata pointer.
1339 dwc_set_device_platform_data(_dev, 0);
1344 static const struct of_device_id usb20_otg_of_match[] = {
1346 .compatible = "rockchip,rk3188_usb20_otg",
1347 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1350 .compatible = "rockchip,rk3288_usb20_otg",
1351 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1354 .compatible = "rockchip,rk3036_usb20_otg",
1355 .data = &usb20otg_pdata[RK3036_USB_CTLR],
1358 .compatible = "rockchip,rk3126_usb20_otg",
1359 .data = &usb20otg_pdata[RK3126_USB_CTLR],
1365 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1368 * This function is called when an lm_device is bound to a
1369 * dwc_otg_driver. It creates the driver components required to
1370 * control the device (CIL, HCD, and PCD) and it initializes the
1371 * device. The driver components are stored in a dwc_otg_device
1372 * structure. A reference to the dwc_otg_device is saved in the
1373 * lm_device. This allows the driver to access the dwc_otg_device
1374 * structure on subsequent calls to driver methods for this device.
1376 * @param _dev Bus device
1378 static int otg20_driver_probe(struct platform_device *_dev)
1383 struct resource *res_base;
1384 dwc_otg_device_t *dwc_otg_device;
1385 struct device *dev = &_dev->dev;
1386 struct device_node *node = _dev->dev.of_node;
1387 struct dwc_otg_platform_data *pldata;
1388 struct usb20otg_pdata_id *p;
1389 const struct of_device_id *match =
1390 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1393 p = (struct usb20otg_pdata_id *)match->data;
1395 dev_err(dev, "usb20otg match failed\n");
1399 dev->platform_data = p->pdata;
1400 /* dev->platform_data = &usb20otg_pdata; */
1401 pldata = dev->platform_data;
1405 dev_err(dev, "device node not found\n");
1408 /*todo : move to usbdev_rk-XX.c */
1409 if (pldata->hw_init)
1412 if (pldata->clock_init) {
1413 pldata->clock_init(pldata);
1414 pldata->clock_enable(pldata, 1);
1417 if (pldata->phy_suspend)
1418 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1420 if (pldata->dwc_otg_uart_mode)
1421 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1423 /* do reset later, because reset need about
1424 * 100ms to ensure otg id state change.
1427 if(pldata->soft_reset)
1428 pldata->soft_reset();
1432 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1434 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1436 if (!dwc_otg_device) {
1437 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1442 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1443 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1446 * Map the DWC_otg Core memory into virtual address space.
1449 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1451 if (!dwc_otg_device->os_dep.base) {
1452 dev_err(&_dev->dev, "ioremap() failed\n");
1453 DWC_FREE(dwc_otg_device);
1457 dev_dbg(&_dev->dev, "base=0x%08x\n",
1458 (unsigned)dwc_otg_device->os_dep.base);
1461 * Initialize driver data to point to the global DWC_otg
1465 g_otgdev = dwc_otg_device;
1466 pldata->privdata = dwc_otg_device;
1467 dwc_otg_device->pldata = pldata;
1469 dwc_set_device_platform_data(_dev, dwc_otg_device);
1471 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1473 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1474 if (!dwc_otg_device->core_if) {
1475 dev_err(&_dev->dev, "CIL initialization failed!\n");
1480 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1482 * Attempt to ensure this device is really a DWC_otg Controller.
1483 * Read and verify the SNPSID register contents. The value should be
1484 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1485 * as in "OTG version 2.XX" or "OTG version 3.XX".
1488 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1490 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1492 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1493 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1499 * Validate parameter values.
1501 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1507 * Create Device Attributes in sysfs
1509 dwc_otg_attr_create(_dev);
1512 * Disable the global interrupt until all the interrupt
1513 * handlers are installed.
1515 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1518 * Install the interrupt handler for the common interrupts before
1519 * enabling common interrupts in core_init below.
1521 irq = platform_get_irq(_dev, 0);
1522 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1523 retval = request_irq(irq, dwc_otg_common_irq,
1524 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1526 DWC_ERROR("request of irq%d failed\n", irq);
1530 dwc_otg_device->common_irq_installed = 1;
1534 * Initialize the DWC_otg core.
1535 * In order to reduce the time of initialization,
1536 * we do core soft reset after connection detected.
1538 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1541 * 0 - USB_MODE_NORMAL
1542 * 1 - USB_MODE_FORCE_HOST
1543 * 2 - USB_MODE_FORCE_DEVICE
1545 of_property_read_u32(node, "rockchip,usb-mode", &val);
1546 dwc_otg_device->core_if->usb_mode = val;
1548 #ifndef DWC_HOST_ONLY
1550 * Initialize the PCD
1552 retval = pcd_init(_dev);
1554 DWC_ERROR("pcd_init failed\n");
1555 dwc_otg_device->pcd = NULL;
1559 #ifndef DWC_DEVICE_ONLY
1561 * Initialize the HCD
1563 retval = otg20_hcd_init(_dev);
1565 DWC_ERROR("hcd_init failed\n");
1566 dwc_otg_device->hcd = NULL;
1571 * Enable the global interrupt after all the interrupt
1572 * handlers are installed if there is no ADP support else
1573 * perform initial actions required for Internal ADP logic.
1575 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1576 if (pldata->phy_status == USB_PHY_ENABLED) {
1577 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1579 pldata->clock_enable(pldata, 0);
1581 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1583 dwc_otg_adp_start(dwc_otg_device->core_if,
1584 dwc_otg_is_host_mode(dwc_otg_device->
1590 otg20_driver_remove(_dev);
1593 if (pldata->clock_enable)
1594 pldata->clock_enable(pldata, 0);
1599 static struct platform_driver dwc_otg_driver = {
1601 .name = (char *)dwc_otg20_driver_name,
1602 .of_match_table = of_match_ptr(usb20_otg_of_match),
1604 .probe = otg20_driver_probe,
1605 .remove = otg20_driver_remove,
1606 .suspend = dwc_otg_driver_suspend,
1607 .resume = dwc_otg_driver_resume,
1608 .shutdown = dwc_otg_driver_shutdown,
1612 void rk_usb_power_up(void)
1614 struct dwc_otg_platform_data *pldata_otg;
1615 struct dwc_otg_platform_data *pldata_host;
1616 struct rkehci_platform_data *pldata_ehci;
1618 if (cpu_is_rk3288()) {
1619 #ifdef CONFIG_RK_USB_UART
1620 /* enable USB bypass UART function */
1621 writel_relaxed(0x00c00000 | usb_to_uart_status,
1622 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1625 /* unset siddq,the analog blocks are powered up */
1626 #ifdef CONFIG_USB20_OTG
1627 pldata_otg = &usb20otg_pdata_rk3288;
1629 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1630 writel_relaxed((0x01 << 13) << 16,
1632 RK3288_GRF_UOC0_CON0);
1635 #ifdef CONFIG_USB20_HOST
1636 pldata_host = &usb20host_pdata_rk3288;
1638 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1639 writel_relaxed((0x01 << 13) << 16,
1641 RK3288_GRF_UOC2_CON0);
1644 #ifdef CONFIG_USB_EHCI_RK
1645 pldata_ehci = &rkehci_pdata_rk3288;
1647 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1648 writel_relaxed((0x01 << 13) << 16,
1650 RK3288_GRF_UOC1_CON0);
1657 void rk_usb_power_down(void)
1659 struct dwc_otg_platform_data *pldata_otg;
1660 struct dwc_otg_platform_data *pldata_host;
1661 struct rkehci_platform_data *pldata_ehci;
1663 if (cpu_is_rk3288()) {
1664 #ifdef CONFIG_RK_USB_UART
1665 /* disable USB bypass UART function */
1666 usb_to_uart_status =
1667 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1668 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1670 /* set siddq,the analog blocks are powered down
1672 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1673 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1674 * and TESTBURNIN are set to 1'b0.
1675 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1676 #ifdef CONFIG_USB20_OTG
1677 pldata_otg = &usb20otg_pdata_rk3288;
1679 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1680 writel_relaxed((0x01 << 13) |
1681 ((0x01 << 13) << 16),
1683 RK3288_GRF_UOC0_CON0);
1686 #ifdef CONFIG_USB20_HOST
1687 pldata_host = &usb20host_pdata_rk3288;
1689 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1690 writel_relaxed((0x01 << 13) |
1691 ((0x01 << 13) << 16),
1693 RK3288_GRF_UOC2_CON0);
1696 #ifdef CONFIG_USB_EHCI_RK
1697 pldata_ehci = &rkehci_pdata_rk3288;
1699 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1700 writel_relaxed((0x01 << 13) |
1701 ((0x01 << 13) << 16),
1703 RK3288_GRF_UOC1_CON0);
1709 EXPORT_SYMBOL(rk_usb_power_up);
1710 EXPORT_SYMBOL(rk_usb_power_down);
1712 * This function is called when the dwc_otg_driver is installed with the
1713 * insmod command. It registers the dwc_otg_driver structure with the
1714 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1715 * to be called. In addition, the bus driver will automatically expose
1716 * attributes defined for the device and driver in the special sysfs file
1721 static int __init dwc_otg_driver_init(void)
1726 #ifdef CONFIG_USB20_OTG
1727 /* register otg20 */
1728 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1729 DWC_DRIVER_VERSION);
1731 retval = platform_driver_register(&dwc_otg_driver);
1733 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1738 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1740 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1742 driver_create_file(&dwc_otg_driver.driver,
1743 &driver_attr_dwc_otg_conn_en);
1745 driver_create_file(&dwc_otg_driver.driver,
1746 &driver_attr_vbus_status);
1748 driver_create_file(&dwc_otg_driver.driver,
1749 &driver_attr_force_usb_mode);
1751 driver_create_file(&dwc_otg_driver.driver,
1752 &driver_attr_op_state);
1756 /* register host20 */
1757 #ifdef CONFIG_USB20_HOST
1758 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1759 DWC_DRIVER_VERSION);
1761 retval = platform_driver_register(&dwc_host_driver);
1763 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1768 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1770 driver_create_file(&dwc_host_driver.driver,
1771 &driver_attr_debuglevel);
1776 module_init(dwc_otg_driver_init);
1779 * This function is called when the driver is removed from the kernel
1780 * with the rmmod command. The driver unregisters itself with its bus
1784 static void __exit dwc_otg_driver_cleanup(void)
1786 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1788 #ifdef CONFIG_USB20_HOST
1790 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1791 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1792 platform_driver_unregister(&dwc_host_driver);
1793 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1796 #ifdef CONFIG_USB20_OTG
1798 driver_remove_file(&dwc_otg_driver.driver,
1799 &driver_attr_dwc_otg_conn_en);
1800 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1801 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1802 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1803 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1804 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1805 platform_driver_unregister(&dwc_otg_driver);
1806 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1810 module_exit(dwc_otg_driver_cleanup);
1812 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1813 MODULE_AUTHOR("Synopsys Inc.");
1814 MODULE_LICENSE("GPL");
1816 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1817 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1818 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1819 MODULE_PARM_DESC(opt, "OPT Mode");
1820 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1821 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1823 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1825 MODULE_PARM_DESC(dma_desc_enable,
1826 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1828 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1830 MODULE_PARM_DESC(dma_burst_size,
1831 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1832 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1833 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1834 module_param_named(host_support_fs_ls_low_power,
1835 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1837 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1838 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1839 module_param_named(host_ls_low_power_phy_clk,
1840 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1841 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1842 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1843 module_param_named(enable_dynamic_fifo,
1844 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1845 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1846 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1848 MODULE_PARM_DESC(data_fifo_size,
1849 "Total number of words in the data FIFO memory 32-32768");
1850 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1852 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1853 module_param_named(dev_nperio_tx_fifo_size,
1854 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1855 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1856 "Number of words in the non-periodic Tx FIFO 16-32768");
1857 module_param_named(dev_perio_tx_fifo_size_1,
1858 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1859 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1860 "Number of words in the periodic Tx FIFO 4-768");
1861 module_param_named(dev_perio_tx_fifo_size_2,
1862 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1863 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1864 "Number of words in the periodic Tx FIFO 4-768");
1865 module_param_named(dev_perio_tx_fifo_size_3,
1866 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1867 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1868 "Number of words in the periodic Tx FIFO 4-768");
1869 module_param_named(dev_perio_tx_fifo_size_4,
1870 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1871 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1872 "Number of words in the periodic Tx FIFO 4-768");
1873 module_param_named(dev_perio_tx_fifo_size_5,
1874 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1875 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1876 "Number of words in the periodic Tx FIFO 4-768");
1877 module_param_named(dev_perio_tx_fifo_size_6,
1878 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1879 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1880 "Number of words in the periodic Tx FIFO 4-768");
1881 module_param_named(dev_perio_tx_fifo_size_7,
1882 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1883 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1884 "Number of words in the periodic Tx FIFO 4-768");
1885 module_param_named(dev_perio_tx_fifo_size_8,
1886 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1887 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1888 "Number of words in the periodic Tx FIFO 4-768");
1889 module_param_named(dev_perio_tx_fifo_size_9,
1890 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1891 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1892 "Number of words in the periodic Tx FIFO 4-768");
1893 module_param_named(dev_perio_tx_fifo_size_10,
1894 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1895 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1896 "Number of words in the periodic Tx FIFO 4-768");
1897 module_param_named(dev_perio_tx_fifo_size_11,
1898 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1899 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1900 "Number of words in the periodic Tx FIFO 4-768");
1901 module_param_named(dev_perio_tx_fifo_size_12,
1902 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1903 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1904 "Number of words in the periodic Tx FIFO 4-768");
1905 module_param_named(dev_perio_tx_fifo_size_13,
1906 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1907 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1908 "Number of words in the periodic Tx FIFO 4-768");
1909 module_param_named(dev_perio_tx_fifo_size_14,
1910 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1911 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1912 "Number of words in the periodic Tx FIFO 4-768");
1913 module_param_named(dev_perio_tx_fifo_size_15,
1914 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1915 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1916 "Number of words in the periodic Tx FIFO 4-768");
1917 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1919 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1920 module_param_named(host_nperio_tx_fifo_size,
1921 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1922 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1923 "Number of words in the non-periodic Tx FIFO 16-32768");
1924 module_param_named(host_perio_tx_fifo_size,
1925 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1926 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1927 "Number of words in the host periodic Tx FIFO 16-32768");
1928 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1930 /** @todo Set the max to 512K, modify checks */
1931 MODULE_PARM_DESC(max_transfer_size,
1932 "The maximum transfer size supported in bytes 2047-65535");
1933 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1935 MODULE_PARM_DESC(max_packet_count,
1936 "The maximum number of packets in a transfer 15-511");
1937 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1939 MODULE_PARM_DESC(host_channels,
1940 "The number of host channel registers to use 1-16");
1941 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1943 MODULE_PARM_DESC(dev_endpoints,
1944 "The number of endpoints in addition to EP0 available for device mode 1-15");
1945 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1946 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1947 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1949 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1950 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1951 MODULE_PARM_DESC(phy_ulpi_ddr,
1952 "ULPI at double or single data rate 0=Single 1=Double");
1953 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1955 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1956 "ULPI PHY using internal or external vbus 0=Internal");
1957 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1958 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1959 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1960 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1961 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1962 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1963 module_param_named(debug, g_dbg_lvl, int, 0444);
1964 MODULE_PARM_DESC(debug, "");
1966 module_param_named(en_multiple_tx_fifo,
1967 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1968 MODULE_PARM_DESC(en_multiple_tx_fifo,
1969 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1970 module_param_named(dev_tx_fifo_size_1,
1971 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1972 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1973 module_param_named(dev_tx_fifo_size_2,
1974 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1975 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1976 module_param_named(dev_tx_fifo_size_3,
1977 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1978 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1979 module_param_named(dev_tx_fifo_size_4,
1980 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1981 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1982 module_param_named(dev_tx_fifo_size_5,
1983 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1984 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1985 module_param_named(dev_tx_fifo_size_6,
1986 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1987 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1988 module_param_named(dev_tx_fifo_size_7,
1989 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1990 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1991 module_param_named(dev_tx_fifo_size_8,
1992 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1993 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1994 module_param_named(dev_tx_fifo_size_9,
1995 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1996 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1997 module_param_named(dev_tx_fifo_size_10,
1998 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1999 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(dev_tx_fifo_size_11,
2001 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_12,
2004 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2006 module_param_named(dev_tx_fifo_size_13,
2007 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_14,
2010 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2011 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2012 module_param_named(dev_tx_fifo_size_15,
2013 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2016 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2017 MODULE_PARM_DESC(thr_ctl,
2018 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2019 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2021 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2022 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2024 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2026 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2027 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2028 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2029 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2031 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2032 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2033 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2035 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2036 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2037 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2039 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2040 MODULE_PARM_DESC(ic_usb_cap,
2041 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2042 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2044 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2045 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2046 MODULE_PARM_DESC(power_down, "Power Down Mode");
2047 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2048 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2049 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2050 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2051 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2052 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2053 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2054 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2055 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2056 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2057 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2058 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2060 /** @page "Module Parameters"
2062 * The following parameters may be specified when starting the module.
2063 * These parameters define how the DWC_otg controller should be
2064 * configured. Parameter values are passed to the CIL initialization
2065 * function dwc_otg_cil_init
2067 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2071 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2075 <td>Specifies the OTG capabilities. The driver will automatically detect the
2076 value for this parameter if none is specified.
2077 - 0: HNP and SRP capable (default, if available)
2078 - 1: SRP Only capable
2079 - 2: No HNP/SRP capable
2084 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2085 The driver will automatically detect the value for this parameter if none is
2088 - 1: DMA (default, if available)
2092 <td>dma_burst_size</td>
2093 <td>The DMA Burst size (applicable only for External DMA Mode).
2094 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2099 <td>Specifies the maximum speed of operation in host and device mode. The
2100 actual speed depends on the speed of the attached device and the value of
2102 - 0: High Speed (default)
2107 <td>host_support_fs_ls_low_power</td>
2108 <td>Specifies whether low power mode is supported when attached to a Full
2109 Speed or Low Speed device in host mode.
2110 - 0: Don't support low power mode (default)
2111 - 1: Support low power mode
2115 <td>host_ls_low_power_phy_clk</td>
2116 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2117 Speed device in host mode. This parameter is applicable only if
2118 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2119 - 0: 48 MHz (default)
2124 <td>enable_dynamic_fifo</td>
2125 <td> Specifies whether FIFOs may be resized by the driver software.
2126 - 0: Use cC FIFO size parameters
2127 - 1: Allow dynamic FIFO sizing (default)
2131 <td>data_fifo_size</td>
2132 <td>Total number of 4-byte words in the data FIFO memory. This memory
2133 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2134 - Values: 32 to 32768 (default 8192)
2136 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2140 <td>dev_rx_fifo_size</td>
2141 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2142 FIFO sizing is enabled.
2143 - Values: 16 to 32768 (default 1064)
2147 <td>dev_nperio_tx_fifo_size</td>
2148 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2149 dynamic FIFO sizing is enabled.
2150 - Values: 16 to 32768 (default 1024)
2154 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2155 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2156 when dynamic FIFO sizing is enabled.
2157 - Values: 4 to 768 (default 256)
2161 <td>host_rx_fifo_size</td>
2162 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2164 - Values: 16 to 32768 (default 1024)
2168 <td>host_nperio_tx_fifo_size</td>
2169 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2170 dynamic FIFO sizing is enabled in the core.
2171 - Values: 16 to 32768 (default 1024)
2175 <td>host_perio_tx_fifo_size</td>
2176 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2178 - Values: 16 to 32768 (default 1024)
2182 <td>max_transfer_size</td>
2183 <td>The maximum transfer size supported in bytes.
2184 - Values: 2047 to 65,535 (default 65,535)
2188 <td>max_packet_count</td>
2189 <td>The maximum number of packets in a transfer.
2190 - Values: 15 to 511 (default 511)
2194 <td>host_channels</td>
2195 <td>The number of host channel registers to use.
2196 - Values: 1 to 16 (default 12)
2198 Note: The FPGA configuration supports a maximum of 12 host channels.
2202 <td>dev_endpoints</td>
2203 <td>The number of endpoints in addition to EP0 available for device mode
2205 - Values: 1 to 15 (default 6 IN and OUT)
2207 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2213 <td>Specifies the type of PHY interface to use. By default, the driver will
2214 automatically detect the phy_type.
2216 - 1: UTMI+ (default, if available)
2221 <td>phy_utmi_width</td>
2222 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2223 phy_type of UTMI+. Also, this parameter is applicable only if the
2224 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2225 core has been configured to work at either data path width.
2226 - Values: 8 or 16 bits (default 16)
2230 <td>phy_ulpi_ddr</td>
2231 <td>Specifies whether the ULPI operates at double or single data rate. This
2232 parameter is only applicable if phy_type is ULPI.
2233 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2234 - 1: double data rate ULPI interface with 4 bit wide data bus
2239 <td>Specifies whether to use the I2C interface for full speed PHY. This
2240 parameter is only applicable if PHY_TYPE is FS.
2241 - 0: Disabled (default)
2247 <td>Specifies whether to use ULPI FS/LS mode only.
2248 - 0: Disabled (default)
2254 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2255 - 0: Disabled (default)
2260 <td>en_multiple_tx_fifo</td>
2261 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2262 The driver will automatically detect the value for this parameter if none is
2265 - 1: Enabled (default, if available)
2269 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2270 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2271 when dynamic FIFO sizing is enabled.
2272 - Values: 4 to 768 (default 256)
2276 <td>tx_thr_length</td>
2277 <td>Transmit Threshold length in 32 bit double words
2278 - Values: 8 to 128 (default 64)
2282 <td>rx_thr_length</td>
2283 <td>Receive Threshold length in 32 bit double words
2284 - Values: 8 to 128 (default 64)
2289 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2290 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2291 Rx transfers accordingly.
2292 The driver will automatically detect the value for this parameter if none is
2294 - Values: 0 to 7 (default 0)
2295 Bit values indicate:
2296 - 0: Thresholding disabled
2297 - 1: Thresholding enabled
2301 <td>dma_desc_enable</td>
2302 <td>Specifies whether to enable Descriptor DMA mode.
2303 The driver will automatically detect the value for this parameter if none is
2305 - 0: Descriptor DMA disabled
2306 - 1: Descriptor DMA (default, if available)
2311 <td>Specifies whether to enable MPI enhancement mode.
2312 The driver will automatically detect the value for this parameter if none is
2314 - 0: MPI disabled (default)
2320 <td>Specifies whether to enable PTI enhancement support.
2321 The driver will automatically detect the value for this parameter if none is
2323 - 0: PTI disabled (default)
2329 <td>Specifies whether to enable LPM support.
2330 The driver will automatically detect the value for this parameter if none is
2333 - 1: LPM enable (default, if available)
2337 <td>besl_enable</td>
2338 <td>Specifies whether to enable LPM Errata support.
2339 The driver will automatically detect the value for this parameter if none is
2341 - 0: LPM Errata disabled (default)
2342 - 1: LPM Errata enable
2346 <td>baseline_besl</td>
2347 <td>Specifies the baseline besl value.
2348 - Values: 0 to 15 (default 0)
2353 <td>Specifies the deep besl value.
2354 - Values: 0 to 15 (default 15)
2359 <td>Specifies whether to enable IC_USB capability.
2360 The driver will automatically detect the value for this parameter if none is
2362 - 0: IC_USB disabled (default, if available)
2367 <td>ahb_thr_ratio</td>
2368 <td>Specifies AHB Threshold ratio.
2369 - Values: 0 to 3 (default 0)
2374 <td>Specifies Power Down(Hibernation) Mode.
2375 The driver will automatically detect the value for this parameter if none is
2377 - 0: Power Down disabled (default)
2378 - 2: Power Down enabled
2383 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2384 run time. The driver will automatically detect the value for this parameter if
2385 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2386 the core might misbehave.
2387 - 0: Reload Control disabled (default)
2388 - 1: Reload Control enabled
2392 <td>dev_out_nak</td>
2393 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2394 The driver will automatically detect the value for this parameter if
2395 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2396 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2397 - 1: The core sets NAK after Bulk OUT transfer complete
2401 <td>cont_on_bna</td>
2402 <td>Specifies whether Enable Continue on BNA enabled or no.
2403 After receiving BNA interrupt the core disables the endpoint,when the
2404 endpoint is re-enabled by the application the
2405 - 0: Core starts processing from the DOEPDMA descriptor (default)
2406 - 1: Core starts processing from the descriptor which received the BNA.
2407 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2412 <td>This bit when programmed supports SINGLE transfers for remainder data
2413 in a transfer for DMA mode of operation.
2414 - 0: The remainder data will be sent using INCR burst size (default)
2415 - 1: The remainder data will be sent using SINGLE burst size.
2420 <td>Specifies whether ADP feature is enabled.
2421 The driver will automatically detect the value for this parameter if none is
2423 - 0: ADP feature disabled (default)
2424 - 1: ADP feature enabled
2429 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2431 - 0: OTG 2.0 support disabled (default)
2432 - 1: OTG 2.0 support enabled