1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
90 .name = "rk3036-usb20otg",
91 .pdata = &usb20otg_pdata_rk3036,
97 #ifdef CONFIG_USB20_HOST
98 static struct usb20host_pdata_id usb20host_pdata[] = {
100 .name = "rk3188-usb20host",
101 .pdata = &usb20host_pdata_rk3188,
104 .name = "rk3288-usb20host",
105 .pdata = &usb20host_pdata_rk3288,
108 .name = "rk3036-usb20host",
109 .pdata = &usb20host_pdata_rk3036,
115 #ifdef CONFIG_RK_USB_UART
116 static u32 usb_to_uart_status;
118 /*-------------------------------------------------------------------------*/
119 /* Encapsulate the module parameter settings */
121 struct dwc_otg_driver_module_params {
125 int32_t dma_desc_enable;
126 int32_t dma_burst_size;
128 int32_t host_support_fs_ls_low_power;
129 int32_t host_ls_low_power_phy_clk;
130 int32_t enable_dynamic_fifo;
131 int32_t data_fifo_size;
132 int32_t dev_rx_fifo_size;
133 int32_t dev_nperio_tx_fifo_size;
134 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
135 int32_t host_rx_fifo_size;
136 int32_t host_nperio_tx_fifo_size;
137 int32_t host_perio_tx_fifo_size;
138 int32_t max_transfer_size;
139 int32_t max_packet_count;
140 int32_t host_channels;
141 int32_t dev_endpoints;
143 int32_t phy_utmi_width;
144 int32_t phy_ulpi_ddr;
145 int32_t phy_ulpi_ext_vbus;
149 int32_t en_multiple_tx_fifo;
150 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
152 uint32_t tx_thr_length;
153 uint32_t rx_thr_length;
158 int32_t baseline_besl;
161 int32_t ahb_thr_ratio;
171 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
173 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
175 .dma_desc_enable = 0,
176 .dma_burst_size = -1,
178 .host_support_fs_ls_low_power = -1,
179 .host_ls_low_power_phy_clk = -1,
180 .enable_dynamic_fifo = 1,
181 .data_fifo_size = -1,
182 .dev_rx_fifo_size = 0x120,
183 .dev_nperio_tx_fifo_size = 0x10,
184 .dev_perio_tx_fifo_size = {
185 /* dev_perio_tx_fifo_size_1 */
203 .host_rx_fifo_size = -1,
204 .host_nperio_tx_fifo_size = -1,
205 .host_perio_tx_fifo_size = -1,
206 .max_transfer_size = -1,
207 .max_packet_count = -1,
211 .phy_utmi_width = -1,
213 .phy_ulpi_ext_vbus = -1,
217 .en_multiple_tx_fifo = -1,
218 .dev_tx_fifo_size = {
219 /* dev_tx_fifo_size */
257 #ifdef CONFIG_USB20_HOST
258 static struct dwc_otg_driver_module_params dwc_host_module_params = {
260 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
262 .dma_desc_enable = 0,
263 .dma_burst_size = -1,
265 .host_support_fs_ls_low_power = -1,
266 .host_ls_low_power_phy_clk = -1,
267 .enable_dynamic_fifo = -1,
268 .data_fifo_size = -1,
269 .dev_rx_fifo_size = -1,
270 .dev_nperio_tx_fifo_size = -1,
271 .dev_perio_tx_fifo_size = {
272 /* dev_perio_tx_fifo_size_1 */
290 .host_rx_fifo_size = -1,
291 .host_nperio_tx_fifo_size = -1,
292 .host_perio_tx_fifo_size = -1,
293 .max_transfer_size = -1,
294 .max_packet_count = -1,
298 .phy_utmi_width = -1,
300 .phy_ulpi_ext_vbus = -1,
304 .en_multiple_tx_fifo = -1,
305 .dev_tx_fifo_size = {
306 /* dev_tx_fifo_size */
346 * This function shows the Driver Version.
348 static ssize_t version_show(struct device_driver *dev, char *buf)
350 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
354 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
357 * Global Debug Level Mask.
359 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
362 * This function shows the driver Debug Level.
364 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
366 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
370 * This function stores the driver Debug Level.
372 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
375 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
379 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
382 extern void hcd_start(dwc_otg_core_if_t *core_if);
383 extern struct usb_hub *g_dwc_otg_root_hub20;
384 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
386 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
388 dwc_otg_device_t *otg_dev = core_if->otg_dev;
389 dctl_data_t dctl = {.d32 = 0 };
392 if (core_if->op_state == A_HOST) {
393 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
396 core_if->op_state = A_HOST;
398 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
399 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
400 dctl.b.sftdiscon = 1;
401 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
403 local_irq_save(flags);
404 cil_pcd_stop(core_if);
406 * Initialize the Core for Host mode.
409 dwc_otg_core_init(core_if);
410 dwc_otg_enable_global_interrupts(core_if);
411 cil_hcd_start(core_if);
412 local_irq_restore(flags);
415 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
417 dwc_otg_device_t *otg_dev = core_if->otg_dev;
420 local_irq_save(flags);
422 if (core_if->op_state == B_PERIPHERAL) {
424 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
427 core_if->op_state = B_PERIPHERAL;
428 cil_hcd_stop(core_if);
429 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
430 otg_dev->pcd->phy_suspend = 1;
431 otg_dev->pcd->vbus_status = 0;
432 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
434 /* Reset the Controller */
435 dwc_otg_core_reset(core_if);
437 dwc_otg_core_init(core_if);
438 dwc_otg_disable_global_interrupts(core_if);
439 cil_pcd_start(core_if);
441 local_irq_restore(flags);
444 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
446 gusbcfg_data_t usbcfg = {.d32 = 0 };
447 printk("!!!dwc_otg_set_force_mode\n");
448 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
450 case USB_MODE_FORCE_HOST:
451 usbcfg.b.force_host_mode = 1;
452 usbcfg.b.force_dev_mode = 0;
454 case USB_MODE_FORCE_DEVICE:
455 usbcfg.b.force_host_mode = 0;
456 usbcfg.b.force_dev_mode = 1;
458 case USB_MODE_NORMAL:
459 usbcfg.b.force_host_mode = 0;
460 usbcfg.b.force_dev_mode = 0;
463 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
466 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
468 dwc_otg_device_t *otg_dev = g_otgdev;
469 dwc_otg_core_if_t *core_if = otg_dev->core_if;
471 return sprintf(buf, "%d\n", core_if->usb_mode);
474 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
477 int new_mode = simple_strtoul(buf, NULL, 16);
478 dwc_otg_device_t *otg_dev = g_otgdev;
479 dwc_otg_core_if_t *core_if;
480 struct dwc_otg_platform_data *pldata;
485 core_if = otg_dev->core_if;
486 pldata = otg_dev->pldata;
488 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
490 if (core_if->usb_mode == new_mode) {
494 if (pldata->phy_status == USB_PHY_SUSPEND) {
495 pldata->clock_enable(pldata, 1);
496 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
500 case USB_MODE_FORCE_HOST:
501 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
503 core_if->usb_mode = new_mode;
504 dwc_otg_force_host(core_if);
505 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
506 core_if->usb_mode = new_mode;
507 if (dwc_otg_is_host_mode(core_if))
508 dwc_otg_set_force_mode(core_if, new_mode);
510 dwc_otg_force_host(core_if);
514 case USB_MODE_FORCE_DEVICE:
515 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
516 core_if->usb_mode = new_mode;
517 dwc_otg_force_device(core_if);
518 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
519 core_if->usb_mode = new_mode;
520 if (dwc_otg_is_device_mode(core_if))
521 dwc_otg_set_force_mode(core_if, new_mode);
523 dwc_otg_force_device(core_if);
527 case USB_MODE_NORMAL:
528 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
529 core_if->usb_mode = new_mode;
530 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
531 dwc_otg_set_force_mode(core_if, new_mode);
533 if (dwc_otg_is_host_mode(core_if)) {
534 dwc_otg_force_host(core_if);
536 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
538 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
539 core_if->usb_mode = new_mode;
540 dwc_otg_set_force_mode(core_if, new_mode);
542 if (dwc_otg_is_device_mode(core_if)) {
543 dwc_otg_force_device(core_if);
554 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
555 force_usb_mode_store);
557 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
560 dwc_otg_device_t *otg_dev = g_otgdev;
561 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
562 return sprintf(_buf, "%d\n", _pcd->conn_en);
566 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
567 const char *_buf, size_t _count)
569 int enable = simple_strtoul(_buf, NULL, 10);
570 dwc_otg_device_t *otg_dev = g_otgdev;
571 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
572 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
574 _pcd->conn_en = enable;
578 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
579 dwc_otg_conn_en_store);
581 /* used for product vbus power control, SDK not need.
582 * If dwc_otg is host mode, enable vbus power.
583 * If dwc_otg is device mode, disable vbus power.
584 * return 1 - host mode, 0 - device mode.
586 int dwc_otg_usb_state(void)
588 dwc_otg_device_t *otg_dev = g_otgdev;
591 /* op_state is A_HOST */
592 if (1 == otg_dev->core_if->op_state)
594 /* op_state is B_PERIPHERAL */
595 else if (4 == otg_dev->core_if->op_state)
600 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
604 EXPORT_SYMBOL(dwc_otg_usb_state);
606 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
608 dwc_otg_device_t *otg_dev = g_otgdev;
611 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
613 return sprintf(_buf, "%d\n", 0);
616 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
618 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
620 dwc_otg_device_t *otg_dev = g_otgdev;
621 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
622 return sprintf(_buf, "%d\n", _pcd->vbus_status);
625 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
628 * This function is called during module intialization
629 * to pass module parameters to the DWC_OTG CORE.
631 static int set_parameters(dwc_otg_core_if_t *core_if,
632 struct dwc_otg_driver_module_params module_params)
637 if (module_params.otg_cap != -1) {
639 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
641 if (module_params.dma_enable != -1) {
643 dwc_otg_set_param_dma_enable(core_if,
644 module_params.dma_enable);
646 if (module_params.dma_desc_enable != -1) {
648 dwc_otg_set_param_dma_desc_enable(core_if,
649 module_params.dma_desc_enable);
651 if (module_params.opt != -1) {
652 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
654 if (module_params.dma_burst_size != -1) {
656 dwc_otg_set_param_dma_burst_size(core_if,
657 module_params.dma_burst_size);
659 if (module_params.host_support_fs_ls_low_power != -1) {
661 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
662 module_params.host_support_fs_ls_low_power);
664 if (module_params.enable_dynamic_fifo != -1) {
666 dwc_otg_set_param_enable_dynamic_fifo(core_if,
667 module_params.enable_dynamic_fifo);
669 if (module_params.data_fifo_size != -1) {
671 dwc_otg_set_param_data_fifo_size(core_if,
672 module_params.data_fifo_size);
674 if (module_params.dev_rx_fifo_size != -1) {
676 dwc_otg_set_param_dev_rx_fifo_size(core_if,
677 module_params.dev_rx_fifo_size);
679 if (module_params.dev_nperio_tx_fifo_size != -1) {
681 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
682 module_params.dev_nperio_tx_fifo_size);
684 if (module_params.host_rx_fifo_size != -1) {
686 dwc_otg_set_param_host_rx_fifo_size(core_if,
690 if (module_params.host_nperio_tx_fifo_size != -1) {
692 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
693 module_params.host_nperio_tx_fifo_size);
695 if (module_params.host_perio_tx_fifo_size != -1) {
697 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
698 module_params.host_perio_tx_fifo_size);
700 if (module_params.max_transfer_size != -1) {
702 dwc_otg_set_param_max_transfer_size(core_if,
703 module_params.max_transfer_size);
705 if (module_params.max_packet_count != -1) {
707 dwc_otg_set_param_max_packet_count(core_if,
708 module_params.max_packet_count);
710 if (module_params.host_channels != -1) {
712 dwc_otg_set_param_host_channels(core_if,
713 module_params.host_channels);
715 if (module_params.dev_endpoints != -1) {
717 dwc_otg_set_param_dev_endpoints(core_if,
718 module_params.dev_endpoints);
720 if (module_params.phy_type != -1) {
722 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
724 if (module_params.speed != -1) {
725 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
727 if (module_params.host_ls_low_power_phy_clk != -1) {
729 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
730 module_params.host_ls_low_power_phy_clk);
732 if (module_params.phy_ulpi_ddr != -1) {
734 dwc_otg_set_param_phy_ulpi_ddr(core_if,
735 module_params.phy_ulpi_ddr);
737 if (module_params.phy_ulpi_ext_vbus != -1) {
739 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
740 module_params.phy_ulpi_ext_vbus);
742 if (module_params.phy_utmi_width != -1) {
744 dwc_otg_set_param_phy_utmi_width(core_if,
745 module_params.phy_utmi_width);
747 if (module_params.ulpi_fs_ls != -1) {
749 dwc_otg_set_param_ulpi_fs_ls(core_if,
750 module_params.ulpi_fs_ls);
752 if (module_params.ts_dline != -1) {
754 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
756 if (module_params.i2c_enable != -1) {
758 dwc_otg_set_param_i2c_enable(core_if,
759 module_params.i2c_enable);
761 if (module_params.en_multiple_tx_fifo != -1) {
763 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
764 module_params.en_multiple_tx_fifo);
766 for (i = 0; i < 15; i++) {
767 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
769 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
770 module_params.dev_perio_tx_fifo_size
775 for (i = 0; i < 15; i++) {
776 if (module_params.dev_tx_fifo_size[i] != -1) {
777 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
778 module_params.dev_tx_fifo_size
782 if (module_params.thr_ctl != -1) {
784 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
786 if (module_params.mpi_enable != -1) {
788 dwc_otg_set_param_mpi_enable(core_if,
789 module_params.mpi_enable);
791 if (module_params.pti_enable != -1) {
793 dwc_otg_set_param_pti_enable(core_if,
794 module_params.pti_enable);
796 if (module_params.lpm_enable != -1) {
798 dwc_otg_set_param_lpm_enable(core_if,
799 module_params.lpm_enable);
801 if (module_params.besl_enable != -1) {
803 dwc_otg_set_param_besl_enable(core_if,
804 module_params.besl_enable);
806 if (module_params.baseline_besl != -1) {
808 dwc_otg_set_param_baseline_besl(core_if,
809 module_params.baseline_besl);
811 if (module_params.deep_besl != -1) {
813 dwc_otg_set_param_deep_besl(core_if,
814 module_params.deep_besl);
816 if (module_params.ic_usb_cap != -1) {
818 dwc_otg_set_param_ic_usb_cap(core_if,
819 module_params.ic_usb_cap);
821 if (module_params.tx_thr_length != -1) {
823 dwc_otg_set_param_tx_thr_length(core_if,
827 if (module_params.rx_thr_length != -1) {
829 dwc_otg_set_param_rx_thr_length(core_if,
830 module_params.rx_thr_length);
832 if (module_params.ahb_thr_ratio != -1) {
834 dwc_otg_set_param_ahb_thr_ratio(core_if,
838 if (module_params.power_down != -1) {
840 dwc_otg_set_param_power_down(core_if,
841 module_params.power_down);
843 if (module_params.reload_ctl != -1) {
845 dwc_otg_set_param_reload_ctl(core_if,
846 module_params.reload_ctl);
849 if (module_params.dev_out_nak != -1) {
851 dwc_otg_set_param_dev_out_nak(core_if,
852 module_params.dev_out_nak);
855 if (module_params.cont_on_bna != -1) {
857 dwc_otg_set_param_cont_on_bna(core_if,
858 module_params.cont_on_bna);
861 if (module_params.ahb_single != -1) {
863 dwc_otg_set_param_ahb_single(core_if,
864 module_params.ahb_single);
867 if (module_params.otg_ver != -1) {
869 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
871 if (module_params.adp_enable != -1) {
873 dwc_otg_set_param_adp_enable(core_if,
874 module_params.adp_enable);
880 * This function is the top level interrupt handler for the Common
881 * (Device and host modes) interrupts.
883 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
885 int32_t retval = IRQ_NONE;
887 retval = dwc_otg_handle_common_intr(dev);
889 /* S3C2410X_CLEAR_EINTPEND(); */
891 return IRQ_RETVAL(retval);
894 #ifdef CONFIG_USB20_HOST
896 * This function is called when a lm_device is unregistered with the
897 * dwc_otg_driver. This happens, for example, when the rmmod command is
898 * executed. The device may or may not be electrically present. If it is
899 * present, the driver stops device processing. Any resources used on behalf
900 * of this device are freed.
904 static int host20_driver_remove(struct platform_device *_dev)
907 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
908 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
911 /* Memory allocation for the dwc_otg_device failed. */
912 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
915 #ifndef DWC_DEVICE_ONLY
919 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
924 #ifndef DWC_HOST_ONLY
928 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
936 if (otg_dev->common_irq_installed) {
937 /* free_irq(_dev->irq, otg_dev); */
938 free_irq(platform_get_irq(_dev, 0), otg_dev);
940 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
945 if (otg_dev->core_if) {
946 dwc_otg_cil_remove(otg_dev->core_if);
948 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
953 * Remove the device attributes
955 dwc_otg_attr_remove(_dev);
960 if (otg_dev->os_dep.base) {
961 iounmap(otg_dev->os_dep.base);
966 * Clear the drvdata pointer.
969 dwc_set_device_platform_data(_dev, 0);
974 static const struct of_device_id usb20_host_of_match[] = {
976 .compatible = "rockchip,rk3188_usb20_host",
977 .data = &usb20host_pdata[RK3188_USB_CTLR],
980 .compatible = "rockchip,rk3288_usb20_host",
981 .data = &usb20host_pdata[RK3288_USB_CTLR],
984 .compatible = "rockchip,rk3036_usb20_host",
985 .data = &usb20host_pdata[RK3036_USB_CTLR],
990 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
993 * This function is called when an lm_device is bound to a
994 * dwc_otg_driver. It creates the driver components required to
995 * control the device (CIL, HCD, and PCD) and it initializes the
996 * device. The driver components are stored in a dwc_otg_device
997 * structure. A reference to the dwc_otg_device is saved in the
998 * lm_device. This allows the driver to access the dwc_otg_device
999 * structure on subsequent calls to driver methods for this device.
1001 * @param _dev Bus device
1003 static int host20_driver_probe(struct platform_device *_dev)
1007 struct resource *res_base;
1008 dwc_otg_device_t *dwc_otg_device;
1009 struct device *dev = &_dev->dev;
1010 struct device_node *node = _dev->dev.of_node;
1011 struct dwc_otg_platform_data *pldata;
1012 struct usb20host_pdata_id *p;
1013 const struct of_device_id *match =
1014 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
1017 p = (struct usb20host_pdata_id *)match->data;
1019 dev_err(dev, "usb20host match failed\n");
1023 dev->platform_data = p->pdata;
1024 pldata = dev->platform_data;
1028 dev_err(dev, "device node not found\n");
1032 if (pldata->hw_init)
1035 if (pldata->clock_init) {
1036 pldata->clock_init(pldata);
1037 pldata->clock_enable(pldata, 1);
1040 if (pldata->phy_suspend)
1041 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1043 if (pldata->soft_reset)
1044 pldata->soft_reset(pldata, RST_POR);
1046 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1048 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1050 if (!dwc_otg_device) {
1051 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1056 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1057 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1060 * Map the DWC_otg Core memory into virtual address space.
1063 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1065 if (!dwc_otg_device->os_dep.base) {
1066 dev_err(&_dev->dev, "ioremap() failed\n");
1067 DWC_FREE(dwc_otg_device);
1071 dev_dbg(&_dev->dev, "base=0x%08x\n",
1072 (unsigned)dwc_otg_device->os_dep.base);
1075 * Initialize driver data to point to the global DWC_otg
1079 dwc_set_device_platform_data(_dev, dwc_otg_device);
1080 pldata->privdata = dwc_otg_device;
1081 dwc_otg_device->pldata = (void *)pldata;
1083 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1085 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1087 if (!dwc_otg_device->core_if) {
1088 dev_err(&_dev->dev, "CIL initialization failed!\n");
1093 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1096 * Attempt to ensure this device is really a DWC_otg Controller.
1097 * Read and verify the SNPSID register contents. The value should be
1098 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1099 * as in "OTG version 2.XX" or "OTG version 3.XX".
1102 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1104 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1106 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1107 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1113 * Validate parameter values.
1115 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1121 * Create Device Attributes in sysfs
1123 dwc_otg_attr_create(_dev);
1126 * Disable the global interrupt until all the interrupt
1127 * handlers are installed.
1129 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1132 * Install the interrupt handler for the common interrupts before
1133 * enabling common interrupts in core_init below.
1135 irq = platform_get_irq(_dev, 0);
1136 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1137 retval = request_irq(irq, dwc_otg_common_irq,
1138 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1140 DWC_ERROR("request of irq%d failed\n", irq);
1144 dwc_otg_device->common_irq_installed = 1;
1148 * Initialize the DWC_otg core.
1149 * In order to reduce the time of initialization,
1150 * we do core soft reset after connection detected.
1152 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1155 * Initialize the HCD
1157 retval = host20_hcd_init(_dev);
1159 DWC_ERROR("hcd_init failed\n");
1160 dwc_otg_device->hcd = NULL;
1164 clk_set_rate(pldata->phyclk_480m, 480000000);
1166 * Enable the global interrupt after all the interrupt
1167 * handlers are installed if there is no ADP support else
1168 * perform initial actions required for Internal ADP logic.
1170 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1171 if (pldata->phy_status == USB_PHY_ENABLED) {
1172 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1174 pldata->clock_enable(pldata, 0);
1176 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1178 dwc_otg_adp_start(dwc_otg_device->core_if,
1179 dwc_otg_is_host_mode(dwc_otg_device->
1185 host20_driver_remove(_dev);
1187 if (pldata->clock_enable)
1188 pldata->clock_enable(pldata, 0);
1194 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1200 static int dwc_otg_driver_resume(struct platform_device *_dev)
1205 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1207 struct device *dev = &_dev->dev;
1208 dwc_otg_device_t *otg_dev = dev->platform_data;
1209 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1210 dctl_data_t dctl = {.d32 = 0 };
1212 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1213 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1214 if (dwc_otg_is_host_mode(core_if)) {
1215 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1216 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1218 /* soft disconnect */
1220 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1221 dctl.b.sftdiscon = 1;
1222 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1225 /* Clear any pending interrupts */
1226 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1231 * This structure defines the methods to be called by a bus driver
1232 * during the lifecycle of a device on that bus. Both drivers and
1233 * devices are registered with a bus driver. The bus driver matches
1234 * devices to drivers based on information in the device and driver
1237 * The probe function is called when the bus driver matches a device
1238 * to this driver. The remove function is called when a device is
1239 * unregistered with the bus driver.
1241 #ifdef CONFIG_USB20_HOST
1242 static struct platform_driver dwc_host_driver = {
1244 .name = (char *)dwc_host20_driver_name,
1245 .of_match_table = of_match_ptr(usb20_host_of_match),
1247 .probe = host20_driver_probe,
1248 .remove = host20_driver_remove,
1249 .suspend = dwc_otg_driver_suspend,
1250 .resume = dwc_otg_driver_resume,
1254 #ifdef CONFIG_USB20_OTG
1256 * This function is called when a lm_device is unregistered with the
1257 * dwc_otg_driver. This happens, for example, when the rmmod command is
1258 * executed. The device may or may not be electrically present. If it is
1259 * present, the driver stops device processing. Any resources used on behalf
1260 * of this device are freed.
1264 static int otg20_driver_remove(struct platform_device *_dev)
1267 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1268 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1271 /* Memory allocation for the dwc_otg_device failed. */
1272 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1275 #ifndef DWC_DEVICE_ONLY
1279 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1284 #ifndef DWC_HOST_ONLY
1288 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1295 if (otg_dev->common_irq_installed) {
1296 /* free_irq(_dev->irq, otg_dev); */
1297 free_irq(platform_get_irq(_dev, 0), otg_dev);
1299 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1304 if (otg_dev->core_if) {
1305 dwc_otg_cil_remove(otg_dev->core_if);
1307 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1312 * Remove the device attributes
1314 dwc_otg_attr_remove(_dev);
1317 * Return the memory.
1319 if (otg_dev->os_dep.base)
1320 iounmap(otg_dev->os_dep.base);
1324 * Clear the drvdata pointer.
1327 dwc_set_device_platform_data(_dev, 0);
1332 static const struct of_device_id usb20_otg_of_match[] = {
1334 .compatible = "rockchip,rk3188_usb20_otg",
1335 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1338 .compatible = "rockchip,rk3288_usb20_otg",
1339 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1342 .compatible = "rockchip,rk3036_usb20_otg",
1343 .data = &usb20otg_pdata[RK3036_USB_CTLR],
1349 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1352 * This function is called when an lm_device is bound to a
1353 * dwc_otg_driver. It creates the driver components required to
1354 * control the device (CIL, HCD, and PCD) and it initializes the
1355 * device. The driver components are stored in a dwc_otg_device
1356 * structure. A reference to the dwc_otg_device is saved in the
1357 * lm_device. This allows the driver to access the dwc_otg_device
1358 * structure on subsequent calls to driver methods for this device.
1360 * @param _dev Bus device
1362 static int otg20_driver_probe(struct platform_device *_dev)
1367 struct resource *res_base;
1368 dwc_otg_device_t *dwc_otg_device;
1369 struct device *dev = &_dev->dev;
1370 struct device_node *node = _dev->dev.of_node;
1371 struct dwc_otg_platform_data *pldata;
1372 struct usb20otg_pdata_id *p;
1373 const struct of_device_id *match =
1374 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1377 p = (struct usb20otg_pdata_id *)match->data;
1379 dev_err(dev, "usb20otg match failed\n");
1383 dev->platform_data = p->pdata;
1384 /* dev->platform_data = &usb20otg_pdata; */
1385 pldata = dev->platform_data;
1389 dev_err(dev, "device node not found\n");
1392 /*todo : move to usbdev_rk-XX.c */
1393 if (pldata->hw_init)
1396 if (pldata->clock_init) {
1397 pldata->clock_init(pldata);
1398 pldata->clock_enable(pldata, 1);
1401 if (pldata->phy_suspend)
1402 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1404 if (pldata->dwc_otg_uart_mode)
1405 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1407 /* do reset later, because reset need about
1408 * 100ms to ensure otg id state change.
1411 if(pldata->soft_reset)
1412 pldata->soft_reset();
1416 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1418 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1420 if (!dwc_otg_device) {
1421 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1426 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1427 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1430 * Map the DWC_otg Core memory into virtual address space.
1433 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1435 if (!dwc_otg_device->os_dep.base) {
1436 dev_err(&_dev->dev, "ioremap() failed\n");
1437 DWC_FREE(dwc_otg_device);
1441 dev_dbg(&_dev->dev, "base=0x%08x\n",
1442 (unsigned)dwc_otg_device->os_dep.base);
1445 * Initialize driver data to point to the global DWC_otg
1449 g_otgdev = dwc_otg_device;
1450 pldata->privdata = dwc_otg_device;
1451 dwc_otg_device->pldata = pldata;
1453 dwc_set_device_platform_data(_dev, dwc_otg_device);
1455 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1457 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1458 if (!dwc_otg_device->core_if) {
1459 dev_err(&_dev->dev, "CIL initialization failed!\n");
1464 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1466 * Attempt to ensure this device is really a DWC_otg Controller.
1467 * Read and verify the SNPSID register contents. The value should be
1468 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1469 * as in "OTG version 2.XX" or "OTG version 3.XX".
1472 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1474 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1476 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1477 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1483 * Validate parameter values.
1485 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1491 * Create Device Attributes in sysfs
1493 dwc_otg_attr_create(_dev);
1496 * Disable the global interrupt until all the interrupt
1497 * handlers are installed.
1499 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1502 * Install the interrupt handler for the common interrupts before
1503 * enabling common interrupts in core_init below.
1505 irq = platform_get_irq(_dev, 0);
1506 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1507 retval = request_irq(irq, dwc_otg_common_irq,
1508 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1510 DWC_ERROR("request of irq%d failed\n", irq);
1514 dwc_otg_device->common_irq_installed = 1;
1518 * Initialize the DWC_otg core.
1519 * In order to reduce the time of initialization,
1520 * we do core soft reset after connection detected.
1522 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1525 * 0 - USB_MODE_NORMAL
1526 * 1 - USB_MODE_FORCE_HOST
1527 * 2 - USB_MODE_FORCE_DEVICE
1529 of_property_read_u32(node, "rockchip,usb-mode", &val);
1530 dwc_otg_device->core_if->usb_mode = val;
1532 #ifndef DWC_HOST_ONLY
1534 * Initialize the PCD
1536 retval = pcd_init(_dev);
1538 DWC_ERROR("pcd_init failed\n");
1539 dwc_otg_device->pcd = NULL;
1543 #ifndef DWC_DEVICE_ONLY
1545 * Initialize the HCD
1547 retval = otg20_hcd_init(_dev);
1549 DWC_ERROR("hcd_init failed\n");
1550 dwc_otg_device->hcd = NULL;
1555 * Enable the global interrupt after all the interrupt
1556 * handlers are installed if there is no ADP support else
1557 * perform initial actions required for Internal ADP logic.
1559 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1560 if (pldata->phy_status == USB_PHY_ENABLED) {
1561 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1563 pldata->clock_enable(pldata, 0);
1565 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1567 dwc_otg_adp_start(dwc_otg_device->core_if,
1568 dwc_otg_is_host_mode(dwc_otg_device->
1574 otg20_driver_remove(_dev);
1577 if (pldata->clock_enable)
1578 pldata->clock_enable(pldata, 0);
1583 static struct platform_driver dwc_otg_driver = {
1585 .name = (char *)dwc_otg20_driver_name,
1586 .of_match_table = of_match_ptr(usb20_otg_of_match),
1588 .probe = otg20_driver_probe,
1589 .remove = otg20_driver_remove,
1590 .suspend = dwc_otg_driver_suspend,
1591 .resume = dwc_otg_driver_resume,
1592 .shutdown = dwc_otg_driver_shutdown,
1596 void rk_usb_power_up(void)
1598 struct dwc_otg_platform_data *pldata_otg;
1599 struct dwc_otg_platform_data *pldata_host;
1600 struct rkehci_platform_data *pldata_ehci;
1602 if (cpu_is_rk3288()) {
1603 #ifdef CONFIG_RK_USB_UART
1604 /* enable USB bypass UART function */
1605 writel_relaxed(0x00c00000 | usb_to_uart_status,
1606 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1609 /* unset siddq,the analog blocks are powered up */
1610 #ifdef CONFIG_USB20_OTG
1611 pldata_otg = &usb20otg_pdata_rk3288;
1613 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1614 writel_relaxed((0x01 << 13) << 16,
1616 RK3288_GRF_UOC0_CON0);
1619 #ifdef CONFIG_USB20_HOST
1620 pldata_host = &usb20host_pdata_rk3288;
1622 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1623 writel_relaxed((0x01 << 13) << 16,
1625 RK3288_GRF_UOC2_CON0);
1628 #ifdef CONFIG_USB_EHCI_RK
1629 pldata_ehci = &rkehci_pdata_rk3288;
1631 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1632 writel_relaxed((0x01 << 13) << 16,
1634 RK3288_GRF_UOC1_CON0);
1641 void rk_usb_power_down(void)
1643 struct dwc_otg_platform_data *pldata_otg;
1644 struct dwc_otg_platform_data *pldata_host;
1645 struct rkehci_platform_data *pldata_ehci;
1647 if (cpu_is_rk3288()) {
1648 #ifdef CONFIG_RK_USB_UART
1649 /* disable USB bypass UART function */
1650 usb_to_uart_status =
1651 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1652 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1654 /* set siddq,the analog blocks are powered down
1656 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1657 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1658 * and TESTBURNIN are set to 1'b0.
1659 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1660 #ifdef CONFIG_USB20_OTG
1661 pldata_otg = &usb20otg_pdata_rk3288;
1663 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1664 writel_relaxed((0x01 << 13) |
1665 ((0x01 << 13) << 16),
1667 RK3288_GRF_UOC0_CON0);
1670 #ifdef CONFIG_USB20_HOST
1671 pldata_host = &usb20host_pdata_rk3288;
1673 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1674 writel_relaxed((0x01 << 13) |
1675 ((0x01 << 13) << 16),
1677 RK3288_GRF_UOC2_CON0);
1680 #ifdef CONFIG_USB_EHCI_RK
1681 pldata_ehci = &rkehci_pdata_rk3288;
1683 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1684 writel_relaxed((0x01 << 13) |
1685 ((0x01 << 13) << 16),
1687 RK3288_GRF_UOC1_CON0);
1693 EXPORT_SYMBOL(rk_usb_power_up);
1694 EXPORT_SYMBOL(rk_usb_power_down);
1696 * This function is called when the dwc_otg_driver is installed with the
1697 * insmod command. It registers the dwc_otg_driver structure with the
1698 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1699 * to be called. In addition, the bus driver will automatically expose
1700 * attributes defined for the device and driver in the special sysfs file
1705 static int __init dwc_otg_driver_init(void)
1710 #ifdef CONFIG_USB20_OTG
1711 /* register otg20 */
1712 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1713 DWC_DRIVER_VERSION);
1715 retval = platform_driver_register(&dwc_otg_driver);
1717 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1722 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1724 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1726 driver_create_file(&dwc_otg_driver.driver,
1727 &driver_attr_dwc_otg_conn_en);
1729 driver_create_file(&dwc_otg_driver.driver,
1730 &driver_attr_vbus_status);
1732 driver_create_file(&dwc_otg_driver.driver,
1733 &driver_attr_force_usb_mode);
1735 driver_create_file(&dwc_otg_driver.driver,
1736 &driver_attr_op_state);
1740 /* register host20 */
1741 #ifdef CONFIG_USB20_HOST
1742 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1743 DWC_DRIVER_VERSION);
1745 retval = platform_driver_register(&dwc_host_driver);
1747 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1752 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1754 driver_create_file(&dwc_host_driver.driver,
1755 &driver_attr_debuglevel);
1760 module_init(dwc_otg_driver_init);
1763 * This function is called when the driver is removed from the kernel
1764 * with the rmmod command. The driver unregisters itself with its bus
1768 static void __exit dwc_otg_driver_cleanup(void)
1770 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1772 #ifdef CONFIG_USB20_HOST
1774 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1775 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1776 platform_driver_unregister(&dwc_host_driver);
1777 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1780 #ifdef CONFIG_USB20_OTG
1782 driver_remove_file(&dwc_otg_driver.driver,
1783 &driver_attr_dwc_otg_conn_en);
1784 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1785 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1786 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1787 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1788 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1789 platform_driver_unregister(&dwc_otg_driver);
1790 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1794 module_exit(dwc_otg_driver_cleanup);
1796 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1797 MODULE_AUTHOR("Synopsys Inc.");
1798 MODULE_LICENSE("GPL");
1800 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1801 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1802 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1803 MODULE_PARM_DESC(opt, "OPT Mode");
1804 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1805 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1807 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1809 MODULE_PARM_DESC(dma_desc_enable,
1810 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1812 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1814 MODULE_PARM_DESC(dma_burst_size,
1815 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1816 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1817 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1818 module_param_named(host_support_fs_ls_low_power,
1819 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1821 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1822 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1823 module_param_named(host_ls_low_power_phy_clk,
1824 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1825 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1826 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1827 module_param_named(enable_dynamic_fifo,
1828 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1829 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1830 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1832 MODULE_PARM_DESC(data_fifo_size,
1833 "Total number of words in the data FIFO memory 32-32768");
1834 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1836 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1837 module_param_named(dev_nperio_tx_fifo_size,
1838 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1839 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1840 "Number of words in the non-periodic Tx FIFO 16-32768");
1841 module_param_named(dev_perio_tx_fifo_size_1,
1842 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1843 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1844 "Number of words in the periodic Tx FIFO 4-768");
1845 module_param_named(dev_perio_tx_fifo_size_2,
1846 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1847 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1848 "Number of words in the periodic Tx FIFO 4-768");
1849 module_param_named(dev_perio_tx_fifo_size_3,
1850 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1851 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1852 "Number of words in the periodic Tx FIFO 4-768");
1853 module_param_named(dev_perio_tx_fifo_size_4,
1854 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1855 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1856 "Number of words in the periodic Tx FIFO 4-768");
1857 module_param_named(dev_perio_tx_fifo_size_5,
1858 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1859 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1860 "Number of words in the periodic Tx FIFO 4-768");
1861 module_param_named(dev_perio_tx_fifo_size_6,
1862 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1863 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1864 "Number of words in the periodic Tx FIFO 4-768");
1865 module_param_named(dev_perio_tx_fifo_size_7,
1866 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1867 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1868 "Number of words in the periodic Tx FIFO 4-768");
1869 module_param_named(dev_perio_tx_fifo_size_8,
1870 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1871 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1872 "Number of words in the periodic Tx FIFO 4-768");
1873 module_param_named(dev_perio_tx_fifo_size_9,
1874 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1875 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1876 "Number of words in the periodic Tx FIFO 4-768");
1877 module_param_named(dev_perio_tx_fifo_size_10,
1878 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1879 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1880 "Number of words in the periodic Tx FIFO 4-768");
1881 module_param_named(dev_perio_tx_fifo_size_11,
1882 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1883 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1884 "Number of words in the periodic Tx FIFO 4-768");
1885 module_param_named(dev_perio_tx_fifo_size_12,
1886 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1887 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1888 "Number of words in the periodic Tx FIFO 4-768");
1889 module_param_named(dev_perio_tx_fifo_size_13,
1890 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1891 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1892 "Number of words in the periodic Tx FIFO 4-768");
1893 module_param_named(dev_perio_tx_fifo_size_14,
1894 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1895 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1896 "Number of words in the periodic Tx FIFO 4-768");
1897 module_param_named(dev_perio_tx_fifo_size_15,
1898 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1899 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1900 "Number of words in the periodic Tx FIFO 4-768");
1901 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1903 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1904 module_param_named(host_nperio_tx_fifo_size,
1905 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1906 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1907 "Number of words in the non-periodic Tx FIFO 16-32768");
1908 module_param_named(host_perio_tx_fifo_size,
1909 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1910 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1911 "Number of words in the host periodic Tx FIFO 16-32768");
1912 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1914 /** @todo Set the max to 512K, modify checks */
1915 MODULE_PARM_DESC(max_transfer_size,
1916 "The maximum transfer size supported in bytes 2047-65535");
1917 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1919 MODULE_PARM_DESC(max_packet_count,
1920 "The maximum number of packets in a transfer 15-511");
1921 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1923 MODULE_PARM_DESC(host_channels,
1924 "The number of host channel registers to use 1-16");
1925 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1927 MODULE_PARM_DESC(dev_endpoints,
1928 "The number of endpoints in addition to EP0 available for device mode 1-15");
1929 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1930 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1931 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1933 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1934 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1935 MODULE_PARM_DESC(phy_ulpi_ddr,
1936 "ULPI at double or single data rate 0=Single 1=Double");
1937 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1939 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1940 "ULPI PHY using internal or external vbus 0=Internal");
1941 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1942 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1943 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1944 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1945 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1946 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1947 module_param_named(debug, g_dbg_lvl, int, 0444);
1948 MODULE_PARM_DESC(debug, "");
1950 module_param_named(en_multiple_tx_fifo,
1951 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1952 MODULE_PARM_DESC(en_multiple_tx_fifo,
1953 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1954 module_param_named(dev_tx_fifo_size_1,
1955 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1956 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1957 module_param_named(dev_tx_fifo_size_2,
1958 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1959 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1960 module_param_named(dev_tx_fifo_size_3,
1961 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1962 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1963 module_param_named(dev_tx_fifo_size_4,
1964 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1965 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1966 module_param_named(dev_tx_fifo_size_5,
1967 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1968 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1969 module_param_named(dev_tx_fifo_size_6,
1970 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1971 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1972 module_param_named(dev_tx_fifo_size_7,
1973 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1974 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1975 module_param_named(dev_tx_fifo_size_8,
1976 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1977 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1978 module_param_named(dev_tx_fifo_size_9,
1979 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1980 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1981 module_param_named(dev_tx_fifo_size_10,
1982 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1983 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1984 module_param_named(dev_tx_fifo_size_11,
1985 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1986 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1987 module_param_named(dev_tx_fifo_size_12,
1988 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1989 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1990 module_param_named(dev_tx_fifo_size_13,
1991 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1992 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1993 module_param_named(dev_tx_fifo_size_14,
1994 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1995 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1996 module_param_named(dev_tx_fifo_size_15,
1997 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1998 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2001 MODULE_PARM_DESC(thr_ctl,
2002 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2003 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2005 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2006 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2008 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2010 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2011 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2012 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2013 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2015 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2016 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2017 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2019 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2020 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2021 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2023 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2024 MODULE_PARM_DESC(ic_usb_cap,
2025 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2026 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2028 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2029 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2030 MODULE_PARM_DESC(power_down, "Power Down Mode");
2031 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2032 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2033 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2034 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2035 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2036 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2037 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2038 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2039 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2040 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2041 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2042 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2044 /** @page "Module Parameters"
2046 * The following parameters may be specified when starting the module.
2047 * These parameters define how the DWC_otg controller should be
2048 * configured. Parameter values are passed to the CIL initialization
2049 * function dwc_otg_cil_init
2051 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2055 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2059 <td>Specifies the OTG capabilities. The driver will automatically detect the
2060 value for this parameter if none is specified.
2061 - 0: HNP and SRP capable (default, if available)
2062 - 1: SRP Only capable
2063 - 2: No HNP/SRP capable
2068 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2069 The driver will automatically detect the value for this parameter if none is
2072 - 1: DMA (default, if available)
2076 <td>dma_burst_size</td>
2077 <td>The DMA Burst size (applicable only for External DMA Mode).
2078 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2083 <td>Specifies the maximum speed of operation in host and device mode. The
2084 actual speed depends on the speed of the attached device and the value of
2086 - 0: High Speed (default)
2091 <td>host_support_fs_ls_low_power</td>
2092 <td>Specifies whether low power mode is supported when attached to a Full
2093 Speed or Low Speed device in host mode.
2094 - 0: Don't support low power mode (default)
2095 - 1: Support low power mode
2099 <td>host_ls_low_power_phy_clk</td>
2100 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2101 Speed device in host mode. This parameter is applicable only if
2102 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2103 - 0: 48 MHz (default)
2108 <td>enable_dynamic_fifo</td>
2109 <td> Specifies whether FIFOs may be resized by the driver software.
2110 - 0: Use cC FIFO size parameters
2111 - 1: Allow dynamic FIFO sizing (default)
2115 <td>data_fifo_size</td>
2116 <td>Total number of 4-byte words in the data FIFO memory. This memory
2117 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2118 - Values: 32 to 32768 (default 8192)
2120 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2124 <td>dev_rx_fifo_size</td>
2125 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2126 FIFO sizing is enabled.
2127 - Values: 16 to 32768 (default 1064)
2131 <td>dev_nperio_tx_fifo_size</td>
2132 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2133 dynamic FIFO sizing is enabled.
2134 - Values: 16 to 32768 (default 1024)
2138 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2139 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2140 when dynamic FIFO sizing is enabled.
2141 - Values: 4 to 768 (default 256)
2145 <td>host_rx_fifo_size</td>
2146 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2148 - Values: 16 to 32768 (default 1024)
2152 <td>host_nperio_tx_fifo_size</td>
2153 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2154 dynamic FIFO sizing is enabled in the core.
2155 - Values: 16 to 32768 (default 1024)
2159 <td>host_perio_tx_fifo_size</td>
2160 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2162 - Values: 16 to 32768 (default 1024)
2166 <td>max_transfer_size</td>
2167 <td>The maximum transfer size supported in bytes.
2168 - Values: 2047 to 65,535 (default 65,535)
2172 <td>max_packet_count</td>
2173 <td>The maximum number of packets in a transfer.
2174 - Values: 15 to 511 (default 511)
2178 <td>host_channels</td>
2179 <td>The number of host channel registers to use.
2180 - Values: 1 to 16 (default 12)
2182 Note: The FPGA configuration supports a maximum of 12 host channels.
2186 <td>dev_endpoints</td>
2187 <td>The number of endpoints in addition to EP0 available for device mode
2189 - Values: 1 to 15 (default 6 IN and OUT)
2191 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2197 <td>Specifies the type of PHY interface to use. By default, the driver will
2198 automatically detect the phy_type.
2200 - 1: UTMI+ (default, if available)
2205 <td>phy_utmi_width</td>
2206 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2207 phy_type of UTMI+. Also, this parameter is applicable only if the
2208 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2209 core has been configured to work at either data path width.
2210 - Values: 8 or 16 bits (default 16)
2214 <td>phy_ulpi_ddr</td>
2215 <td>Specifies whether the ULPI operates at double or single data rate. This
2216 parameter is only applicable if phy_type is ULPI.
2217 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2218 - 1: double data rate ULPI interface with 4 bit wide data bus
2223 <td>Specifies whether to use the I2C interface for full speed PHY. This
2224 parameter is only applicable if PHY_TYPE is FS.
2225 - 0: Disabled (default)
2231 <td>Specifies whether to use ULPI FS/LS mode only.
2232 - 0: Disabled (default)
2238 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2239 - 0: Disabled (default)
2244 <td>en_multiple_tx_fifo</td>
2245 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2246 The driver will automatically detect the value for this parameter if none is
2249 - 1: Enabled (default, if available)
2253 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2254 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2255 when dynamic FIFO sizing is enabled.
2256 - Values: 4 to 768 (default 256)
2260 <td>tx_thr_length</td>
2261 <td>Transmit Threshold length in 32 bit double words
2262 - Values: 8 to 128 (default 64)
2266 <td>rx_thr_length</td>
2267 <td>Receive Threshold length in 32 bit double words
2268 - Values: 8 to 128 (default 64)
2273 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2274 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2275 Rx transfers accordingly.
2276 The driver will automatically detect the value for this parameter if none is
2278 - Values: 0 to 7 (default 0)
2279 Bit values indicate:
2280 - 0: Thresholding disabled
2281 - 1: Thresholding enabled
2285 <td>dma_desc_enable</td>
2286 <td>Specifies whether to enable Descriptor DMA mode.
2287 The driver will automatically detect the value for this parameter if none is
2289 - 0: Descriptor DMA disabled
2290 - 1: Descriptor DMA (default, if available)
2295 <td>Specifies whether to enable MPI enhancement mode.
2296 The driver will automatically detect the value for this parameter if none is
2298 - 0: MPI disabled (default)
2304 <td>Specifies whether to enable PTI enhancement support.
2305 The driver will automatically detect the value for this parameter if none is
2307 - 0: PTI disabled (default)
2313 <td>Specifies whether to enable LPM support.
2314 The driver will automatically detect the value for this parameter if none is
2317 - 1: LPM enable (default, if available)
2321 <td>besl_enable</td>
2322 <td>Specifies whether to enable LPM Errata support.
2323 The driver will automatically detect the value for this parameter if none is
2325 - 0: LPM Errata disabled (default)
2326 - 1: LPM Errata enable
2330 <td>baseline_besl</td>
2331 <td>Specifies the baseline besl value.
2332 - Values: 0 to 15 (default 0)
2337 <td>Specifies the deep besl value.
2338 - Values: 0 to 15 (default 15)
2343 <td>Specifies whether to enable IC_USB capability.
2344 The driver will automatically detect the value for this parameter if none is
2346 - 0: IC_USB disabled (default, if available)
2351 <td>ahb_thr_ratio</td>
2352 <td>Specifies AHB Threshold ratio.
2353 - Values: 0 to 3 (default 0)
2358 <td>Specifies Power Down(Hibernation) Mode.
2359 The driver will automatically detect the value for this parameter if none is
2361 - 0: Power Down disabled (default)
2362 - 2: Power Down enabled
2367 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2368 run time. The driver will automatically detect the value for this parameter if
2369 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2370 the core might misbehave.
2371 - 0: Reload Control disabled (default)
2372 - 1: Reload Control enabled
2376 <td>dev_out_nak</td>
2377 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2378 The driver will automatically detect the value for this parameter if
2379 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2380 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2381 - 1: The core sets NAK after Bulk OUT transfer complete
2385 <td>cont_on_bna</td>
2386 <td>Specifies whether Enable Continue on BNA enabled or no.
2387 After receiving BNA interrupt the core disables the endpoint,when the
2388 endpoint is re-enabled by the application the
2389 - 0: Core starts processing from the DOEPDMA descriptor (default)
2390 - 1: Core starts processing from the descriptor which received the BNA.
2391 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2396 <td>This bit when programmed supports SINGLE transfers for remainder data
2397 in a transfer for DMA mode of operation.
2398 - 0: The remainder data will be sent using INCR burst size (default)
2399 - 1: The remainder data will be sent using SINGLE burst size.
2404 <td>Specifies whether ADP feature is enabled.
2405 The driver will automatically detect the value for this parameter if none is
2407 - 0: ADP feature disabled (default)
2408 - 1: ADP feature enabled
2413 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2415 - 0: OTG 2.0 support disabled (default)
2416 - 1: OTG 2.0 support enabled