1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
90 .name = "rk3036-usb20otg",
91 .pdata = &usb20otg_pdata_rk3036,
94 .name = "rk3126-usb20otg",
95 .pdata = &usb20otg_pdata_rk3126,
101 #ifdef CONFIG_USB20_HOST
102 static struct usb20host_pdata_id usb20host_pdata[] = {
104 .name = "rk3188-usb20host",
105 .pdata = &usb20host_pdata_rk3188,
108 .name = "rk3288-usb20host",
109 .pdata = &usb20host_pdata_rk3288,
112 .name = "rk3036-usb20host",
113 .pdata = &usb20host_pdata_rk3036,
116 .name = "rk3126-usb20host",
117 .pdata = &usb20host_pdata_rk3126,
123 static u32 usb_to_uart_status;
124 /*-------------------------------------------------------------------------*/
125 /* Encapsulate the module parameter settings */
127 struct dwc_otg_driver_module_params {
131 int32_t dma_desc_enable;
132 int32_t dma_burst_size;
134 int32_t host_support_fs_ls_low_power;
135 int32_t host_ls_low_power_phy_clk;
136 int32_t enable_dynamic_fifo;
137 int32_t data_fifo_size;
138 int32_t dev_rx_fifo_size;
139 int32_t dev_nperio_tx_fifo_size;
140 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
141 int32_t host_rx_fifo_size;
142 int32_t host_nperio_tx_fifo_size;
143 int32_t host_perio_tx_fifo_size;
144 int32_t max_transfer_size;
145 int32_t max_packet_count;
146 int32_t host_channels;
147 int32_t dev_endpoints;
149 int32_t phy_utmi_width;
150 int32_t phy_ulpi_ddr;
151 int32_t phy_ulpi_ext_vbus;
155 int32_t en_multiple_tx_fifo;
156 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
158 uint32_t tx_thr_length;
159 uint32_t rx_thr_length;
164 int32_t baseline_besl;
167 int32_t ahb_thr_ratio;
177 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
179 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
181 .dma_desc_enable = 0,
182 .dma_burst_size = -1,
184 .host_support_fs_ls_low_power = -1,
185 .host_ls_low_power_phy_clk = -1,
186 .enable_dynamic_fifo = 1,
187 .data_fifo_size = -1,
188 .dev_rx_fifo_size = 0x120,
189 .dev_nperio_tx_fifo_size = 0x10,
190 .dev_perio_tx_fifo_size = {
191 /* dev_perio_tx_fifo_size_1 */
209 .host_rx_fifo_size = -1,
210 .host_nperio_tx_fifo_size = -1,
211 .host_perio_tx_fifo_size = -1,
212 .max_transfer_size = -1,
213 .max_packet_count = -1,
217 .phy_utmi_width = -1,
219 .phy_ulpi_ext_vbus = -1,
223 .en_multiple_tx_fifo = -1,
224 .dev_tx_fifo_size = {
225 /* dev_tx_fifo_size */
263 #ifdef CONFIG_USB20_HOST
264 static struct dwc_otg_driver_module_params dwc_host_module_params = {
266 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
268 .dma_desc_enable = 0,
269 .dma_burst_size = -1,
271 .host_support_fs_ls_low_power = -1,
272 .host_ls_low_power_phy_clk = -1,
273 .enable_dynamic_fifo = -1,
274 .data_fifo_size = -1,
275 .dev_rx_fifo_size = -1,
276 .dev_nperio_tx_fifo_size = -1,
277 .dev_perio_tx_fifo_size = {
278 /* dev_perio_tx_fifo_size_1 */
296 .host_rx_fifo_size = -1,
297 .host_nperio_tx_fifo_size = -1,
298 .host_perio_tx_fifo_size = -1,
299 .max_transfer_size = -1,
300 .max_packet_count = -1,
304 .phy_utmi_width = -1,
306 .phy_ulpi_ext_vbus = -1,
310 .en_multiple_tx_fifo = -1,
311 .dev_tx_fifo_size = {
312 /* dev_tx_fifo_size */
352 * This function shows the Driver Version.
354 static ssize_t version_show(struct device_driver *dev, char *buf)
356 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
360 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
363 * Global Debug Level Mask.
365 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
368 * This function shows the driver Debug Level.
370 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
372 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
376 * This function stores the driver Debug Level.
378 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
381 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
385 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
388 extern void hcd_start(dwc_otg_core_if_t *core_if);
389 extern struct usb_hub *g_dwc_otg_root_hub20;
390 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
392 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
394 dwc_otg_device_t *otg_dev = core_if->otg_dev;
395 dctl_data_t dctl = {.d32 = 0 };
398 if (core_if->op_state == A_HOST) {
399 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
402 core_if->op_state = A_HOST;
404 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
405 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
406 dctl.b.sftdiscon = 1;
407 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
409 local_irq_save(flags);
410 cil_pcd_stop(core_if);
412 * Initialize the Core for Host mode.
415 dwc_otg_core_init(core_if);
416 dwc_otg_enable_global_interrupts(core_if);
417 cil_hcd_start(core_if);
418 local_irq_restore(flags);
421 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
423 dwc_otg_device_t *otg_dev = core_if->otg_dev;
426 local_irq_save(flags);
428 if (core_if->op_state == B_PERIPHERAL) {
430 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
433 core_if->op_state = B_PERIPHERAL;
434 cil_hcd_stop(core_if);
435 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
436 otg_dev->pcd->phy_suspend = 1;
437 otg_dev->pcd->vbus_status = 0;
438 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
440 /* Reset the Controller */
441 dwc_otg_core_reset(core_if);
443 dwc_otg_core_init(core_if);
444 dwc_otg_disable_global_interrupts(core_if);
445 cil_pcd_start(core_if);
447 local_irq_restore(flags);
450 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
452 gusbcfg_data_t usbcfg = {.d32 = 0 };
453 printk("!!!dwc_otg_set_force_mode\n");
454 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
456 case USB_MODE_FORCE_HOST:
457 usbcfg.b.force_host_mode = 1;
458 usbcfg.b.force_dev_mode = 0;
460 case USB_MODE_FORCE_DEVICE:
461 usbcfg.b.force_host_mode = 0;
462 usbcfg.b.force_dev_mode = 1;
464 case USB_MODE_NORMAL:
465 usbcfg.b.force_host_mode = 0;
466 usbcfg.b.force_dev_mode = 0;
469 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
472 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
474 dwc_otg_device_t *otg_dev = g_otgdev;
475 dwc_otg_core_if_t *core_if = otg_dev->core_if;
477 return sprintf(buf, "%d\n", core_if->usb_mode);
480 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
483 int new_mode = simple_strtoul(buf, NULL, 16);
484 dwc_otg_device_t *otg_dev = g_otgdev;
485 dwc_otg_core_if_t *core_if;
486 struct dwc_otg_platform_data *pldata;
491 core_if = otg_dev->core_if;
492 pldata = otg_dev->pldata;
494 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
496 if (core_if->usb_mode == new_mode) {
500 if (pldata->phy_status == USB_PHY_SUSPEND) {
501 pldata->clock_enable(pldata, 1);
502 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
506 case USB_MODE_FORCE_HOST:
507 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
509 core_if->usb_mode = new_mode;
510 dwc_otg_force_host(core_if);
511 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
512 core_if->usb_mode = new_mode;
513 if (dwc_otg_is_host_mode(core_if))
514 dwc_otg_set_force_mode(core_if, new_mode);
516 dwc_otg_force_host(core_if);
520 case USB_MODE_FORCE_DEVICE:
521 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
522 core_if->usb_mode = new_mode;
523 dwc_otg_force_device(core_if);
524 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
525 core_if->usb_mode = new_mode;
526 if (dwc_otg_is_device_mode(core_if))
527 dwc_otg_set_force_mode(core_if, new_mode);
529 dwc_otg_force_device(core_if);
533 case USB_MODE_NORMAL:
534 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
535 core_if->usb_mode = new_mode;
536 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
537 dwc_otg_set_force_mode(core_if, new_mode);
539 if (dwc_otg_is_host_mode(core_if)) {
540 dwc_otg_force_host(core_if);
542 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
544 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
545 core_if->usb_mode = new_mode;
546 dwc_otg_set_force_mode(core_if, new_mode);
548 if (dwc_otg_is_device_mode(core_if)) {
549 dwc_otg_force_device(core_if);
560 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
561 force_usb_mode_store);
563 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
566 dwc_otg_device_t *otg_dev = g_otgdev;
567 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
568 return sprintf(_buf, "%d\n", _pcd->conn_en);
572 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
573 const char *_buf, size_t _count)
575 int enable = simple_strtoul(_buf, NULL, 10);
576 dwc_otg_device_t *otg_dev = g_otgdev;
577 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
578 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
580 _pcd->conn_en = enable;
584 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
585 dwc_otg_conn_en_store);
587 /* used for product vbus power control, SDK not need.
588 * If dwc_otg is host mode, enable vbus power.
589 * If dwc_otg is device mode, disable vbus power.
590 * return 1 - host mode, 0 - device mode.
592 int dwc_otg_usb_state(void)
594 dwc_otg_device_t *otg_dev = g_otgdev;
597 /* op_state is A_HOST */
598 if (1 == otg_dev->core_if->op_state)
600 /* op_state is B_PERIPHERAL */
601 else if (4 == otg_dev->core_if->op_state)
606 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
610 EXPORT_SYMBOL(dwc_otg_usb_state);
612 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
614 dwc_otg_device_t *otg_dev = g_otgdev;
617 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
619 return sprintf(_buf, "%d\n", 0);
622 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
624 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
626 dwc_otg_device_t *otg_dev = g_otgdev;
627 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
628 return sprintf(_buf, "%d\n", _pcd->vbus_status);
631 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
634 * This function is called during module intialization
635 * to pass module parameters to the DWC_OTG CORE.
637 static int set_parameters(dwc_otg_core_if_t *core_if,
638 struct dwc_otg_driver_module_params module_params)
643 if (module_params.otg_cap != -1) {
645 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
647 if (module_params.dma_enable != -1) {
649 dwc_otg_set_param_dma_enable(core_if,
650 module_params.dma_enable);
652 if (module_params.dma_desc_enable != -1) {
654 dwc_otg_set_param_dma_desc_enable(core_if,
655 module_params.dma_desc_enable);
657 if (module_params.opt != -1) {
658 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
660 if (module_params.dma_burst_size != -1) {
662 dwc_otg_set_param_dma_burst_size(core_if,
663 module_params.dma_burst_size);
665 if (module_params.host_support_fs_ls_low_power != -1) {
667 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
668 module_params.host_support_fs_ls_low_power);
670 if (module_params.enable_dynamic_fifo != -1) {
672 dwc_otg_set_param_enable_dynamic_fifo(core_if,
673 module_params.enable_dynamic_fifo);
675 if (module_params.data_fifo_size != -1) {
677 dwc_otg_set_param_data_fifo_size(core_if,
678 module_params.data_fifo_size);
680 if (module_params.dev_rx_fifo_size != -1) {
682 dwc_otg_set_param_dev_rx_fifo_size(core_if,
683 module_params.dev_rx_fifo_size);
685 if (module_params.dev_nperio_tx_fifo_size != -1) {
687 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
688 module_params.dev_nperio_tx_fifo_size);
690 if (module_params.host_rx_fifo_size != -1) {
692 dwc_otg_set_param_host_rx_fifo_size(core_if,
696 if (module_params.host_nperio_tx_fifo_size != -1) {
698 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
699 module_params.host_nperio_tx_fifo_size);
701 if (module_params.host_perio_tx_fifo_size != -1) {
703 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
704 module_params.host_perio_tx_fifo_size);
706 if (module_params.max_transfer_size != -1) {
708 dwc_otg_set_param_max_transfer_size(core_if,
709 module_params.max_transfer_size);
711 if (module_params.max_packet_count != -1) {
713 dwc_otg_set_param_max_packet_count(core_if,
714 module_params.max_packet_count);
716 if (module_params.host_channels != -1) {
718 dwc_otg_set_param_host_channels(core_if,
719 module_params.host_channels);
721 if (module_params.dev_endpoints != -1) {
723 dwc_otg_set_param_dev_endpoints(core_if,
724 module_params.dev_endpoints);
726 if (module_params.phy_type != -1) {
728 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
730 if (module_params.speed != -1) {
731 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
733 if (module_params.host_ls_low_power_phy_clk != -1) {
735 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
736 module_params.host_ls_low_power_phy_clk);
738 if (module_params.phy_ulpi_ddr != -1) {
740 dwc_otg_set_param_phy_ulpi_ddr(core_if,
741 module_params.phy_ulpi_ddr);
743 if (module_params.phy_ulpi_ext_vbus != -1) {
745 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
746 module_params.phy_ulpi_ext_vbus);
748 if (module_params.phy_utmi_width != -1) {
750 dwc_otg_set_param_phy_utmi_width(core_if,
751 module_params.phy_utmi_width);
753 if (module_params.ulpi_fs_ls != -1) {
755 dwc_otg_set_param_ulpi_fs_ls(core_if,
756 module_params.ulpi_fs_ls);
758 if (module_params.ts_dline != -1) {
760 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
762 if (module_params.i2c_enable != -1) {
764 dwc_otg_set_param_i2c_enable(core_if,
765 module_params.i2c_enable);
767 if (module_params.en_multiple_tx_fifo != -1) {
769 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
770 module_params.en_multiple_tx_fifo);
772 for (i = 0; i < 15; i++) {
773 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
775 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
776 module_params.dev_perio_tx_fifo_size
781 for (i = 0; i < 15; i++) {
782 if (module_params.dev_tx_fifo_size[i] != -1) {
783 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
784 module_params.dev_tx_fifo_size
788 if (module_params.thr_ctl != -1) {
790 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
792 if (module_params.mpi_enable != -1) {
794 dwc_otg_set_param_mpi_enable(core_if,
795 module_params.mpi_enable);
797 if (module_params.pti_enable != -1) {
799 dwc_otg_set_param_pti_enable(core_if,
800 module_params.pti_enable);
802 if (module_params.lpm_enable != -1) {
804 dwc_otg_set_param_lpm_enable(core_if,
805 module_params.lpm_enable);
807 if (module_params.besl_enable != -1) {
809 dwc_otg_set_param_besl_enable(core_if,
810 module_params.besl_enable);
812 if (module_params.baseline_besl != -1) {
814 dwc_otg_set_param_baseline_besl(core_if,
815 module_params.baseline_besl);
817 if (module_params.deep_besl != -1) {
819 dwc_otg_set_param_deep_besl(core_if,
820 module_params.deep_besl);
822 if (module_params.ic_usb_cap != -1) {
824 dwc_otg_set_param_ic_usb_cap(core_if,
825 module_params.ic_usb_cap);
827 if (module_params.tx_thr_length != -1) {
829 dwc_otg_set_param_tx_thr_length(core_if,
833 if (module_params.rx_thr_length != -1) {
835 dwc_otg_set_param_rx_thr_length(core_if,
836 module_params.rx_thr_length);
838 if (module_params.ahb_thr_ratio != -1) {
840 dwc_otg_set_param_ahb_thr_ratio(core_if,
844 if (module_params.power_down != -1) {
846 dwc_otg_set_param_power_down(core_if,
847 module_params.power_down);
849 if (module_params.reload_ctl != -1) {
851 dwc_otg_set_param_reload_ctl(core_if,
852 module_params.reload_ctl);
855 if (module_params.dev_out_nak != -1) {
857 dwc_otg_set_param_dev_out_nak(core_if,
858 module_params.dev_out_nak);
861 if (module_params.cont_on_bna != -1) {
863 dwc_otg_set_param_cont_on_bna(core_if,
864 module_params.cont_on_bna);
867 if (module_params.ahb_single != -1) {
869 dwc_otg_set_param_ahb_single(core_if,
870 module_params.ahb_single);
873 if (module_params.otg_ver != -1) {
875 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
877 if (module_params.adp_enable != -1) {
879 dwc_otg_set_param_adp_enable(core_if,
880 module_params.adp_enable);
886 * This function is the top level interrupt handler for the Common
887 * (Device and host modes) interrupts.
889 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
891 int32_t retval = IRQ_NONE;
893 retval = dwc_otg_handle_common_intr(dev);
895 /* S3C2410X_CLEAR_EINTPEND(); */
897 return IRQ_RETVAL(retval);
900 #ifdef CONFIG_USB20_HOST
902 * This function is called when a lm_device is unregistered with the
903 * dwc_otg_driver. This happens, for example, when the rmmod command is
904 * executed. The device may or may not be electrically present. If it is
905 * present, the driver stops device processing. Any resources used on behalf
906 * of this device are freed.
910 static int host20_driver_remove(struct platform_device *_dev)
913 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
914 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
917 /* Memory allocation for the dwc_otg_device failed. */
918 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
921 #ifndef DWC_DEVICE_ONLY
925 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
930 #ifndef DWC_HOST_ONLY
934 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
942 if (otg_dev->common_irq_installed) {
943 /* free_irq(_dev->irq, otg_dev); */
944 free_irq(platform_get_irq(_dev, 0), otg_dev);
946 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
951 if (otg_dev->core_if) {
952 dwc_otg_cil_remove(otg_dev->core_if);
954 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
959 * Remove the device attributes
961 dwc_otg_attr_remove(_dev);
966 if (otg_dev->os_dep.base) {
967 iounmap(otg_dev->os_dep.base);
972 * Clear the drvdata pointer.
975 dwc_set_device_platform_data(_dev, 0);
980 static const struct of_device_id usb20_host_of_match[] = {
982 .compatible = "rockchip,rk3188_usb20_host",
983 .data = &usb20host_pdata[RK3188_USB_CTLR],
986 .compatible = "rockchip,rk3288_usb20_host",
987 .data = &usb20host_pdata[RK3288_USB_CTLR],
990 .compatible = "rockchip,rk3036_usb20_host",
991 .data = &usb20host_pdata[RK3036_USB_CTLR],
994 .compatible = "rockchip,rk3126_usb20_host",
995 .data = &usb20host_pdata[RK3126_USB_CTLR],
1000 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
1003 * This function is called when an lm_device is bound to a
1004 * dwc_otg_driver. It creates the driver components required to
1005 * control the device (CIL, HCD, and PCD) and it initializes the
1006 * device. The driver components are stored in a dwc_otg_device
1007 * structure. A reference to the dwc_otg_device is saved in the
1008 * lm_device. This allows the driver to access the dwc_otg_device
1009 * structure on subsequent calls to driver methods for this device.
1011 * @param _dev Bus device
1013 static int host20_driver_probe(struct platform_device *_dev)
1017 struct resource *res_base;
1018 dwc_otg_device_t *dwc_otg_device;
1019 struct device *dev = &_dev->dev;
1020 struct device_node *node = _dev->dev.of_node;
1021 struct dwc_otg_platform_data *pldata;
1022 struct usb20host_pdata_id *p;
1023 const struct of_device_id *match =
1024 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
1027 p = (struct usb20host_pdata_id *)match->data;
1029 dev_err(dev, "usb20host match failed\n");
1033 dev->platform_data = p->pdata;
1034 pldata = dev->platform_data;
1038 dev_err(dev, "device node not found\n");
1042 if (pldata->hw_init)
1045 if (pldata->clock_init) {
1046 pldata->clock_init(pldata);
1047 pldata->clock_enable(pldata, 1);
1050 if (pldata->phy_suspend)
1051 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1053 if (pldata->soft_reset)
1054 pldata->soft_reset(pldata, RST_POR);
1056 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1058 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1060 if (!dwc_otg_device) {
1061 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1066 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1067 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1070 * Map the DWC_otg Core memory into virtual address space.
1073 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1075 if (!dwc_otg_device->os_dep.base) {
1076 dev_err(&_dev->dev, "ioremap() failed\n");
1077 DWC_FREE(dwc_otg_device);
1081 dev_dbg(&_dev->dev, "base=0x%08x\n",
1082 (unsigned)dwc_otg_device->os_dep.base);
1085 * Initialize driver data to point to the global DWC_otg
1089 dwc_set_device_platform_data(_dev, dwc_otg_device);
1090 pldata->privdata = dwc_otg_device;
1091 dwc_otg_device->pldata = (void *)pldata;
1093 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1095 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1097 if (!dwc_otg_device->core_if) {
1098 dev_err(&_dev->dev, "CIL initialization failed!\n");
1103 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1106 * Attempt to ensure this device is really a DWC_otg Controller.
1107 * Read and verify the SNPSID register contents. The value should be
1108 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1109 * as in "OTG version 2.XX" or "OTG version 3.XX".
1112 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1114 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1116 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1117 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1123 * Validate parameter values.
1125 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1131 * Create Device Attributes in sysfs
1133 dwc_otg_attr_create(_dev);
1136 * Disable the global interrupt until all the interrupt
1137 * handlers are installed.
1139 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1142 * Install the interrupt handler for the common interrupts before
1143 * enabling common interrupts in core_init below.
1145 irq = platform_get_irq(_dev, 0);
1146 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1147 retval = request_irq(irq, dwc_otg_common_irq,
1148 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1150 DWC_ERROR("request of irq%d failed\n", irq);
1154 dwc_otg_device->common_irq_installed = 1;
1158 * Initialize the DWC_otg core.
1159 * In order to reduce the time of initialization,
1160 * we do core soft reset after connection detected.
1162 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1165 * Initialize the HCD
1167 retval = host20_hcd_init(_dev);
1169 DWC_ERROR("hcd_init failed\n");
1170 dwc_otg_device->hcd = NULL;
1174 clk_set_rate(pldata->phyclk_480m, 480000000);
1176 * Enable the global interrupt after all the interrupt
1177 * handlers are installed if there is no ADP support else
1178 * perform initial actions required for Internal ADP logic.
1180 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1181 if (pldata->phy_status == USB_PHY_ENABLED) {
1182 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1184 pldata->clock_enable(pldata, 0);
1186 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1188 dwc_otg_adp_start(dwc_otg_device->core_if,
1189 dwc_otg_is_host_mode(dwc_otg_device->
1195 host20_driver_remove(_dev);
1197 if (pldata->clock_enable)
1198 pldata->clock_enable(pldata, 0);
1204 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1210 static int dwc_otg_driver_resume(struct platform_device *_dev)
1215 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1217 struct device *dev = &_dev->dev;
1218 struct dwc_otg_platform_data *pldata = dev->platform_data;
1219 dwc_otg_device_t *otg_dev = dev->platform_data;
1220 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1221 dctl_data_t dctl = {.d32 = 0 };
1223 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1224 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1226 if( pldata->dwc_otg_uart_mode != NULL)
1227 pldata->dwc_otg_uart_mode( pldata, PHY_USB_MODE);
1228 if(pldata->phy_suspend != NULL)
1229 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1230 if (dwc_otg_is_host_mode(core_if)) {
1231 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1232 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1234 /* soft disconnect */
1236 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1237 dctl.b.sftdiscon = 1;
1238 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1241 /* Clear any pending interrupts */
1242 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1247 * This structure defines the methods to be called by a bus driver
1248 * during the lifecycle of a device on that bus. Both drivers and
1249 * devices are registered with a bus driver. The bus driver matches
1250 * devices to drivers based on information in the device and driver
1253 * The probe function is called when the bus driver matches a device
1254 * to this driver. The remove function is called when a device is
1255 * unregistered with the bus driver.
1257 #ifdef CONFIG_USB20_HOST
1258 static struct platform_driver dwc_host_driver = {
1260 .name = (char *)dwc_host20_driver_name,
1261 .of_match_table = of_match_ptr(usb20_host_of_match),
1263 .probe = host20_driver_probe,
1264 .remove = host20_driver_remove,
1265 .suspend = dwc_otg_driver_suspend,
1266 .resume = dwc_otg_driver_resume,
1270 #ifdef CONFIG_USB20_OTG
1272 * This function is called when a lm_device is unregistered with the
1273 * dwc_otg_driver. This happens, for example, when the rmmod command is
1274 * executed. The device may or may not be electrically present. If it is
1275 * present, the driver stops device processing. Any resources used on behalf
1276 * of this device are freed.
1280 static int otg20_driver_remove(struct platform_device *_dev)
1283 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1284 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1287 /* Memory allocation for the dwc_otg_device failed. */
1288 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1291 #ifndef DWC_DEVICE_ONLY
1295 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1300 #ifndef DWC_HOST_ONLY
1304 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1311 if (otg_dev->common_irq_installed) {
1312 /* free_irq(_dev->irq, otg_dev); */
1313 free_irq(platform_get_irq(_dev, 0), otg_dev);
1315 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1320 if (otg_dev->core_if) {
1321 dwc_otg_cil_remove(otg_dev->core_if);
1323 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1328 * Remove the device attributes
1330 dwc_otg_attr_remove(_dev);
1333 * Return the memory.
1335 if (otg_dev->os_dep.base)
1336 iounmap(otg_dev->os_dep.base);
1340 * Clear the drvdata pointer.
1343 dwc_set_device_platform_data(_dev, 0);
1348 static const struct of_device_id usb20_otg_of_match[] = {
1350 .compatible = "rockchip,rk3188_usb20_otg",
1351 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1354 .compatible = "rockchip,rk3288_usb20_otg",
1355 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1358 .compatible = "rockchip,rk3036_usb20_otg",
1359 .data = &usb20otg_pdata[RK3036_USB_CTLR],
1362 .compatible = "rockchip,rk3126_usb20_otg",
1363 .data = &usb20otg_pdata[RK3126_USB_CTLR],
1369 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1372 * This function is called when an lm_device is bound to a
1373 * dwc_otg_driver. It creates the driver components required to
1374 * control the device (CIL, HCD, and PCD) and it initializes the
1375 * device. The driver components are stored in a dwc_otg_device
1376 * structure. A reference to the dwc_otg_device is saved in the
1377 * lm_device. This allows the driver to access the dwc_otg_device
1378 * structure on subsequent calls to driver methods for this device.
1380 * @param _dev Bus device
1382 static int otg20_driver_probe(struct platform_device *_dev)
1387 struct resource *res_base;
1388 dwc_otg_device_t *dwc_otg_device;
1389 struct device *dev = &_dev->dev;
1390 struct device_node *node = _dev->dev.of_node;
1391 struct dwc_otg_platform_data *pldata;
1392 struct usb20otg_pdata_id *p;
1393 const struct of_device_id *match =
1394 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1397 p = (struct usb20otg_pdata_id *)match->data;
1399 dev_err(dev, "usb20otg match failed\n");
1403 dev->platform_data = p->pdata;
1404 /* dev->platform_data = &usb20otg_pdata; */
1405 pldata = dev->platform_data;
1409 dev_err(dev, "device node not found\n");
1412 /*todo : move to usbdev_rk-XX.c */
1413 if (pldata->hw_init)
1416 if (pldata->clock_init) {
1417 pldata->clock_init(pldata);
1418 pldata->clock_enable(pldata, 1);
1421 if (pldata->phy_suspend)
1422 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1424 if (pldata->dwc_otg_uart_mode)
1425 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1427 /* do reset later, because reset need about
1428 * 100ms to ensure otg id state change.
1431 if(pldata->soft_reset)
1432 pldata->soft_reset();
1436 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1438 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1440 if (!dwc_otg_device) {
1441 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1446 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1447 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1450 * Map the DWC_otg Core memory into virtual address space.
1453 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1455 if (!dwc_otg_device->os_dep.base) {
1456 dev_err(&_dev->dev, "ioremap() failed\n");
1457 DWC_FREE(dwc_otg_device);
1461 dev_dbg(&_dev->dev, "base=0x%08x\n",
1462 (unsigned)dwc_otg_device->os_dep.base);
1465 * Initialize driver data to point to the global DWC_otg
1469 g_otgdev = dwc_otg_device;
1470 pldata->privdata = dwc_otg_device;
1471 dwc_otg_device->pldata = pldata;
1473 dwc_set_device_platform_data(_dev, dwc_otg_device);
1475 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1477 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1478 if (!dwc_otg_device->core_if) {
1479 dev_err(&_dev->dev, "CIL initialization failed!\n");
1484 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1486 * Attempt to ensure this device is really a DWC_otg Controller.
1487 * Read and verify the SNPSID register contents. The value should be
1488 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1489 * as in "OTG version 2.XX" or "OTG version 3.XX".
1492 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1494 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1496 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1497 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1503 * Validate parameter values.
1505 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1511 * Create Device Attributes in sysfs
1513 dwc_otg_attr_create(_dev);
1516 * Disable the global interrupt until all the interrupt
1517 * handlers are installed.
1519 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1522 * Install the interrupt handler for the common interrupts before
1523 * enabling common interrupts in core_init below.
1525 irq = platform_get_irq(_dev, 0);
1526 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1527 retval = request_irq(irq, dwc_otg_common_irq,
1528 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1530 DWC_ERROR("request of irq%d failed\n", irq);
1534 dwc_otg_device->common_irq_installed = 1;
1538 * Initialize the DWC_otg core.
1539 * In order to reduce the time of initialization,
1540 * we do core soft reset after connection detected.
1542 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1545 * 0 - USB_MODE_NORMAL
1546 * 1 - USB_MODE_FORCE_HOST
1547 * 2 - USB_MODE_FORCE_DEVICE
1549 of_property_read_u32(node, "rockchip,usb-mode", &val);
1550 dwc_otg_device->core_if->usb_mode = val;
1552 #ifndef DWC_HOST_ONLY
1554 * Initialize the PCD
1556 retval = pcd_init(_dev);
1558 DWC_ERROR("pcd_init failed\n");
1559 dwc_otg_device->pcd = NULL;
1563 #ifndef DWC_DEVICE_ONLY
1565 * Initialize the HCD
1567 retval = otg20_hcd_init(_dev);
1569 DWC_ERROR("hcd_init failed\n");
1570 dwc_otg_device->hcd = NULL;
1575 * Enable the global interrupt after all the interrupt
1576 * handlers are installed if there is no ADP support else
1577 * perform initial actions required for Internal ADP logic.
1579 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1580 if (pldata->phy_status == USB_PHY_ENABLED) {
1581 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1583 pldata->clock_enable(pldata, 0);
1585 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1587 dwc_otg_adp_start(dwc_otg_device->core_if,
1588 dwc_otg_is_host_mode(dwc_otg_device->
1594 otg20_driver_remove(_dev);
1597 if (pldata->clock_enable)
1598 pldata->clock_enable(pldata, 0);
1603 static struct platform_driver dwc_otg_driver = {
1605 .name = (char *)dwc_otg20_driver_name,
1606 .of_match_table = of_match_ptr(usb20_otg_of_match),
1608 .probe = otg20_driver_probe,
1609 .remove = otg20_driver_remove,
1610 .suspend = dwc_otg_driver_suspend,
1611 .resume = dwc_otg_driver_resume,
1612 .shutdown = dwc_otg_driver_shutdown,
1616 void rk_usb_power_up(void)
1618 struct dwc_otg_platform_data *pldata_otg;
1619 struct dwc_otg_platform_data *pldata_host;
1620 struct rkehci_platform_data *pldata_ehci;
1621 if (cpu_is_rk312x()) {
1622 pldata_otg = &usb20otg_pdata_rk3126;
1623 if (usb_to_uart_status)
1624 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_UART_MODE);
1626 if (cpu_is_rk3288()) {
1627 #ifdef CONFIG_RK_USB_UART
1628 /* enable USB bypass UART function */
1629 writel_relaxed(0x00c00000 | usb_to_uart_status,
1630 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1633 /* unset siddq,the analog blocks are powered up */
1634 #ifdef CONFIG_USB20_OTG
1635 pldata_otg = &usb20otg_pdata_rk3288;
1637 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1638 writel_relaxed((0x01 << 13) << 16,
1640 RK3288_GRF_UOC0_CON0);
1643 #ifdef CONFIG_USB20_HOST
1644 pldata_host = &usb20host_pdata_rk3288;
1646 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1647 writel_relaxed((0x01 << 13) << 16,
1649 RK3288_GRF_UOC2_CON0);
1652 #ifdef CONFIG_USB_EHCI_RK
1653 pldata_ehci = &rkehci_pdata_rk3288;
1655 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1656 writel_relaxed((0x01 << 13) << 16,
1658 RK3288_GRF_UOC1_CON0);
1665 void rk_usb_power_down(void)
1667 struct dwc_otg_platform_data *pldata_otg;
1668 struct dwc_otg_platform_data *pldata_host;
1669 struct rkehci_platform_data *pldata_ehci;
1671 if (cpu_is_rk312x()) {
1672 pldata_otg = &usb20otg_pdata_rk3126;
1673 usb_to_uart_status = pldata_otg->get_status(USB_STATUS_UARTMODE);
1674 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_USB_MODE);
1676 if (cpu_is_rk3288()) {
1677 #ifdef CONFIG_RK_USB_UART
1678 /* disable USB bypass UART function */
1679 usb_to_uart_status =
1680 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1681 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1683 /* set siddq,the analog blocks are powered down
1685 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1686 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1687 * and TESTBURNIN are set to 1'b0.
1688 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1689 #ifdef CONFIG_USB20_OTG
1690 pldata_otg = &usb20otg_pdata_rk3288;
1692 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1693 writel_relaxed((0x01 << 13) |
1694 ((0x01 << 13) << 16),
1696 RK3288_GRF_UOC0_CON0);
1699 #ifdef CONFIG_USB20_HOST
1700 pldata_host = &usb20host_pdata_rk3288;
1702 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1703 writel_relaxed((0x01 << 13) |
1704 ((0x01 << 13) << 16),
1706 RK3288_GRF_UOC2_CON0);
1709 #ifdef CONFIG_USB_EHCI_RK
1710 pldata_ehci = &rkehci_pdata_rk3288;
1712 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1713 writel_relaxed((0x01 << 13) |
1714 ((0x01 << 13) << 16),
1716 RK3288_GRF_UOC1_CON0);
1722 EXPORT_SYMBOL(rk_usb_power_up);
1723 EXPORT_SYMBOL(rk_usb_power_down);
1725 * This function is called when the dwc_otg_driver is installed with the
1726 * insmod command. It registers the dwc_otg_driver structure with the
1727 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1728 * to be called. In addition, the bus driver will automatically expose
1729 * attributes defined for the device and driver in the special sysfs file
1734 static int __init dwc_otg_driver_init(void)
1739 #ifdef CONFIG_USB20_OTG
1740 /* register otg20 */
1741 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1742 DWC_DRIVER_VERSION);
1744 retval = platform_driver_register(&dwc_otg_driver);
1746 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1751 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1753 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1755 driver_create_file(&dwc_otg_driver.driver,
1756 &driver_attr_dwc_otg_conn_en);
1758 driver_create_file(&dwc_otg_driver.driver,
1759 &driver_attr_vbus_status);
1761 driver_create_file(&dwc_otg_driver.driver,
1762 &driver_attr_force_usb_mode);
1764 driver_create_file(&dwc_otg_driver.driver,
1765 &driver_attr_op_state);
1769 /* register host20 */
1770 #ifdef CONFIG_USB20_HOST
1771 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1772 DWC_DRIVER_VERSION);
1774 retval = platform_driver_register(&dwc_host_driver);
1776 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1781 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1783 driver_create_file(&dwc_host_driver.driver,
1784 &driver_attr_debuglevel);
1789 module_init(dwc_otg_driver_init);
1792 * This function is called when the driver is removed from the kernel
1793 * with the rmmod command. The driver unregisters itself with its bus
1797 static void __exit dwc_otg_driver_cleanup(void)
1799 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1801 #ifdef CONFIG_USB20_HOST
1803 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1804 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1805 platform_driver_unregister(&dwc_host_driver);
1806 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1809 #ifdef CONFIG_USB20_OTG
1811 driver_remove_file(&dwc_otg_driver.driver,
1812 &driver_attr_dwc_otg_conn_en);
1813 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1814 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1815 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1816 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1817 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1818 platform_driver_unregister(&dwc_otg_driver);
1819 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1823 module_exit(dwc_otg_driver_cleanup);
1825 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1826 MODULE_AUTHOR("Synopsys Inc.");
1827 MODULE_LICENSE("GPL");
1829 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1830 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1831 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1832 MODULE_PARM_DESC(opt, "OPT Mode");
1833 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1834 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1836 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1838 MODULE_PARM_DESC(dma_desc_enable,
1839 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1841 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1843 MODULE_PARM_DESC(dma_burst_size,
1844 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1845 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1846 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1847 module_param_named(host_support_fs_ls_low_power,
1848 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1850 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1851 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1852 module_param_named(host_ls_low_power_phy_clk,
1853 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1854 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1855 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1856 module_param_named(enable_dynamic_fifo,
1857 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1858 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1859 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1861 MODULE_PARM_DESC(data_fifo_size,
1862 "Total number of words in the data FIFO memory 32-32768");
1863 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1865 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1866 module_param_named(dev_nperio_tx_fifo_size,
1867 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1868 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1869 "Number of words in the non-periodic Tx FIFO 16-32768");
1870 module_param_named(dev_perio_tx_fifo_size_1,
1871 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1872 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1873 "Number of words in the periodic Tx FIFO 4-768");
1874 module_param_named(dev_perio_tx_fifo_size_2,
1875 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1876 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1877 "Number of words in the periodic Tx FIFO 4-768");
1878 module_param_named(dev_perio_tx_fifo_size_3,
1879 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1880 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1881 "Number of words in the periodic Tx FIFO 4-768");
1882 module_param_named(dev_perio_tx_fifo_size_4,
1883 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1884 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1885 "Number of words in the periodic Tx FIFO 4-768");
1886 module_param_named(dev_perio_tx_fifo_size_5,
1887 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1888 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1889 "Number of words in the periodic Tx FIFO 4-768");
1890 module_param_named(dev_perio_tx_fifo_size_6,
1891 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1892 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1893 "Number of words in the periodic Tx FIFO 4-768");
1894 module_param_named(dev_perio_tx_fifo_size_7,
1895 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1896 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1897 "Number of words in the periodic Tx FIFO 4-768");
1898 module_param_named(dev_perio_tx_fifo_size_8,
1899 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1900 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1901 "Number of words in the periodic Tx FIFO 4-768");
1902 module_param_named(dev_perio_tx_fifo_size_9,
1903 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1904 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1905 "Number of words in the periodic Tx FIFO 4-768");
1906 module_param_named(dev_perio_tx_fifo_size_10,
1907 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1908 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1909 "Number of words in the periodic Tx FIFO 4-768");
1910 module_param_named(dev_perio_tx_fifo_size_11,
1911 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1912 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1913 "Number of words in the periodic Tx FIFO 4-768");
1914 module_param_named(dev_perio_tx_fifo_size_12,
1915 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1916 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1917 "Number of words in the periodic Tx FIFO 4-768");
1918 module_param_named(dev_perio_tx_fifo_size_13,
1919 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1920 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1921 "Number of words in the periodic Tx FIFO 4-768");
1922 module_param_named(dev_perio_tx_fifo_size_14,
1923 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1924 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1925 "Number of words in the periodic Tx FIFO 4-768");
1926 module_param_named(dev_perio_tx_fifo_size_15,
1927 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1928 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1929 "Number of words in the periodic Tx FIFO 4-768");
1930 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1932 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1933 module_param_named(host_nperio_tx_fifo_size,
1934 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1935 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1936 "Number of words in the non-periodic Tx FIFO 16-32768");
1937 module_param_named(host_perio_tx_fifo_size,
1938 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1939 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1940 "Number of words in the host periodic Tx FIFO 16-32768");
1941 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1943 /** @todo Set the max to 512K, modify checks */
1944 MODULE_PARM_DESC(max_transfer_size,
1945 "The maximum transfer size supported in bytes 2047-65535");
1946 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1948 MODULE_PARM_DESC(max_packet_count,
1949 "The maximum number of packets in a transfer 15-511");
1950 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1952 MODULE_PARM_DESC(host_channels,
1953 "The number of host channel registers to use 1-16");
1954 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1956 MODULE_PARM_DESC(dev_endpoints,
1957 "The number of endpoints in addition to EP0 available for device mode 1-15");
1958 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1959 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1960 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1962 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1963 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1964 MODULE_PARM_DESC(phy_ulpi_ddr,
1965 "ULPI at double or single data rate 0=Single 1=Double");
1966 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1968 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1969 "ULPI PHY using internal or external vbus 0=Internal");
1970 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1971 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1972 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1973 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1974 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1975 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1976 module_param_named(debug, g_dbg_lvl, int, 0444);
1977 MODULE_PARM_DESC(debug, "");
1979 module_param_named(en_multiple_tx_fifo,
1980 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1981 MODULE_PARM_DESC(en_multiple_tx_fifo,
1982 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1983 module_param_named(dev_tx_fifo_size_1,
1984 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1985 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1986 module_param_named(dev_tx_fifo_size_2,
1987 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1988 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1989 module_param_named(dev_tx_fifo_size_3,
1990 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1991 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1992 module_param_named(dev_tx_fifo_size_4,
1993 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1994 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1995 module_param_named(dev_tx_fifo_size_5,
1996 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1997 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1998 module_param_named(dev_tx_fifo_size_6,
1999 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2000 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2001 module_param_named(dev_tx_fifo_size_7,
2002 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2003 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2004 module_param_named(dev_tx_fifo_size_8,
2005 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2006 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2007 module_param_named(dev_tx_fifo_size_9,
2008 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2009 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2010 module_param_named(dev_tx_fifo_size_10,
2011 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2012 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2013 module_param_named(dev_tx_fifo_size_11,
2014 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2015 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2016 module_param_named(dev_tx_fifo_size_12,
2017 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2018 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2019 module_param_named(dev_tx_fifo_size_13,
2020 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2021 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2022 module_param_named(dev_tx_fifo_size_14,
2023 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2024 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2025 module_param_named(dev_tx_fifo_size_15,
2026 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2027 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2029 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2030 MODULE_PARM_DESC(thr_ctl,
2031 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2032 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2034 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2035 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2037 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2039 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2040 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2041 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2042 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2044 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2045 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2046 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2048 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2049 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2050 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2052 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2053 MODULE_PARM_DESC(ic_usb_cap,
2054 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2055 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2057 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2058 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2059 MODULE_PARM_DESC(power_down, "Power Down Mode");
2060 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2061 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2062 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2063 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2064 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2065 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2066 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2067 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2068 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2069 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2070 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2071 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2073 /** @page "Module Parameters"
2075 * The following parameters may be specified when starting the module.
2076 * These parameters define how the DWC_otg controller should be
2077 * configured. Parameter values are passed to the CIL initialization
2078 * function dwc_otg_cil_init
2080 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2084 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2088 <td>Specifies the OTG capabilities. The driver will automatically detect the
2089 value for this parameter if none is specified.
2090 - 0: HNP and SRP capable (default, if available)
2091 - 1: SRP Only capable
2092 - 2: No HNP/SRP capable
2097 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2098 The driver will automatically detect the value for this parameter if none is
2101 - 1: DMA (default, if available)
2105 <td>dma_burst_size</td>
2106 <td>The DMA Burst size (applicable only for External DMA Mode).
2107 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2112 <td>Specifies the maximum speed of operation in host and device mode. The
2113 actual speed depends on the speed of the attached device and the value of
2115 - 0: High Speed (default)
2120 <td>host_support_fs_ls_low_power</td>
2121 <td>Specifies whether low power mode is supported when attached to a Full
2122 Speed or Low Speed device in host mode.
2123 - 0: Don't support low power mode (default)
2124 - 1: Support low power mode
2128 <td>host_ls_low_power_phy_clk</td>
2129 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2130 Speed device in host mode. This parameter is applicable only if
2131 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2132 - 0: 48 MHz (default)
2137 <td>enable_dynamic_fifo</td>
2138 <td> Specifies whether FIFOs may be resized by the driver software.
2139 - 0: Use cC FIFO size parameters
2140 - 1: Allow dynamic FIFO sizing (default)
2144 <td>data_fifo_size</td>
2145 <td>Total number of 4-byte words in the data FIFO memory. This memory
2146 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2147 - Values: 32 to 32768 (default 8192)
2149 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2153 <td>dev_rx_fifo_size</td>
2154 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2155 FIFO sizing is enabled.
2156 - Values: 16 to 32768 (default 1064)
2160 <td>dev_nperio_tx_fifo_size</td>
2161 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2162 dynamic FIFO sizing is enabled.
2163 - Values: 16 to 32768 (default 1024)
2167 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2168 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2169 when dynamic FIFO sizing is enabled.
2170 - Values: 4 to 768 (default 256)
2174 <td>host_rx_fifo_size</td>
2175 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2177 - Values: 16 to 32768 (default 1024)
2181 <td>host_nperio_tx_fifo_size</td>
2182 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2183 dynamic FIFO sizing is enabled in the core.
2184 - Values: 16 to 32768 (default 1024)
2188 <td>host_perio_tx_fifo_size</td>
2189 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2191 - Values: 16 to 32768 (default 1024)
2195 <td>max_transfer_size</td>
2196 <td>The maximum transfer size supported in bytes.
2197 - Values: 2047 to 65,535 (default 65,535)
2201 <td>max_packet_count</td>
2202 <td>The maximum number of packets in a transfer.
2203 - Values: 15 to 511 (default 511)
2207 <td>host_channels</td>
2208 <td>The number of host channel registers to use.
2209 - Values: 1 to 16 (default 12)
2211 Note: The FPGA configuration supports a maximum of 12 host channels.
2215 <td>dev_endpoints</td>
2216 <td>The number of endpoints in addition to EP0 available for device mode
2218 - Values: 1 to 15 (default 6 IN and OUT)
2220 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2226 <td>Specifies the type of PHY interface to use. By default, the driver will
2227 automatically detect the phy_type.
2229 - 1: UTMI+ (default, if available)
2234 <td>phy_utmi_width</td>
2235 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2236 phy_type of UTMI+. Also, this parameter is applicable only if the
2237 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2238 core has been configured to work at either data path width.
2239 - Values: 8 or 16 bits (default 16)
2243 <td>phy_ulpi_ddr</td>
2244 <td>Specifies whether the ULPI operates at double or single data rate. This
2245 parameter is only applicable if phy_type is ULPI.
2246 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2247 - 1: double data rate ULPI interface with 4 bit wide data bus
2252 <td>Specifies whether to use the I2C interface for full speed PHY. This
2253 parameter is only applicable if PHY_TYPE is FS.
2254 - 0: Disabled (default)
2260 <td>Specifies whether to use ULPI FS/LS mode only.
2261 - 0: Disabled (default)
2267 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2268 - 0: Disabled (default)
2273 <td>en_multiple_tx_fifo</td>
2274 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2275 The driver will automatically detect the value for this parameter if none is
2278 - 1: Enabled (default, if available)
2282 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2283 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2284 when dynamic FIFO sizing is enabled.
2285 - Values: 4 to 768 (default 256)
2289 <td>tx_thr_length</td>
2290 <td>Transmit Threshold length in 32 bit double words
2291 - Values: 8 to 128 (default 64)
2295 <td>rx_thr_length</td>
2296 <td>Receive Threshold length in 32 bit double words
2297 - Values: 8 to 128 (default 64)
2302 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2303 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2304 Rx transfers accordingly.
2305 The driver will automatically detect the value for this parameter if none is
2307 - Values: 0 to 7 (default 0)
2308 Bit values indicate:
2309 - 0: Thresholding disabled
2310 - 1: Thresholding enabled
2314 <td>dma_desc_enable</td>
2315 <td>Specifies whether to enable Descriptor DMA mode.
2316 The driver will automatically detect the value for this parameter if none is
2318 - 0: Descriptor DMA disabled
2319 - 1: Descriptor DMA (default, if available)
2324 <td>Specifies whether to enable MPI enhancement mode.
2325 The driver will automatically detect the value for this parameter if none is
2327 - 0: MPI disabled (default)
2333 <td>Specifies whether to enable PTI enhancement support.
2334 The driver will automatically detect the value for this parameter if none is
2336 - 0: PTI disabled (default)
2342 <td>Specifies whether to enable LPM support.
2343 The driver will automatically detect the value for this parameter if none is
2346 - 1: LPM enable (default, if available)
2350 <td>besl_enable</td>
2351 <td>Specifies whether to enable LPM Errata support.
2352 The driver will automatically detect the value for this parameter if none is
2354 - 0: LPM Errata disabled (default)
2355 - 1: LPM Errata enable
2359 <td>baseline_besl</td>
2360 <td>Specifies the baseline besl value.
2361 - Values: 0 to 15 (default 0)
2366 <td>Specifies the deep besl value.
2367 - Values: 0 to 15 (default 15)
2372 <td>Specifies whether to enable IC_USB capability.
2373 The driver will automatically detect the value for this parameter if none is
2375 - 0: IC_USB disabled (default, if available)
2380 <td>ahb_thr_ratio</td>
2381 <td>Specifies AHB Threshold ratio.
2382 - Values: 0 to 3 (default 0)
2387 <td>Specifies Power Down(Hibernation) Mode.
2388 The driver will automatically detect the value for this parameter if none is
2390 - 0: Power Down disabled (default)
2391 - 2: Power Down enabled
2396 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2397 run time. The driver will automatically detect the value for this parameter if
2398 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2399 the core might misbehave.
2400 - 0: Reload Control disabled (default)
2401 - 1: Reload Control enabled
2405 <td>dev_out_nak</td>
2406 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2407 The driver will automatically detect the value for this parameter if
2408 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2409 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2410 - 1: The core sets NAK after Bulk OUT transfer complete
2414 <td>cont_on_bna</td>
2415 <td>Specifies whether Enable Continue on BNA enabled or no.
2416 After receiving BNA interrupt the core disables the endpoint,when the
2417 endpoint is re-enabled by the application the
2418 - 0: Core starts processing from the DOEPDMA descriptor (default)
2419 - 1: Core starts processing from the descriptor which received the BNA.
2420 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2425 <td>This bit when programmed supports SINGLE transfers for remainder data
2426 in a transfer for DMA mode of operation.
2427 - 0: The remainder data will be sent using INCR burst size (default)
2428 - 1: The remainder data will be sent using SINGLE burst size.
2433 <td>Specifies whether ADP feature is enabled.
2434 The driver will automatically detect the value for this parameter if none is
2436 - 0: ADP feature disabled (default)
2437 - 1: ADP feature enabled
2442 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2444 - 0: OTG 2.0 support disabled (default)
2445 - 1: OTG 2.0 support enabled