1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
80 #ifdef CONFIG_RK_USB_UART
81 static u32 usb_to_uart_status;
83 /*-------------------------------------------------------------------------*/
84 /* Encapsulate the module parameter settings */
86 struct dwc_otg_driver_module_params {
90 int32_t dma_desc_enable;
91 int32_t dma_burst_size;
93 int32_t host_support_fs_ls_low_power;
94 int32_t host_ls_low_power_phy_clk;
95 int32_t enable_dynamic_fifo;
96 int32_t data_fifo_size;
97 int32_t dev_rx_fifo_size;
98 int32_t dev_nperio_tx_fifo_size;
99 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
100 int32_t host_rx_fifo_size;
101 int32_t host_nperio_tx_fifo_size;
102 int32_t host_perio_tx_fifo_size;
103 int32_t max_transfer_size;
104 int32_t max_packet_count;
105 int32_t host_channels;
106 int32_t dev_endpoints;
108 int32_t phy_utmi_width;
109 int32_t phy_ulpi_ddr;
110 int32_t phy_ulpi_ext_vbus;
114 int32_t en_multiple_tx_fifo;
115 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
117 uint32_t tx_thr_length;
118 uint32_t rx_thr_length;
123 int32_t baseline_besl;
126 int32_t ahb_thr_ratio;
136 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
138 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
140 .dma_desc_enable = 0,
141 .dma_burst_size = -1,
143 .host_support_fs_ls_low_power = -1,
144 .host_ls_low_power_phy_clk = -1,
145 .enable_dynamic_fifo = 1,
146 .data_fifo_size = -1,
147 .dev_rx_fifo_size = 0x120,
148 .dev_nperio_tx_fifo_size = 0x10,
149 .dev_perio_tx_fifo_size = {
150 /* dev_perio_tx_fifo_size_1 */
168 .host_rx_fifo_size = -1,
169 .host_nperio_tx_fifo_size = -1,
170 .host_perio_tx_fifo_size = -1,
171 .max_transfer_size = -1,
172 .max_packet_count = -1,
176 .phy_utmi_width = -1,
178 .phy_ulpi_ext_vbus = -1,
182 .en_multiple_tx_fifo = -1,
183 .dev_tx_fifo_size = {
184 /* dev_tx_fifo_size */
222 #ifdef CONFIG_USB20_HOST
223 static struct dwc_otg_driver_module_params dwc_host_module_params = {
225 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
227 .dma_desc_enable = 0,
228 .dma_burst_size = -1,
230 .host_support_fs_ls_low_power = -1,
231 .host_ls_low_power_phy_clk = -1,
232 .enable_dynamic_fifo = -1,
233 .data_fifo_size = -1,
234 .dev_rx_fifo_size = -1,
235 .dev_nperio_tx_fifo_size = -1,
236 .dev_perio_tx_fifo_size = {
237 /* dev_perio_tx_fifo_size_1 */
255 .host_rx_fifo_size = -1,
256 .host_nperio_tx_fifo_size = -1,
257 .host_perio_tx_fifo_size = -1,
258 .max_transfer_size = -1,
259 .max_packet_count = -1,
263 .phy_utmi_width = -1,
265 .phy_ulpi_ext_vbus = -1,
269 .en_multiple_tx_fifo = -1,
270 .dev_tx_fifo_size = {
271 /* dev_tx_fifo_size */
311 * This function shows the Driver Version.
313 static ssize_t version_show(struct device_driver *dev, char *buf)
315 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
319 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
322 * Global Debug Level Mask.
324 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
327 * This function shows the driver Debug Level.
329 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
331 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
335 * This function stores the driver Debug Level.
337 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
340 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
344 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
347 extern void hcd_start(dwc_otg_core_if_t *core_if);
348 extern struct usb_hub *g_dwc_otg_root_hub20;
349 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
351 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
353 dwc_otg_device_t *otg_dev = core_if->otg_dev;
354 dctl_data_t dctl = {.d32 = 0 };
357 if (core_if->op_state == A_HOST) {
358 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
361 core_if->op_state = A_HOST;
363 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
364 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
365 dctl.b.sftdiscon = 1;
366 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
368 local_irq_save(flags);
369 cil_pcd_stop(core_if);
371 * Initialize the Core for Host mode.
374 dwc_otg_core_init(core_if);
375 dwc_otg_enable_global_interrupts(core_if);
376 cil_hcd_start(core_if);
377 local_irq_restore(flags);
380 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
382 dwc_otg_device_t *otg_dev = core_if->otg_dev;
385 local_irq_save(flags);
387 if (core_if->op_state == B_PERIPHERAL) {
389 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
392 core_if->op_state = B_PERIPHERAL;
393 cil_hcd_stop(core_if);
394 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
395 otg_dev->pcd->phy_suspend = 1;
396 otg_dev->pcd->vbus_status = 0;
397 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
399 /* Reset the Controller */
400 dwc_otg_core_reset(core_if);
402 dwc_otg_core_init(core_if);
403 dwc_otg_disable_global_interrupts(core_if);
404 cil_pcd_start(core_if);
406 local_irq_restore(flags);
409 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
411 dwc_otg_device_t *otg_dev = g_otgdev;
412 dwc_otg_core_if_t *core_if = otg_dev->core_if;
414 return sprintf(buf, "%d\n", core_if->usb_mode);
417 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
420 int new_mode = simple_strtoul(buf, NULL, 16);
421 dwc_otg_device_t *otg_dev = g_otgdev;
422 dwc_otg_core_if_t *core_if;
423 struct dwc_otg_platform_data *pldata;
428 core_if = otg_dev->core_if;
429 pldata = otg_dev->pldata;
431 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
433 if (core_if->usb_mode == new_mode) {
437 if (pldata->phy_status == USB_PHY_SUSPEND) {
438 pldata->clock_enable(pldata, 1);
439 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
443 case USB_MODE_FORCE_HOST:
444 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
446 core_if->usb_mode = new_mode;
447 dwc_otg_force_host(core_if);
448 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
449 core_if->usb_mode = new_mode;
450 if (dwc_otg_is_host_mode(core_if))
451 dwc_otg_set_force_mode(core_if, new_mode);
453 dwc_otg_force_host(core_if);
457 case USB_MODE_FORCE_DEVICE:
458 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
459 core_if->usb_mode = new_mode;
460 dwc_otg_force_device(core_if);
461 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
462 core_if->usb_mode = new_mode;
463 if (dwc_otg_is_device_mode(core_if))
464 dwc_otg_set_force_mode(core_if, new_mode);
466 dwc_otg_force_device(core_if);
470 case USB_MODE_NORMAL:
471 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
472 core_if->usb_mode = new_mode;
473 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
474 dwc_otg_set_force_mode(core_if, new_mode);
476 if (dwc_otg_is_host_mode(core_if)) {
477 dwc_otg_force_host(core_if);
479 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
481 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
482 core_if->usb_mode = new_mode;
483 dwc_otg_set_force_mode(core_if, new_mode);
485 if (dwc_otg_is_device_mode(core_if)) {
486 dwc_otg_force_device(core_if);
497 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
498 force_usb_mode_store);
500 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
503 dwc_otg_device_t *otg_dev = g_otgdev;
504 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
505 return sprintf(_buf, "%d\n", _pcd->conn_en);
509 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
510 const char *_buf, size_t _count)
512 int enable = simple_strtoul(_buf, NULL, 10);
513 dwc_otg_device_t *otg_dev = g_otgdev;
514 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
515 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
517 _pcd->conn_en = enable;
521 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
522 dwc_otg_conn_en_store);
524 /* used for product vbus power control, SDK not need.
525 * If dwc_otg is host mode, enable vbus power.
526 * If dwc_otg is device mode, disable vbus power.
527 * return 1 - host mode, 0 - device mode.
529 int dwc_otg_usb_state(void)
531 dwc_otg_device_t *otg_dev = g_otgdev;
534 /* op_state is A_HOST */
535 if (1 == otg_dev->core_if->op_state)
537 /* op_state is B_PERIPHERAL */
538 else if (4 == otg_dev->core_if->op_state)
543 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
547 EXPORT_SYMBOL(dwc_otg_usb_state);
549 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
551 dwc_otg_device_t *otg_dev = g_otgdev;
554 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
556 return sprintf(_buf, "%d\n", 0);
559 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
561 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
563 dwc_otg_device_t *otg_dev = g_otgdev;
564 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
565 return sprintf(_buf, "%d\n", _pcd->vbus_status);
568 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
571 * This function is called during module intialization
572 * to pass module parameters to the DWC_OTG CORE.
574 static int set_parameters(dwc_otg_core_if_t *core_if,
575 struct dwc_otg_driver_module_params module_params)
580 if (module_params.otg_cap != -1) {
582 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
584 if (module_params.dma_enable != -1) {
586 dwc_otg_set_param_dma_enable(core_if,
587 module_params.dma_enable);
589 if (module_params.dma_desc_enable != -1) {
591 dwc_otg_set_param_dma_desc_enable(core_if,
592 module_params.dma_desc_enable);
594 if (module_params.opt != -1) {
595 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
597 if (module_params.dma_burst_size != -1) {
599 dwc_otg_set_param_dma_burst_size(core_if,
600 module_params.dma_burst_size);
602 if (module_params.host_support_fs_ls_low_power != -1) {
604 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
605 module_params.host_support_fs_ls_low_power);
607 if (module_params.enable_dynamic_fifo != -1) {
609 dwc_otg_set_param_enable_dynamic_fifo(core_if,
610 module_params.enable_dynamic_fifo);
612 if (module_params.data_fifo_size != -1) {
614 dwc_otg_set_param_data_fifo_size(core_if,
615 module_params.data_fifo_size);
617 if (module_params.dev_rx_fifo_size != -1) {
619 dwc_otg_set_param_dev_rx_fifo_size(core_if,
620 module_params.dev_rx_fifo_size);
622 if (module_params.dev_nperio_tx_fifo_size != -1) {
624 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
625 module_params.dev_nperio_tx_fifo_size);
627 if (module_params.host_rx_fifo_size != -1) {
629 dwc_otg_set_param_host_rx_fifo_size(core_if,
633 if (module_params.host_nperio_tx_fifo_size != -1) {
635 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
636 module_params.host_nperio_tx_fifo_size);
638 if (module_params.host_perio_tx_fifo_size != -1) {
640 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
641 module_params.host_perio_tx_fifo_size);
643 if (module_params.max_transfer_size != -1) {
645 dwc_otg_set_param_max_transfer_size(core_if,
646 module_params.max_transfer_size);
648 if (module_params.max_packet_count != -1) {
650 dwc_otg_set_param_max_packet_count(core_if,
651 module_params.max_packet_count);
653 if (module_params.host_channels != -1) {
655 dwc_otg_set_param_host_channels(core_if,
656 module_params.host_channels);
658 if (module_params.dev_endpoints != -1) {
660 dwc_otg_set_param_dev_endpoints(core_if,
661 module_params.dev_endpoints);
663 if (module_params.phy_type != -1) {
665 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
667 if (module_params.speed != -1) {
668 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
670 if (module_params.host_ls_low_power_phy_clk != -1) {
672 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
673 module_params.host_ls_low_power_phy_clk);
675 if (module_params.phy_ulpi_ddr != -1) {
677 dwc_otg_set_param_phy_ulpi_ddr(core_if,
678 module_params.phy_ulpi_ddr);
680 if (module_params.phy_ulpi_ext_vbus != -1) {
682 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
683 module_params.phy_ulpi_ext_vbus);
685 if (module_params.phy_utmi_width != -1) {
687 dwc_otg_set_param_phy_utmi_width(core_if,
688 module_params.phy_utmi_width);
690 if (module_params.ulpi_fs_ls != -1) {
692 dwc_otg_set_param_ulpi_fs_ls(core_if,
693 module_params.ulpi_fs_ls);
695 if (module_params.ts_dline != -1) {
697 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
699 if (module_params.i2c_enable != -1) {
701 dwc_otg_set_param_i2c_enable(core_if,
702 module_params.i2c_enable);
704 if (module_params.en_multiple_tx_fifo != -1) {
706 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
707 module_params.en_multiple_tx_fifo);
709 for (i = 0; i < 15; i++) {
710 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
712 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
713 module_params.dev_perio_tx_fifo_size
718 for (i = 0; i < 15; i++) {
719 if (module_params.dev_tx_fifo_size[i] != -1) {
720 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
721 module_params.dev_tx_fifo_size
725 if (module_params.thr_ctl != -1) {
727 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
729 if (module_params.mpi_enable != -1) {
731 dwc_otg_set_param_mpi_enable(core_if,
732 module_params.mpi_enable);
734 if (module_params.pti_enable != -1) {
736 dwc_otg_set_param_pti_enable(core_if,
737 module_params.pti_enable);
739 if (module_params.lpm_enable != -1) {
741 dwc_otg_set_param_lpm_enable(core_if,
742 module_params.lpm_enable);
744 if (module_params.besl_enable != -1) {
746 dwc_otg_set_param_besl_enable(core_if,
747 module_params.besl_enable);
749 if (module_params.baseline_besl != -1) {
751 dwc_otg_set_param_baseline_besl(core_if,
752 module_params.baseline_besl);
754 if (module_params.deep_besl != -1) {
756 dwc_otg_set_param_deep_besl(core_if,
757 module_params.deep_besl);
759 if (module_params.ic_usb_cap != -1) {
761 dwc_otg_set_param_ic_usb_cap(core_if,
762 module_params.ic_usb_cap);
764 if (module_params.tx_thr_length != -1) {
766 dwc_otg_set_param_tx_thr_length(core_if,
770 if (module_params.rx_thr_length != -1) {
772 dwc_otg_set_param_rx_thr_length(core_if,
773 module_params.rx_thr_length);
775 if (module_params.ahb_thr_ratio != -1) {
777 dwc_otg_set_param_ahb_thr_ratio(core_if,
781 if (module_params.power_down != -1) {
783 dwc_otg_set_param_power_down(core_if,
784 module_params.power_down);
786 if (module_params.reload_ctl != -1) {
788 dwc_otg_set_param_reload_ctl(core_if,
789 module_params.reload_ctl);
792 if (module_params.dev_out_nak != -1) {
794 dwc_otg_set_param_dev_out_nak(core_if,
795 module_params.dev_out_nak);
798 if (module_params.cont_on_bna != -1) {
800 dwc_otg_set_param_cont_on_bna(core_if,
801 module_params.cont_on_bna);
804 if (module_params.ahb_single != -1) {
806 dwc_otg_set_param_ahb_single(core_if,
807 module_params.ahb_single);
810 if (module_params.otg_ver != -1) {
812 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
814 if (module_params.adp_enable != -1) {
816 dwc_otg_set_param_adp_enable(core_if,
817 module_params.adp_enable);
823 * This function is the top level interrupt handler for the Common
824 * (Device and host modes) interrupts.
826 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
828 int32_t retval = IRQ_NONE;
830 retval = dwc_otg_handle_common_intr(dev);
832 /* S3C2410X_CLEAR_EINTPEND(); */
834 return IRQ_RETVAL(retval);
837 #ifdef CONFIG_USB20_HOST
839 * This function is called when a lm_device is unregistered with the
840 * dwc_otg_driver. This happens, for example, when the rmmod command is
841 * executed. The device may or may not be electrically present. If it is
842 * present, the driver stops device processing. Any resources used on behalf
843 * of this device are freed.
847 static int host20_driver_remove(struct platform_device *_dev)
850 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
851 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
854 /* Memory allocation for the dwc_otg_device failed. */
855 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
858 #ifndef DWC_DEVICE_ONLY
862 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
867 #ifndef DWC_HOST_ONLY
871 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
879 if (otg_dev->common_irq_installed) {
880 /* free_irq(_dev->irq, otg_dev); */
881 free_irq(platform_get_irq(_dev, 0), otg_dev);
883 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
888 if (otg_dev->core_if) {
889 dwc_otg_cil_remove(otg_dev->core_if);
891 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
896 * Remove the device attributes
898 dwc_otg_attr_remove(_dev);
903 if (otg_dev->os_dep.base) {
904 iounmap(otg_dev->os_dep.base);
909 * Clear the drvdata pointer.
912 dwc_set_device_platform_data(_dev, 0);
917 static const struct of_device_id usb20_host_of_match[] = {
919 .compatible = "rockchip,rk3188_usb20_host",
920 .data = &usb20host_pdata_rk3188,
923 .compatible = "rockchip,rk3288_usb20_host",
924 .data = &usb20host_pdata_rk3288,
927 .compatible = "rockchip,rk3036_usb20_host",
928 .data = &usb20host_pdata_rk3036,
931 .compatible = "rockchip,rk3126_usb20_host",
932 .data = &usb20host_pdata_rk3126,
937 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
940 * This function is called when an lm_device is bound to a
941 * dwc_otg_driver. It creates the driver components required to
942 * control the device (CIL, HCD, and PCD) and it initializes the
943 * device. The driver components are stored in a dwc_otg_device
944 * structure. A reference to the dwc_otg_device is saved in the
945 * lm_device. This allows the driver to access the dwc_otg_device
946 * structure on subsequent calls to driver methods for this device.
948 * @param _dev Bus device
950 static int host20_driver_probe(struct platform_device *_dev)
954 struct resource *res_base;
955 dwc_otg_device_t *dwc_otg_device;
956 struct device *dev = &_dev->dev;
957 struct device_node *node = _dev->dev.of_node;
958 struct dwc_otg_platform_data *pldata;
959 const struct of_device_id *match =
960 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
962 if (match && match->data) {
963 pldata = (void *)match->data;
966 dev_err(dev, "usb20otg match failed\n");
971 dev_err(dev, "device node not found\n");
978 if (pldata->clock_init) {
979 pldata->clock_init(pldata);
980 pldata->clock_enable(pldata, 1);
983 if (pldata->phy_suspend)
984 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
986 if (pldata->soft_reset)
987 pldata->soft_reset(pldata, RST_POR);
989 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
991 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
993 if (!dwc_otg_device) {
994 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
999 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1000 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1003 * Map the DWC_otg Core memory into virtual address space.
1006 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1008 if (!dwc_otg_device->os_dep.base) {
1009 dev_err(&_dev->dev, "ioremap() failed\n");
1010 DWC_FREE(dwc_otg_device);
1014 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1016 /* Set device flags indicating whether the HCD supports DMA. */
1017 if (!_dev->dev.dma_mask)
1018 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1019 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1024 * Initialize driver data to point to the global DWC_otg
1028 dwc_set_device_platform_data(_dev, dwc_otg_device);
1029 pldata->privdata = dwc_otg_device;
1030 dwc_otg_device->pldata = (void *)pldata;
1032 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1034 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1036 if (!dwc_otg_device->core_if) {
1037 dev_err(&_dev->dev, "CIL initialization failed!\n");
1042 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1045 * Attempt to ensure this device is really a DWC_otg Controller.
1046 * Read and verify the SNPSID register contents. The value should be
1047 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1048 * as in "OTG version 2.XX" or "OTG version 3.XX".
1051 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1053 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1056 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1062 * Validate parameter values.
1064 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1070 * Create Device Attributes in sysfs
1072 dwc_otg_attr_create(_dev);
1075 * Disable the global interrupt until all the interrupt
1076 * handlers are installed.
1078 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1081 * Install the interrupt handler for the common interrupts before
1082 * enabling common interrupts in core_init below.
1084 irq = platform_get_irq(_dev, 0);
1085 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1086 retval = request_irq(irq, dwc_otg_common_irq,
1087 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1089 DWC_ERROR("request of irq%d failed\n", irq);
1093 dwc_otg_device->common_irq_installed = 1;
1097 * Initialize the DWC_otg core.
1098 * In order to reduce the time of initialization,
1099 * we do core soft reset after connection detected.
1101 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1104 * Initialize the HCD
1106 retval = host20_hcd_init(_dev);
1108 DWC_ERROR("hcd_init failed\n");
1109 dwc_otg_device->hcd = NULL;
1113 clk_set_rate(pldata->phyclk_480m, 480000000);
1115 * Enable the global interrupt after all the interrupt
1116 * handlers are installed if there is no ADP support else
1117 * perform initial actions required for Internal ADP logic.
1119 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1120 if (pldata->phy_status == USB_PHY_ENABLED) {
1121 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1123 pldata->clock_enable(pldata, 0);
1125 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1127 dwc_otg_adp_start(dwc_otg_device->core_if,
1128 dwc_otg_is_host_mode(dwc_otg_device->
1134 host20_driver_remove(_dev);
1136 if (pldata->clock_enable)
1137 pldata->clock_enable(pldata, 0);
1143 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1149 static int dwc_otg_driver_resume(struct platform_device *_dev)
1154 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1156 struct device *dev = &_dev->dev;
1157 dwc_otg_device_t *otg_dev = dev->platform_data;
1158 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1159 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1160 dctl_data_t dctl = {.d32 = 0 };
1162 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1163 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1165 if (pldata->dwc_otg_uart_mode != NULL)
1166 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1167 if (pldata->phy_suspend != NULL)
1168 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1169 if (dwc_otg_is_host_mode(core_if)) {
1170 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1171 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1173 /* soft disconnect */
1175 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1176 dctl.b.sftdiscon = 1;
1177 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1180 /* Clear any pending interrupts */
1181 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1186 * This structure defines the methods to be called by a bus driver
1187 * during the lifecycle of a device on that bus. Both drivers and
1188 * devices are registered with a bus driver. The bus driver matches
1189 * devices to drivers based on information in the device and driver
1192 * The probe function is called when the bus driver matches a device
1193 * to this driver. The remove function is called when a device is
1194 * unregistered with the bus driver.
1196 #ifdef CONFIG_USB20_HOST
1197 static struct platform_driver dwc_host_driver = {
1199 .name = (char *)dwc_host20_driver_name,
1200 .of_match_table = of_match_ptr(usb20_host_of_match),
1202 .probe = host20_driver_probe,
1203 .remove = host20_driver_remove,
1204 .suspend = dwc_otg_driver_suspend,
1205 .resume = dwc_otg_driver_resume,
1209 #ifdef CONFIG_USB20_OTG
1211 * This function is called when a lm_device is unregistered with the
1212 * dwc_otg_driver. This happens, for example, when the rmmod command is
1213 * executed. The device may or may not be electrically present. If it is
1214 * present, the driver stops device processing. Any resources used on behalf
1215 * of this device are freed.
1219 static int otg20_driver_remove(struct platform_device *_dev)
1222 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1223 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1226 /* Memory allocation for the dwc_otg_device failed. */
1227 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1230 #ifndef DWC_DEVICE_ONLY
1234 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1239 #ifndef DWC_HOST_ONLY
1243 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1250 if (otg_dev->common_irq_installed) {
1251 /* free_irq(_dev->irq, otg_dev); */
1252 free_irq(platform_get_irq(_dev, 0), otg_dev);
1254 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1259 if (otg_dev->core_if) {
1260 dwc_otg_cil_remove(otg_dev->core_if);
1262 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1267 * Remove the device attributes
1269 dwc_otg_attr_remove(_dev);
1272 * Return the memory.
1274 if (otg_dev->os_dep.base)
1275 iounmap(otg_dev->os_dep.base);
1279 * Clear the drvdata pointer.
1282 dwc_set_device_platform_data(_dev, 0);
1287 static const struct of_device_id usb20_otg_of_match[] = {
1289 .compatible = "rockchip,rk3188_usb20_otg",
1290 .data = &usb20otg_pdata_rk3188,
1293 .compatible = "rockchip,rk3288_usb20_otg",
1294 .data = &usb20otg_pdata_rk3288,
1297 .compatible = "rockchip,rk3036_usb20_otg",
1298 .data = &usb20otg_pdata_rk3036,
1301 .compatible = "rockchip,rk3126_usb20_otg",
1302 .data = &usb20otg_pdata_rk3126,
1305 .compatible = "rockchip,rk3368_usb20_otg",
1306 .data = &usb20otg_pdata_rk3368,
1311 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1314 * This function is called when an lm_device is bound to a
1315 * dwc_otg_driver. It creates the driver components required to
1316 * control the device (CIL, HCD, and PCD) and it initializes the
1317 * device. The driver components are stored in a dwc_otg_device
1318 * structure. A reference to the dwc_otg_device is saved in the
1319 * lm_device. This allows the driver to access the dwc_otg_device
1320 * structure on subsequent calls to driver methods for this device.
1322 * @param _dev Bus device
1324 static int otg20_driver_probe(struct platform_device *_dev)
1329 struct resource *res_base;
1330 dwc_otg_device_t *dwc_otg_device;
1331 struct device *dev = &_dev->dev;
1332 struct device_node *node = _dev->dev.of_node;
1333 struct dwc_otg_platform_data *pldata;
1334 const struct of_device_id *match =
1335 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1337 if (match && match->data) {
1338 pldata = (void *)match->data;
1341 dev_err(dev, "usb20otg match failed\n");
1346 dev_err(dev, "device node not found\n");
1350 if (pldata->hw_init)
1353 if (pldata->clock_init) {
1354 pldata->clock_init(pldata);
1355 pldata->clock_enable(pldata, 1);
1358 if (pldata->phy_suspend)
1359 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1361 if (pldata->dwc_otg_uart_mode)
1362 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1364 /* do reset later, because reset need about
1365 * 100ms to ensure otg id state change.
1368 if(pldata->soft_reset)
1369 pldata->soft_reset();
1373 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1375 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1377 if (!dwc_otg_device) {
1378 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1383 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1384 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1387 * Map the DWC_otg Core memory into virtual address space.
1390 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1392 if (!dwc_otg_device->os_dep.base) {
1393 dev_err(&_dev->dev, "ioremap() failed\n");
1394 DWC_FREE(dwc_otg_device);
1398 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1400 /* Set device flags indicating whether the HCD supports DMA. */
1401 if (!_dev->dev.dma_mask)
1402 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1403 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1408 * Initialize driver data to point to the global DWC_otg
1412 g_otgdev = dwc_otg_device;
1413 pldata->privdata = dwc_otg_device;
1414 dwc_otg_device->pldata = pldata;
1416 dwc_set_device_platform_data(_dev, dwc_otg_device);
1418 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1420 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1421 if (!dwc_otg_device->core_if) {
1422 dev_err(&_dev->dev, "CIL initialization failed!\n");
1427 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1429 * Attempt to ensure this device is really a DWC_otg Controller.
1430 * Read and verify the SNPSID register contents. The value should be
1431 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1432 * as in "OTG version 2.XX" or "OTG version 3.XX".
1435 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1437 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1439 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1440 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1446 * Validate parameter values.
1448 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1454 * Create Device Attributes in sysfs
1456 dwc_otg_attr_create(_dev);
1459 * Disable the global interrupt until all the interrupt
1460 * handlers are installed.
1462 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1465 * Install the interrupt handler for the common interrupts before
1466 * enabling common interrupts in core_init below.
1468 irq = platform_get_irq(_dev, 0);
1469 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1470 retval = request_irq(irq, dwc_otg_common_irq,
1471 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1473 DWC_ERROR("request of irq%d failed\n", irq);
1477 dwc_otg_device->common_irq_installed = 1;
1481 * Initialize the DWC_otg core.
1482 * In order to reduce the time of initialization,
1483 * we do core soft reset after connection detected.
1485 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1488 * 0 - USB_MODE_NORMAL
1489 * 1 - USB_MODE_FORCE_HOST
1490 * 2 - USB_MODE_FORCE_DEVICE
1492 of_property_read_u32(node, "rockchip,usb-mode", &val);
1493 dwc_otg_device->core_if->usb_mode = val;
1495 #ifndef DWC_HOST_ONLY
1497 * Initialize the PCD
1499 retval = pcd_init(_dev);
1501 DWC_ERROR("pcd_init failed\n");
1502 dwc_otg_device->pcd = NULL;
1506 #ifndef DWC_DEVICE_ONLY
1508 * Initialize the HCD
1510 retval = otg20_hcd_init(_dev);
1512 DWC_ERROR("hcd_init failed\n");
1513 dwc_otg_device->hcd = NULL;
1518 * Enable the global interrupt after all the interrupt
1519 * handlers are installed if there is no ADP support else
1520 * perform initial actions required for Internal ADP logic.
1522 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1523 if (pldata->phy_status == USB_PHY_ENABLED) {
1524 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1526 pldata->clock_enable(pldata, 0);
1528 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1530 dwc_otg_adp_start(dwc_otg_device->core_if,
1531 dwc_otg_is_host_mode(dwc_otg_device->
1537 otg20_driver_remove(_dev);
1540 if (pldata->clock_enable)
1541 pldata->clock_enable(pldata, 0);
1547 static int dwc_otg_pm_suspend(struct device *dev)
1549 dwc_otg_device_t *dwc_otg_device;
1550 struct dwc_otg_platform_data *pdata_otg;
1552 dwc_otg_device = dev_get_platdata(dev);
1554 dev_dbg(dev, "dwc_otg PM suspend\n");
1556 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1559 pdata_otg = dwc_otg_device->pldata;
1560 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1565 static int dwc_otg_pm_resume(struct device *dev)
1567 dwc_otg_device_t *dwc_otg_device;
1568 struct dwc_otg_platform_data *pdata_otg;
1570 dwc_otg_device = dev_get_platdata(dev);
1572 dev_dbg(dev, "dwc_otg PM resume\n");
1574 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1577 pdata_otg = dwc_otg_device->pldata;
1578 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1583 #define dwc_otg_pm_suspend NULL
1584 #define dwc_otg_pm_resume NULL
1587 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1588 .suspend = dwc_otg_pm_suspend,
1589 .resume = dwc_otg_pm_resume,
1592 static struct platform_driver dwc_otg_driver = {
1594 .name = (char *)dwc_otg20_driver_name,
1595 .of_match_table = of_match_ptr(usb20_otg_of_match),
1597 .pm = &dwc_otg_dev_pm_ops,
1600 .probe = otg20_driver_probe,
1601 .remove = otg20_driver_remove,
1602 .suspend = dwc_otg_driver_suspend,
1603 .resume = dwc_otg_driver_resume,
1604 .shutdown = dwc_otg_driver_shutdown,
1608 void rk_usb_power_up(void)
1610 struct dwc_otg_platform_data *pldata_otg;
1611 struct dwc_otg_platform_data *pldata_host;
1612 struct rkehci_platform_data *pldata_ehci;
1614 if (cpu_is_rk3288()) {
1615 #ifdef CONFIG_RK_USB_UART
1616 /* enable USB bypass UART function */
1617 writel_relaxed(0x00c00000 | usb_to_uart_status,
1618 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1621 /* unset siddq,the analog blocks are powered up */
1622 #ifdef CONFIG_USB20_OTG
1623 pldata_otg = &usb20otg_pdata_rk3288;
1625 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1626 writel_relaxed((0x01 << 13) << 16,
1628 RK3288_GRF_UOC0_CON0);
1631 #ifdef CONFIG_USB20_HOST
1632 pldata_host = &usb20host_pdata_rk3288;
1634 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1635 writel_relaxed((0x01 << 13) << 16,
1637 RK3288_GRF_UOC2_CON0);
1640 #ifdef CONFIG_USB_EHCI_RK
1641 pldata_ehci = &rkehci_pdata_rk3288;
1643 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1644 writel_relaxed((0x01 << 13) << 16,
1646 RK3288_GRF_UOC1_CON0);
1651 dwc_otg_device_t *otg_dev = g_otgdev;
1656 pldata_otg = otg_dev->pldata;
1657 if (pldata_otg && pldata_otg->phy_power_down)
1658 pldata_otg->phy_power_down(PHY_POWER_UP);
1662 void rk_usb_power_down(void)
1664 struct dwc_otg_platform_data *pldata_otg;
1665 struct dwc_otg_platform_data *pldata_host;
1666 struct rkehci_platform_data *pldata_ehci;
1668 if (cpu_is_rk3288()) {
1669 #ifdef CONFIG_RK_USB_UART
1670 /* disable USB bypass UART function */
1671 usb_to_uart_status =
1672 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1673 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1675 /* set siddq,the analog blocks are powered down
1677 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1678 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1679 * and TESTBURNIN are set to 1'b0.
1680 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1681 #ifdef CONFIG_USB20_OTG
1682 pldata_otg = &usb20otg_pdata_rk3288;
1684 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1685 writel_relaxed((0x01 << 13) |
1686 ((0x01 << 13) << 16),
1688 RK3288_GRF_UOC0_CON0);
1691 #ifdef CONFIG_USB20_HOST
1692 pldata_host = &usb20host_pdata_rk3288;
1694 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1695 writel_relaxed((0x01 << 13) |
1696 ((0x01 << 13) << 16),
1698 RK3288_GRF_UOC2_CON0);
1701 #ifdef CONFIG_USB_EHCI_RK
1702 pldata_ehci = &rkehci_pdata_rk3288;
1704 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1705 writel_relaxed((0x01 << 13) |
1706 ((0x01 << 13) << 16),
1708 RK3288_GRF_UOC1_CON0);
1712 dwc_otg_device_t *otg_dev = g_otgdev;
1717 pldata_otg = otg_dev->pldata;
1718 if (pldata_otg && pldata_otg->phy_power_down)
1719 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1723 EXPORT_SYMBOL(rk_usb_power_up);
1724 EXPORT_SYMBOL(rk_usb_power_down);
1726 * This function is called when the dwc_otg_driver is installed with the
1727 * insmod command. It registers the dwc_otg_driver structure with the
1728 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1729 * to be called. In addition, the bus driver will automatically expose
1730 * attributes defined for the device and driver in the special sysfs file
1735 static int __init dwc_otg_driver_init(void)
1740 #ifdef CONFIG_USB20_OTG
1741 /* register otg20 */
1742 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1743 DWC_DRIVER_VERSION);
1745 retval = platform_driver_register(&dwc_otg_driver);
1747 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1752 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1754 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1756 driver_create_file(&dwc_otg_driver.driver,
1757 &driver_attr_dwc_otg_conn_en);
1759 driver_create_file(&dwc_otg_driver.driver,
1760 &driver_attr_vbus_status);
1762 driver_create_file(&dwc_otg_driver.driver,
1763 &driver_attr_force_usb_mode);
1765 driver_create_file(&dwc_otg_driver.driver,
1766 &driver_attr_op_state);
1770 /* register host20 */
1771 #ifdef CONFIG_USB20_HOST
1772 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1773 DWC_DRIVER_VERSION);
1775 retval = platform_driver_register(&dwc_host_driver);
1777 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1782 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1784 driver_create_file(&dwc_host_driver.driver,
1785 &driver_attr_debuglevel);
1790 module_init(dwc_otg_driver_init);
1793 * This function is called when the driver is removed from the kernel
1794 * with the rmmod command. The driver unregisters itself with its bus
1798 static void __exit dwc_otg_driver_cleanup(void)
1800 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1802 #ifdef CONFIG_USB20_HOST
1804 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1805 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1806 platform_driver_unregister(&dwc_host_driver);
1807 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1810 #ifdef CONFIG_USB20_OTG
1812 driver_remove_file(&dwc_otg_driver.driver,
1813 &driver_attr_dwc_otg_conn_en);
1814 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1815 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1816 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1817 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1818 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1819 platform_driver_unregister(&dwc_otg_driver);
1820 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1824 module_exit(dwc_otg_driver_cleanup);
1826 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1827 MODULE_AUTHOR("Synopsys Inc.");
1828 MODULE_LICENSE("GPL");
1830 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1831 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1832 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1833 MODULE_PARM_DESC(opt, "OPT Mode");
1834 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1835 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1837 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1839 MODULE_PARM_DESC(dma_desc_enable,
1840 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1842 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1844 MODULE_PARM_DESC(dma_burst_size,
1845 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1846 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1847 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1848 module_param_named(host_support_fs_ls_low_power,
1849 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1851 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1852 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1853 module_param_named(host_ls_low_power_phy_clk,
1854 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1855 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1856 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1857 module_param_named(enable_dynamic_fifo,
1858 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1859 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1860 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1862 MODULE_PARM_DESC(data_fifo_size,
1863 "Total number of words in the data FIFO memory 32-32768");
1864 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1866 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1867 module_param_named(dev_nperio_tx_fifo_size,
1868 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1869 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1870 "Number of words in the non-periodic Tx FIFO 16-32768");
1871 module_param_named(dev_perio_tx_fifo_size_1,
1872 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1873 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1874 "Number of words in the periodic Tx FIFO 4-768");
1875 module_param_named(dev_perio_tx_fifo_size_2,
1876 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1877 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1878 "Number of words in the periodic Tx FIFO 4-768");
1879 module_param_named(dev_perio_tx_fifo_size_3,
1880 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1881 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1882 "Number of words in the periodic Tx FIFO 4-768");
1883 module_param_named(dev_perio_tx_fifo_size_4,
1884 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1885 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1886 "Number of words in the periodic Tx FIFO 4-768");
1887 module_param_named(dev_perio_tx_fifo_size_5,
1888 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1889 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1890 "Number of words in the periodic Tx FIFO 4-768");
1891 module_param_named(dev_perio_tx_fifo_size_6,
1892 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1893 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1894 "Number of words in the periodic Tx FIFO 4-768");
1895 module_param_named(dev_perio_tx_fifo_size_7,
1896 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1897 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1898 "Number of words in the periodic Tx FIFO 4-768");
1899 module_param_named(dev_perio_tx_fifo_size_8,
1900 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1901 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1902 "Number of words in the periodic Tx FIFO 4-768");
1903 module_param_named(dev_perio_tx_fifo_size_9,
1904 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1905 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1906 "Number of words in the periodic Tx FIFO 4-768");
1907 module_param_named(dev_perio_tx_fifo_size_10,
1908 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1909 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1910 "Number of words in the periodic Tx FIFO 4-768");
1911 module_param_named(dev_perio_tx_fifo_size_11,
1912 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1913 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1914 "Number of words in the periodic Tx FIFO 4-768");
1915 module_param_named(dev_perio_tx_fifo_size_12,
1916 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1917 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1918 "Number of words in the periodic Tx FIFO 4-768");
1919 module_param_named(dev_perio_tx_fifo_size_13,
1920 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1921 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1922 "Number of words in the periodic Tx FIFO 4-768");
1923 module_param_named(dev_perio_tx_fifo_size_14,
1924 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1925 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1926 "Number of words in the periodic Tx FIFO 4-768");
1927 module_param_named(dev_perio_tx_fifo_size_15,
1928 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1929 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1930 "Number of words in the periodic Tx FIFO 4-768");
1931 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1933 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1934 module_param_named(host_nperio_tx_fifo_size,
1935 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1936 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1937 "Number of words in the non-periodic Tx FIFO 16-32768");
1938 module_param_named(host_perio_tx_fifo_size,
1939 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1940 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1941 "Number of words in the host periodic Tx FIFO 16-32768");
1942 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1944 /** @todo Set the max to 512K, modify checks */
1945 MODULE_PARM_DESC(max_transfer_size,
1946 "The maximum transfer size supported in bytes 2047-65535");
1947 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1949 MODULE_PARM_DESC(max_packet_count,
1950 "The maximum number of packets in a transfer 15-511");
1951 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1953 MODULE_PARM_DESC(host_channels,
1954 "The number of host channel registers to use 1-16");
1955 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1957 MODULE_PARM_DESC(dev_endpoints,
1958 "The number of endpoints in addition to EP0 available for device mode 1-15");
1959 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1960 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1961 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1963 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1964 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1965 MODULE_PARM_DESC(phy_ulpi_ddr,
1966 "ULPI at double or single data rate 0=Single 1=Double");
1967 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1969 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1970 "ULPI PHY using internal or external vbus 0=Internal");
1971 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1972 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1973 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1974 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1975 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1976 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1977 module_param_named(debug, g_dbg_lvl, int, 0444);
1978 MODULE_PARM_DESC(debug, "");
1980 module_param_named(en_multiple_tx_fifo,
1981 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1982 MODULE_PARM_DESC(en_multiple_tx_fifo,
1983 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1984 module_param_named(dev_tx_fifo_size_1,
1985 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1986 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1987 module_param_named(dev_tx_fifo_size_2,
1988 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1989 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1990 module_param_named(dev_tx_fifo_size_3,
1991 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1992 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1993 module_param_named(dev_tx_fifo_size_4,
1994 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1995 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1996 module_param_named(dev_tx_fifo_size_5,
1997 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1998 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1999 module_param_named(dev_tx_fifo_size_6,
2000 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2001 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2002 module_param_named(dev_tx_fifo_size_7,
2003 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2004 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2005 module_param_named(dev_tx_fifo_size_8,
2006 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2007 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2008 module_param_named(dev_tx_fifo_size_9,
2009 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2010 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2011 module_param_named(dev_tx_fifo_size_10,
2012 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2013 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2014 module_param_named(dev_tx_fifo_size_11,
2015 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2016 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2017 module_param_named(dev_tx_fifo_size_12,
2018 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2019 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2020 module_param_named(dev_tx_fifo_size_13,
2021 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2022 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2023 module_param_named(dev_tx_fifo_size_14,
2024 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2025 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2026 module_param_named(dev_tx_fifo_size_15,
2027 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2028 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2030 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2031 MODULE_PARM_DESC(thr_ctl,
2032 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2033 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2035 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2036 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2038 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2040 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2041 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2042 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2043 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2045 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2046 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2047 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2049 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2050 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2051 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2053 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2054 MODULE_PARM_DESC(ic_usb_cap,
2055 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2056 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2058 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2059 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2060 MODULE_PARM_DESC(power_down, "Power Down Mode");
2061 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2062 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2063 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2064 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2065 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2066 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2067 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2068 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2069 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2070 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2071 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2072 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2074 /** @page "Module Parameters"
2076 * The following parameters may be specified when starting the module.
2077 * These parameters define how the DWC_otg controller should be
2078 * configured. Parameter values are passed to the CIL initialization
2079 * function dwc_otg_cil_init
2081 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2085 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2089 <td>Specifies the OTG capabilities. The driver will automatically detect the
2090 value for this parameter if none is specified.
2091 - 0: HNP and SRP capable (default, if available)
2092 - 1: SRP Only capable
2093 - 2: No HNP/SRP capable
2098 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2099 The driver will automatically detect the value for this parameter if none is
2102 - 1: DMA (default, if available)
2106 <td>dma_burst_size</td>
2107 <td>The DMA Burst size (applicable only for External DMA Mode).
2108 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2113 <td>Specifies the maximum speed of operation in host and device mode. The
2114 actual speed depends on the speed of the attached device and the value of
2116 - 0: High Speed (default)
2121 <td>host_support_fs_ls_low_power</td>
2122 <td>Specifies whether low power mode is supported when attached to a Full
2123 Speed or Low Speed device in host mode.
2124 - 0: Don't support low power mode (default)
2125 - 1: Support low power mode
2129 <td>host_ls_low_power_phy_clk</td>
2130 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2131 Speed device in host mode. This parameter is applicable only if
2132 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2133 - 0: 48 MHz (default)
2138 <td>enable_dynamic_fifo</td>
2139 <td> Specifies whether FIFOs may be resized by the driver software.
2140 - 0: Use cC FIFO size parameters
2141 - 1: Allow dynamic FIFO sizing (default)
2145 <td>data_fifo_size</td>
2146 <td>Total number of 4-byte words in the data FIFO memory. This memory
2147 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2148 - Values: 32 to 32768 (default 8192)
2150 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2154 <td>dev_rx_fifo_size</td>
2155 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2156 FIFO sizing is enabled.
2157 - Values: 16 to 32768 (default 1064)
2161 <td>dev_nperio_tx_fifo_size</td>
2162 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2163 dynamic FIFO sizing is enabled.
2164 - Values: 16 to 32768 (default 1024)
2168 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2169 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2170 when dynamic FIFO sizing is enabled.
2171 - Values: 4 to 768 (default 256)
2175 <td>host_rx_fifo_size</td>
2176 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2178 - Values: 16 to 32768 (default 1024)
2182 <td>host_nperio_tx_fifo_size</td>
2183 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2184 dynamic FIFO sizing is enabled in the core.
2185 - Values: 16 to 32768 (default 1024)
2189 <td>host_perio_tx_fifo_size</td>
2190 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2192 - Values: 16 to 32768 (default 1024)
2196 <td>max_transfer_size</td>
2197 <td>The maximum transfer size supported in bytes.
2198 - Values: 2047 to 65,535 (default 65,535)
2202 <td>max_packet_count</td>
2203 <td>The maximum number of packets in a transfer.
2204 - Values: 15 to 511 (default 511)
2208 <td>host_channels</td>
2209 <td>The number of host channel registers to use.
2210 - Values: 1 to 16 (default 12)
2212 Note: The FPGA configuration supports a maximum of 12 host channels.
2216 <td>dev_endpoints</td>
2217 <td>The number of endpoints in addition to EP0 available for device mode
2219 - Values: 1 to 15 (default 6 IN and OUT)
2221 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2227 <td>Specifies the type of PHY interface to use. By default, the driver will
2228 automatically detect the phy_type.
2230 - 1: UTMI+ (default, if available)
2235 <td>phy_utmi_width</td>
2236 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2237 phy_type of UTMI+. Also, this parameter is applicable only if the
2238 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2239 core has been configured to work at either data path width.
2240 - Values: 8 or 16 bits (default 16)
2244 <td>phy_ulpi_ddr</td>
2245 <td>Specifies whether the ULPI operates at double or single data rate. This
2246 parameter is only applicable if phy_type is ULPI.
2247 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2248 - 1: double data rate ULPI interface with 4 bit wide data bus
2253 <td>Specifies whether to use the I2C interface for full speed PHY. This
2254 parameter is only applicable if PHY_TYPE is FS.
2255 - 0: Disabled (default)
2261 <td>Specifies whether to use ULPI FS/LS mode only.
2262 - 0: Disabled (default)
2268 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2269 - 0: Disabled (default)
2274 <td>en_multiple_tx_fifo</td>
2275 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2276 The driver will automatically detect the value for this parameter if none is
2279 - 1: Enabled (default, if available)
2283 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2284 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2285 when dynamic FIFO sizing is enabled.
2286 - Values: 4 to 768 (default 256)
2290 <td>tx_thr_length</td>
2291 <td>Transmit Threshold length in 32 bit double words
2292 - Values: 8 to 128 (default 64)
2296 <td>rx_thr_length</td>
2297 <td>Receive Threshold length in 32 bit double words
2298 - Values: 8 to 128 (default 64)
2303 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2304 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2305 Rx transfers accordingly.
2306 The driver will automatically detect the value for this parameter if none is
2308 - Values: 0 to 7 (default 0)
2309 Bit values indicate:
2310 - 0: Thresholding disabled
2311 - 1: Thresholding enabled
2315 <td>dma_desc_enable</td>
2316 <td>Specifies whether to enable Descriptor DMA mode.
2317 The driver will automatically detect the value for this parameter if none is
2319 - 0: Descriptor DMA disabled
2320 - 1: Descriptor DMA (default, if available)
2325 <td>Specifies whether to enable MPI enhancement mode.
2326 The driver will automatically detect the value for this parameter if none is
2328 - 0: MPI disabled (default)
2334 <td>Specifies whether to enable PTI enhancement support.
2335 The driver will automatically detect the value for this parameter if none is
2337 - 0: PTI disabled (default)
2343 <td>Specifies whether to enable LPM support.
2344 The driver will automatically detect the value for this parameter if none is
2347 - 1: LPM enable (default, if available)
2351 <td>besl_enable</td>
2352 <td>Specifies whether to enable LPM Errata support.
2353 The driver will automatically detect the value for this parameter if none is
2355 - 0: LPM Errata disabled (default)
2356 - 1: LPM Errata enable
2360 <td>baseline_besl</td>
2361 <td>Specifies the baseline besl value.
2362 - Values: 0 to 15 (default 0)
2367 <td>Specifies the deep besl value.
2368 - Values: 0 to 15 (default 15)
2373 <td>Specifies whether to enable IC_USB capability.
2374 The driver will automatically detect the value for this parameter if none is
2376 - 0: IC_USB disabled (default, if available)
2381 <td>ahb_thr_ratio</td>
2382 <td>Specifies AHB Threshold ratio.
2383 - Values: 0 to 3 (default 0)
2388 <td>Specifies Power Down(Hibernation) Mode.
2389 The driver will automatically detect the value for this parameter if none is
2391 - 0: Power Down disabled (default)
2392 - 2: Power Down enabled
2397 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2398 run time. The driver will automatically detect the value for this parameter if
2399 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2400 the core might misbehave.
2401 - 0: Reload Control disabled (default)
2402 - 1: Reload Control enabled
2406 <td>dev_out_nak</td>
2407 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2408 The driver will automatically detect the value for this parameter if
2409 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2410 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2411 - 1: The core sets NAK after Bulk OUT transfer complete
2415 <td>cont_on_bna</td>
2416 <td>Specifies whether Enable Continue on BNA enabled or no.
2417 After receiving BNA interrupt the core disables the endpoint,when the
2418 endpoint is re-enabled by the application the
2419 - 0: Core starts processing from the DOEPDMA descriptor (default)
2420 - 1: Core starts processing from the descriptor which received the BNA.
2421 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2426 <td>This bit when programmed supports SINGLE transfers for remainder data
2427 in a transfer for DMA mode of operation.
2428 - 0: The remainder data will be sent using INCR burst size (default)
2429 - 1: The remainder data will be sent using SINGLE burst size.
2434 <td>Specifies whether ADP feature is enabled.
2435 The driver will automatically detect the value for this parameter if none is
2437 - 0: ADP feature disabled (default)
2438 - 1: ADP feature enabled
2443 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2445 - 0: OTG 2.0 support disabled (default)
2446 - 1: OTG 2.0 support enabled