drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/clk.h>
  24 #include <linux/clk-provider.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/extcon.h>
  29 #include <linux/reset.h>
  30 #include <linux/usb.h>
  31 #include <linux/usb/hcd.h>
  32
  33 #include "core.h"
  34 #include "io.h"
  35
  36 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  37
  38 struct dwc3_rockchip {
  39         int                     num_clocks;
  40         bool                    connected;
  41         struct device           *dev;
  42         struct clk              **clks;
  43         struct dwc3             *dwc;
  44         struct reset_control    *otg_rst;
  45         struct extcon_dev       *edev;
  46         struct notifier_block   device_nb;
  47         struct notifier_block   host_nb;
  48         struct work_struct      otg_work;
  49 };
  50
  51 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  52                                          unsigned long event, void *ptr)
  53 {
  54         struct dwc3_rockchip *rockchip =
  55                 container_of(nb, struct dwc3_rockchip, device_nb);
  56
  57         schedule_work(&rockchip->otg_work);
  58
  59         return NOTIFY_DONE;
  60 }
  61
  62 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  63                                        unsigned long event, void *ptr)
  64 {
  65         struct dwc3_rockchip *rockchip =
  66                 container_of(nb, struct dwc3_rockchip, host_nb);
  67
  68         schedule_work(&rockchip->otg_work);
  69
  70         return NOTIFY_DONE;
  71 }
  72
  73 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  74 {
  75         struct dwc3_rockchip    *rockchip =
  76                 container_of(work, struct dwc3_rockchip, otg_work);
  77         struct dwc3             *dwc = rockchip->dwc;
  78         struct extcon_dev       *edev = rockchip->edev;
  79         struct usb_hcd          *hcd = dev_get_drvdata(&dwc->xhci->dev);
  80         unsigned long           flags;
  81         int                     ret;
  82         u32                     reg;
  83
  84         if (!dwc)
  85                 return;
  86
  87         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  88                 if (rockchip->connected)
  89                         return;
  90
  91                 /*
  92                  * If dr_mode is host only, never to set
  93                  * the mode to the peripheral mode.
  94                  */
  95                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_HOST))
  96                         return;
  97
  98                 /*
  99                  * Assert otg reset can put the dwc in P2 state, it's
 100                  * necessary operation prior to phy power on. However,
 101                  * asserting the otg reset may affect dwc chip operation.
 102                  * The reset will clear all of the dwc controller registers.
 103                  * So we need to reinit the dwc controller after deassert
 104                  * the reset. We use pm runtime to initialize dwc controller.
 105                  * Also, there are no synchronization primitives, meaning
 106                  * the dwc3 core code could at least in theory access chip
 107                  * registers while the reset is asserted, with unknown impact.
 108                  */
 109                 reset_control_assert(rockchip->otg_rst);
 110                 usleep_range(1000, 1200);
 111                 reset_control_deassert(rockchip->otg_rst);
 112
 113                 pm_runtime_get_sync(dwc->dev);
 114
 115                 spin_lock_irqsave(&dwc->lock, flags);
 116                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 117                 spin_unlock_irqrestore(&dwc->lock, flags);
 118
 119                 rockchip->connected = true;
 120                 dev_info(rockchip->dev, "USB peripheral connected\n");
 121         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 122                 if (rockchip->connected)
 123                         return;
 124
 125                 /*
 126                  * If dr_mode is device only, never to
 127                  * set the mode to the host mode.
 128                  */
 129                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 130                         return;
 131
 132                 /*
 133                  * Assert otg reset can put the dwc in P2 state, it's
 134                  * necessary operation prior to phy power on. However,
 135                  * asserting the otg reset may affect dwc chip operation.
 136                  * The reset will clear all of the dwc controller registers.
 137                  * So we need to reinit the dwc controller after deassert
 138                  * the reset. We use pm runtime to initialize dwc controller.
 139                  * Also, there are no synchronization primitives, meaning
 140                  * the dwc3 core code could at least in theory access chip
 141                  * registers while the reset is asserted, with unknown impact.
 142                  */
 143                 reset_control_assert(rockchip->otg_rst);
 144                 usleep_range(1000, 1200);
 145                 reset_control_deassert(rockchip->otg_rst);
 146
 147                 /*
 148                  * Don't abort on errors. If powering on a phy fails,
 149                  * we still need to init dwc controller and add the
 150                  * HCDs to avoid a crash when unloading the driver.
 151                  */
 152                 ret = phy_power_on(dwc->usb2_generic_phy);
 153                 if (ret < 0)
 154                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 155
 156                 ret = phy_power_on(dwc->usb3_generic_phy);
 157                 if (ret < 0) {
 158                         phy_power_off(dwc->usb2_generic_phy);
 159                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 160                 }
 161
 162                 pm_runtime_get_sync(dwc->dev);
 163
 164                 spin_lock_irqsave(&dwc->lock, flags);
 165                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 166                 spin_unlock_irqrestore(&dwc->lock, flags);
 167
 168                 /*
 169                  * The following sleep helps to ensure that inserted USB3
 170                  * Ethernet devices are discovered if already inserted
 171                  * when booting.
 172                  */
 173                 usleep_range(10000, 11000);
 174
 175                 if (hcd->state == HC_STATE_HALT) {
 176                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 177                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 178                 }
 179
 180                 rockchip->connected = true;
 181                 dev_info(rockchip->dev, "USB HOST connected\n");
 182         } else {
 183                 if (!rockchip->connected)
 184                         return;
 185
 186                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 187
 188                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 189                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 190                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 191
 192                         if (hcd->state != HC_STATE_HALT) {
 193                                 usb_remove_hcd(hcd->shared_hcd);
 194                                 usb_remove_hcd(hcd);
 195                         }
 196
 197                         phy_power_off(dwc->usb2_generic_phy);
 198                         phy_power_off(dwc->usb3_generic_phy);
 199                 }
 200
 201                 pm_runtime_put_sync(dwc->dev);
 202
 203                 rockchip->connected = false;
 204                 dev_info(rockchip->dev, "USB unconnected\n");
 205         }
 206 }
 207
 208 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 209 {
 210         int                     ret;
 211         struct device           *dev = rockchip->dev;
 212         struct extcon_dev       *edev;
 213
 214         if (device_property_read_bool(dev, "extcon")) {
 215                 edev = extcon_get_edev_by_phandle(dev, 0);
 216                 if (IS_ERR(edev)) {
 217                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 218                                 dev_err(dev, "couldn't get extcon device\n");
 219                         return PTR_ERR(edev);
 220                 }
 221
 222                 INIT_WORK(&rockchip->otg_work,
 223                           dwc3_rockchip_otg_extcon_evt_work);
 224
 225                 rockchip->device_nb.notifier_call =
 226                                 dwc3_rockchip_device_notifier;
 227                 ret = extcon_register_notifier(edev, EXTCON_USB,
 228                                                &rockchip->device_nb);
 229                 if (ret < 0) {
 230                         dev_err(dev, "failed to register notifier for USB\n");
 231                         return ret;
 232                 }
 233
 234                 rockchip->host_nb.notifier_call =
 235                                 dwc3_rockchip_host_notifier;
 236                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 237                                                &rockchip->host_nb);
 238                 if (ret < 0) {
 239                         dev_err(dev, "failed to register notifier for USB HOST\n");
 240                         extcon_unregister_notifier(edev, EXTCON_USB,
 241                                                    &rockchip->device_nb);
 242                         return ret;
 243                 }
 244
 245                 rockchip->edev = edev;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 252 {
 253         if (!rockchip->edev)
 254                 return;
 255
 256         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 257                                    &rockchip->device_nb);
 258         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 259                                    &rockchip->host_nb);
 260 }
 261
 262 static int dwc3_rockchip_probe(struct platform_device *pdev)
 263 {
 264         struct dwc3_rockchip    *rockchip;
 265         struct device           *dev = &pdev->dev;
 266         struct device_node      *np = dev->of_node, *child;
 267         struct platform_device  *child_pdev;
 268
 269         unsigned int            count;
 270         int                     ret;
 271         int                     i;
 272
 273         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 274
 275         if (!rockchip)
 276                 return -ENOMEM;
 277
 278         count = of_clk_get_parent_count(np);
 279         if (!count)
 280                 return -ENOENT;
 281
 282         rockchip->num_clocks = count;
 283
 284         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 285                                       sizeof(struct clk *), GFP_KERNEL);
 286         if (!rockchip->clks)
 287                 return -ENOMEM;
 288
 289         platform_set_drvdata(pdev, rockchip);
 290
 291         rockchip->dev = dev;
 292
 293         for (i = 0; i < rockchip->num_clocks; i++) {
 294                 struct clk      *clk;
 295
 296                 clk = of_clk_get(np, i);
 297                 if (IS_ERR(clk)) {
 298                         ret = PTR_ERR(clk);
 299                         goto err0;
 300                 }
 301
 302                 ret = clk_prepare_enable(clk);
 303                 if (ret < 0) {
 304                         clk_put(clk);
 305                         goto err0;
 306                 }
 307
 308                 rockchip->clks[i] = clk;
 309         }
 310
 311         pm_runtime_set_active(dev);
 312         pm_runtime_enable(dev);
 313         ret = pm_runtime_get_sync(dev);
 314         if (ret < 0) {
 315                 dev_err(dev, "get_sync failed with err %d\n", ret);
 316                 goto err1;
 317         }
 318
 319         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 320         if (IS_ERR(rockchip->otg_rst)) {
 321                 dev_err(dev, "could not get reset controller\n");
 322                 ret = PTR_ERR(rockchip->otg_rst);
 323                 goto err1;
 324         }
 325
 326         child = of_get_child_by_name(np, "dwc3");
 327         if (!child) {
 328                 dev_err(dev, "failed to find dwc3 core node\n");
 329                 ret = -ENODEV;
 330                 goto err1;
 331         }
 332
 333         /* Allocate and initialize the core */
 334         ret = of_platform_populate(np, NULL, NULL, dev);
 335         if (ret) {
 336                 dev_err(dev, "failed to create dwc3 core\n");
 337                 goto err1;
 338         }
 339
 340         child_pdev = of_find_device_by_node(child);
 341         if (!child_pdev) {
 342                 dev_err(dev, "failed to find dwc3 core device\n");
 343                 ret = -ENODEV;
 344                 goto err2;
 345         }
 346
 347         rockchip->dwc = platform_get_drvdata(child_pdev);
 348         if (!rockchip->dwc) {
 349                 dev_err(dev, "failed to get drvdata dwc3\n");
 350                 ret = -EPROBE_DEFER;
 351                 goto err2;
 352         }
 353
 354         ret = dwc3_rockchip_extcon_register(rockchip);
 355         if (ret < 0)
 356                 goto err2;
 357
 358         if (rockchip->edev) {
 359                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 360                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 361                 pm_runtime_allow(&child_pdev->dev);
 362
 363                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 364                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 365                         struct usb_hcd *hcd =
 366                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 367                         if (!hcd) {
 368                                 dev_err(dev, "fail to get drvdata hcd\n");
 369                                 ret = -EPROBE_DEFER;
 370                                 goto err3;
 371                         }
 372                         if (hcd->state != HC_STATE_HALT) {
 373                                 usb_remove_hcd(hcd->shared_hcd);
 374                                 usb_remove_hcd(hcd);
 375                         }
 376                 }
 377
 378                 pm_runtime_put_sync(dev);
 379
 380                 if ((extcon_get_cable_state_(rockchip->edev,
 381                                              EXTCON_USB) > 0) ||
 382                     (extcon_get_cable_state_(rockchip->edev,
 383                                              EXTCON_USB_HOST) > 0))
 384                         schedule_work(&rockchip->otg_work);
 385         }
 386
 387         return ret;
 388
 389 err3:
 390         dwc3_rockchip_extcon_unregister(rockchip);
 391
 392 err2:
 393         of_platform_depopulate(dev);
 394
 395 err1:
 396         pm_runtime_put_sync(dev);
 397         pm_runtime_disable(dev);
 398
 399 err0:
 400         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 401                 if (!pm_runtime_status_suspended(dev))
 402                         clk_disable(rockchip->clks[i]);
 403                 clk_unprepare(rockchip->clks[i]);
 404                 clk_put(rockchip->clks[i]);
 405         }
 406
 407         return ret;
 408 }
 409
 410 static int dwc3_rockchip_remove(struct platform_device *pdev)
 411 {
 412         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 413         struct device           *dev = &pdev->dev;
 414         int                     i;
 415
 416         dwc3_rockchip_extcon_unregister(rockchip);
 417
 418         of_platform_depopulate(dev);
 419
 420         if (!rockchip->edev)
 421                 pm_runtime_put_sync(dev);
 422
 423         pm_runtime_disable(dev);
 424         pm_runtime_set_suspended(dev);
 425
 426         for (i = 0; i < rockchip->num_clocks; i++) {
 427                 if (!pm_runtime_status_suspended(dev))
 428                         clk_disable(rockchip->clks[i]);
 429                 clk_unprepare(rockchip->clks[i]);
 430                 clk_put(rockchip->clks[i]);
 431         }
 432
 433         return 0;
 434 }
 435
 436 #ifdef CONFIG_PM
 437 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 438 {
 439         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 440         int                     i;
 441
 442         for (i = 0; i < rockchip->num_clocks; i++)
 443                 clk_disable(rockchip->clks[i]);
 444
 445         return 0;
 446 }
 447
 448 static int dwc3_rockchip_runtime_resume(struct device *dev)
 449 {
 450         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 451         int                     i;
 452
 453         for (i = 0; i < rockchip->num_clocks; i++)
 454                 clk_enable(rockchip->clks[i]);
 455
 456         return 0;
 457 }
 458
 459 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 460         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 461                            dwc3_rockchip_runtime_resume, NULL)
 462 };
 463
 464 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 465 #else
 466 #define DEV_PM_OPS      NULL
 467 #endif /* CONFIG_PM */
 468
 469 static const struct of_device_id rockchip_dwc3_match[] = {
 470         { .compatible = "rockchip,rk3399-dwc3" },
 471         { /* Sentinel */ }
 472 };
 473
 474 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 475
 476 static struct platform_driver dwc3_rockchip_driver = {
 477         .probe          = dwc3_rockchip_probe,
 478         .remove         = dwc3_rockchip_remove,
 479         .driver         = {
 480                 .name   = "rockchip-dwc3",
 481                 .of_match_table = rockchip_dwc3_match,
 482                 .pm     = DEV_PM_OPS,
 483         },
 484 };
 485
 486 module_platform_driver(dwc3_rockchip_driver);
 487
 488 MODULE_ALIAS("platform:rockchip-dwc3");
 489 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 490 MODULE_LICENSE("GPL v2");
 491 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");