drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/freezer.h>
  31 #include <linux/iopoll.h>
  32 #include <linux/reset.h>
  33 #include <linux/usb.h>
  34 #include <linux/usb/hcd.h>
  35
  36 #include "core.h"
  37 #include "io.h"
  38 #include "../host/xhci.h"
  39
  40 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  41 #define PERIPHERAL_DISCONNECT_TIMEOUT 1000000 /* us */
  42
  43 struct dwc3_rockchip {
  44         int                     num_clocks;
  45         bool                    connected;
  46         bool                    skip_suspend;
  47         bool                    suspended;
  48         struct device           *dev;
  49         struct clk              **clks;
  50         struct dwc3             *dwc;
  51         struct reset_control    *otg_rst;
  52         struct extcon_dev       *edev;
  53         struct notifier_block   device_nb;
  54         struct notifier_block   host_nb;
  55         struct work_struct      otg_work;
  56         struct mutex            lock;
  57 };
  58
  59 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  60                                          unsigned long event, void *ptr)
  61 {
  62         struct dwc3_rockchip *rockchip =
  63                 container_of(nb, struct dwc3_rockchip, device_nb);
  64
  65         if (!rockchip->suspended)
  66                 schedule_work(&rockchip->otg_work);
  67
  68         return NOTIFY_DONE;
  69 }
  70
  71 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  72                                        unsigned long event, void *ptr)
  73 {
  74         struct dwc3_rockchip *rockchip =
  75                 container_of(nb, struct dwc3_rockchip, host_nb);
  76
  77         if (!rockchip->suspended)
  78                 schedule_work(&rockchip->otg_work);
  79
  80         return NOTIFY_DONE;
  81 }
  82
  83 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  84 {
  85         struct dwc3_rockchip    *rockchip =
  86                 container_of(work, struct dwc3_rockchip, otg_work);
  87         struct dwc3             *dwc = rockchip->dwc;
  88         struct extcon_dev       *edev = rockchip->edev;
  89         struct usb_hcd          *hcd;
  90         struct xhci_hcd         *xhci;
  91         unsigned long           flags;
  92         int                     ret;
  93         int                     val;
  94         u32                     reg, count;
  95
  96         mutex_lock(&rockchip->lock);
  97
  98         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  99                 if (rockchip->connected)
 100                         goto out;
 101
 102                 /*
 103                  * If dr_mode is host only, never to set
 104                  * the mode to the peripheral mode.
 105                  */
 106                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 107                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 108                         goto out;
 109                 }
 110
 111                 /*
 112                  * Assert otg reset can put the dwc in P2 state, it's
 113                  * necessary operation prior to phy power on. However,
 114                  * asserting the otg reset may affect dwc chip operation.
 115                  * The reset will clear all of the dwc controller registers.
 116                  * So we need to reinit the dwc controller after deassert
 117                  * the reset. We use pm runtime to initialize dwc controller.
 118                  * Also, there are no synchronization primitives, meaning
 119                  * the dwc3 core code could at least in theory access chip
 120                  * registers while the reset is asserted, with unknown impact.
 121                  */
 122                 if (!rockchip->skip_suspend) {
 123                         reset_control_assert(rockchip->otg_rst);
 124                         usleep_range(1000, 1200);
 125                         reset_control_deassert(rockchip->otg_rst);
 126
 127                         pm_runtime_get_sync(rockchip->dev);
 128                         pm_runtime_get_sync(dwc->dev);
 129                 } else {
 130                         rockchip->skip_suspend = false;
 131                 }
 132
 133                 spin_lock_irqsave(&dwc->lock, flags);
 134                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 135                 spin_unlock_irqrestore(&dwc->lock, flags);
 136
 137                 rockchip->connected = true;
 138                 dev_info(rockchip->dev, "USB peripheral connected\n");
 139         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 140                 if (rockchip->connected)
 141                         goto out;
 142
 143                 if (rockchip->skip_suspend) {
 144                         pm_runtime_put(dwc->dev);
 145                         pm_runtime_put(rockchip->dev);
 146                         rockchip->skip_suspend = false;
 147                 }
 148
 149                 /*
 150                  * If dr_mode is device only, never to
 151                  * set the mode to the host mode.
 152                  */
 153                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 154                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 155                         goto out;
 156                 }
 157
 158                 /*
 159                  * Assert otg reset can put the dwc in P2 state, it's
 160                  * necessary operation prior to phy power on. However,
 161                  * asserting the otg reset may affect dwc chip operation.
 162                  * The reset will clear all of the dwc controller registers.
 163                  * So we need to reinit the dwc controller after deassert
 164                  * the reset. We use pm runtime to initialize dwc controller.
 165                  * Also, there are no synchronization primitives, meaning
 166                  * the dwc3 core code could at least in theory access chip
 167                  * registers while the reset is asserted, with unknown impact.
 168                  */
 169                 reset_control_assert(rockchip->otg_rst);
 170                 usleep_range(1000, 1200);
 171                 reset_control_deassert(rockchip->otg_rst);
 172
 173                 /*
 174                  * In usb3 phy init, it will access usb3 module, so we need
 175                  * to resume rockchip dev before phy init to make sure usb3
 176                  * pd is enabled.
 177                  */
 178                 pm_runtime_get_sync(rockchip->dev);
 179
 180                 /*
 181                  * Don't abort on errors. If powering on a phy fails,
 182                  * we still need to init dwc controller and add the
 183                  * HCDs to avoid a crash when unloading the driver.
 184                  */
 185                 ret = phy_power_on(dwc->usb2_generic_phy);
 186                 if (ret < 0)
 187                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 188
 189                 ret = phy_power_on(dwc->usb3_generic_phy);
 190                 if (ret < 0) {
 191                         phy_power_off(dwc->usb2_generic_phy);
 192                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 193                 }
 194
 195                 pm_runtime_get_sync(dwc->dev);
 196
 197                 spin_lock_irqsave(&dwc->lock, flags);
 198                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 199                 spin_unlock_irqrestore(&dwc->lock, flags);
 200
 201                 /*
 202                  * The following sleep helps to ensure that inserted USB3
 203                  * Ethernet devices are discovered if already inserted
 204                  * when booting.
 205                  */
 206                 usleep_range(10000, 11000);
 207
 208                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 209
 210                 if (hcd->state == HC_STATE_HALT) {
 211                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 212                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 213                 }
 214
 215                 rockchip->connected = true;
 216                 dev_info(rockchip->dev, "USB HOST connected\n");
 217         } else {
 218                 if (!rockchip->connected)
 219                         goto out;
 220
 221                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 222
 223                 /*
 224                  * xhci does not support runtime pm. If HCDs are not removed
 225                  * here and and re-added after a cable is inserted, USB3
 226                  * connections will not work.
 227                  * A clean(er) solution would be to implement runtime pm
 228                  * support in xhci. After that is available, this code should
 229                  * be removed.
 230                  * HCDs have to be removed here to prevent attempts by the
 231                  * xhci code to access xhci registers after the call to
 232                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 233                  * in a crash under certain circumstances (this was observed
 234                  * on 3399 chromebook if the system is running on battery).
 235                  */
 236                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 237                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 238                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 239                         xhci = hcd_to_xhci(hcd);
 240
 241                         if (hcd->state != HC_STATE_HALT) {
 242                                 xhci->xhc_state |= XHCI_STATE_REMOVING;
 243                                 count = 0;
 244
 245                                 /*
 246                                  * Wait until XHCI controller resume from
 247                                  * PM suspend, them we can remove hcd safely.
 248                                  */
 249                                 while (dwc->xhci->dev.power.is_suspended) {
 250                                         if (++count > 100) {
 251                                                 dev_err(rockchip->dev,
 252                                                         "wait for XHCI resume 10s timeout!\n");
 253                                                 goto out;
 254                                         }
 255                                         msleep(100);
 256                                 }
 257
 258 #ifdef CONFIG_FREEZER
 259                                 /*
 260                                  * usb_remove_hcd() may call usb_disconnect() to
 261                                  * remove a block device pluged in before.
 262                                  * Unfortunately, the block layer suspend/resume
 263                                  * path is fundamentally broken due to freezable
 264                                  * kthreads and workqueue and may deadlock if a
 265                                  * block device gets removed while resume is in
 266                                  * progress.
 267                                  *
 268                                  * We need to add a ugly hack to avoid removing
 269                                  * hcd and kicking off device removal while
 270                                  * freezer is active. This is a joke but does
 271                                  * avoid this particular deadlock when test with
 272                                  * USB-C HUB and USB2/3 flash drive.
 273                                  */
 274                                 while (pm_freezing)
 275                                         usleep_range(10000, 11000);
 276 #endif
 277
 278                                 usb_remove_hcd(hcd->shared_hcd);
 279                                 usb_remove_hcd(hcd);
 280                         }
 281
 282                         phy_power_off(dwc->usb2_generic_phy);
 283                         phy_power_off(dwc->usb3_generic_phy);
 284                 }
 285
 286                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE) {
 287                         ret = readx_poll_timeout(atomic_read,
 288                                                  &dwc->dev->power.usage_count,
 289                                                  val,
 290                                                  val < 2 && !dwc->connected,
 291                                                  1000,
 292                                                  PERIPHERAL_DISCONNECT_TIMEOUT);
 293                         if (ret < 0) {
 294                                 rockchip->skip_suspend = true;
 295                                 dev_warn(rockchip->dev, "Peripheral disconnect timeout\n");
 296                         }
 297                 }
 298
 299                 if (!rockchip->skip_suspend) {
 300                         pm_runtime_put_sync_suspend(dwc->dev);
 301                         pm_runtime_put_sync_suspend(rockchip->dev);
 302                 }
 303
 304                 rockchip->connected = false;
 305                 dev_info(rockchip->dev, "USB unconnected\n");
 306         }
 307
 308 out:
 309         mutex_unlock(&rockchip->lock);
 310 }
 311
 312 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 313 {
 314         int                     ret;
 315         struct device           *dev = rockchip->dev;
 316         struct extcon_dev       *edev;
 317
 318         if (device_property_read_bool(dev, "extcon")) {
 319                 edev = extcon_get_edev_by_phandle(dev, 0);
 320                 if (IS_ERR(edev)) {
 321                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 322                                 dev_err(dev, "couldn't get extcon device\n");
 323                         return PTR_ERR(edev);
 324                 }
 325
 326                 INIT_WORK(&rockchip->otg_work,
 327                           dwc3_rockchip_otg_extcon_evt_work);
 328
 329                 rockchip->device_nb.notifier_call =
 330                                 dwc3_rockchip_device_notifier;
 331                 ret = extcon_register_notifier(edev, EXTCON_USB,
 332                                                &rockchip->device_nb);
 333                 if (ret < 0) {
 334                         dev_err(dev, "failed to register notifier for USB\n");
 335                         return ret;
 336                 }
 337
 338                 rockchip->host_nb.notifier_call =
 339                                 dwc3_rockchip_host_notifier;
 340                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 341                                                &rockchip->host_nb);
 342                 if (ret < 0) {
 343                         dev_err(dev, "failed to register notifier for USB HOST\n");
 344                         extcon_unregister_notifier(edev, EXTCON_USB,
 345                                                    &rockchip->device_nb);
 346                         return ret;
 347                 }
 348
 349                 rockchip->edev = edev;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 356 {
 357         if (!rockchip->edev)
 358                 return;
 359
 360         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 361                                    &rockchip->device_nb);
 362         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 363                                    &rockchip->host_nb);
 364         cancel_work_sync(&rockchip->otg_work);
 365 }
 366
 367 static int dwc3_rockchip_probe(struct platform_device *pdev)
 368 {
 369         struct dwc3_rockchip    *rockchip;
 370         struct device           *dev = &pdev->dev;
 371         struct device_node      *np = dev->of_node, *child;
 372         struct platform_device  *child_pdev;
 373
 374         unsigned int            count;
 375         int                     ret;
 376         int                     i;
 377
 378         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 379
 380         if (!rockchip)
 381                 return -ENOMEM;
 382
 383         count = of_clk_get_parent_count(np);
 384         if (!count)
 385                 return -ENOENT;
 386
 387         rockchip->num_clocks = count;
 388
 389         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 390                                       sizeof(struct clk *), GFP_KERNEL);
 391         if (!rockchip->clks)
 392                 return -ENOMEM;
 393
 394         platform_set_drvdata(pdev, rockchip);
 395
 396         mutex_init(&rockchip->lock);
 397
 398         rockchip->dev = dev;
 399
 400         mutex_lock(&rockchip->lock);
 401
 402         for (i = 0; i < rockchip->num_clocks; i++) {
 403                 struct clk      *clk;
 404
 405                 clk = of_clk_get(np, i);
 406                 if (IS_ERR(clk)) {
 407                         ret = PTR_ERR(clk);
 408                         goto err0;
 409                 }
 410
 411                 ret = clk_prepare_enable(clk);
 412                 if (ret < 0) {
 413                         clk_put(clk);
 414                         goto err0;
 415                 }
 416
 417                 rockchip->clks[i] = clk;
 418         }
 419
 420         pm_runtime_set_active(dev);
 421         pm_runtime_enable(dev);
 422         ret = pm_runtime_get_sync(dev);
 423         if (ret < 0) {
 424                 dev_err(dev, "get_sync failed with err %d\n", ret);
 425                 goto err1;
 426         }
 427
 428         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 429         if (IS_ERR(rockchip->otg_rst)) {
 430                 dev_err(dev, "could not get reset controller\n");
 431                 ret = PTR_ERR(rockchip->otg_rst);
 432                 goto err1;
 433         }
 434
 435         child = of_get_child_by_name(np, "dwc3");
 436         if (!child) {
 437                 dev_err(dev, "failed to find dwc3 core node\n");
 438                 ret = -ENODEV;
 439                 goto err1;
 440         }
 441
 442         /* Allocate and initialize the core */
 443         ret = of_platform_populate(np, NULL, NULL, dev);
 444         if (ret) {
 445                 dev_err(dev, "failed to create dwc3 core\n");
 446                 goto err1;
 447         }
 448
 449         child_pdev = of_find_device_by_node(child);
 450         if (!child_pdev) {
 451                 dev_err(dev, "failed to find dwc3 core device\n");
 452                 ret = -ENODEV;
 453                 goto err2;
 454         }
 455
 456         rockchip->dwc = platform_get_drvdata(child_pdev);
 457         if (!rockchip->dwc) {
 458                 dev_err(dev, "failed to get drvdata dwc3\n");
 459                 ret = -EPROBE_DEFER;
 460                 goto err2;
 461         }
 462
 463         ret = dwc3_rockchip_extcon_register(rockchip);
 464         if (ret < 0)
 465                 goto err2;
 466
 467         if (rockchip->edev) {
 468                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 469                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 470                         struct usb_hcd *hcd =
 471                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 472                         if (!hcd) {
 473                                 dev_err(dev, "fail to get drvdata hcd\n");
 474                                 ret = -EPROBE_DEFER;
 475                                 goto err3;
 476                         }
 477                         if (hcd->state != HC_STATE_HALT) {
 478                                 usb_remove_hcd(hcd->shared_hcd);
 479                                 usb_remove_hcd(hcd);
 480                         }
 481                 }
 482
 483                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 484                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 485                 pm_runtime_allow(&child_pdev->dev);
 486                 pm_runtime_suspend(&child_pdev->dev);
 487                 pm_runtime_put_sync(dev);
 488
 489                 if ((extcon_get_cable_state_(rockchip->edev,
 490                                              EXTCON_USB) > 0) ||
 491                     (extcon_get_cable_state_(rockchip->edev,
 492                                              EXTCON_USB_HOST) > 0))
 493                         schedule_work(&rockchip->otg_work);
 494         }
 495
 496         mutex_unlock(&rockchip->lock);
 497
 498         return ret;
 499
 500 err3:
 501         dwc3_rockchip_extcon_unregister(rockchip);
 502
 503 err2:
 504         of_platform_depopulate(dev);
 505
 506 err1:
 507         pm_runtime_put_sync(dev);
 508         pm_runtime_disable(dev);
 509
 510 err0:
 511         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 512                 if (!pm_runtime_status_suspended(dev))
 513                         clk_disable(rockchip->clks[i]);
 514                 clk_unprepare(rockchip->clks[i]);
 515                 clk_put(rockchip->clks[i]);
 516         }
 517
 518         mutex_unlock(&rockchip->lock);
 519
 520         return ret;
 521 }
 522
 523 static int dwc3_rockchip_remove(struct platform_device *pdev)
 524 {
 525         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 526         struct device           *dev = &pdev->dev;
 527         int                     i;
 528
 529         dwc3_rockchip_extcon_unregister(rockchip);
 530
 531         /* Restore hcd state before unregistering xhci */
 532         if (rockchip->edev && !rockchip->connected) {
 533                 struct usb_hcd *hcd =
 534                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 535
 536                 pm_runtime_get_sync(dev);
 537
 538                 /*
 539                  * The xhci code does not expect that HCDs have been removed.
 540                  * It will unconditionally call usb_remove_hcd() when the xhci
 541                  * driver is unloaded in of_platform_depopulate(). This results
 542                  * in a crash if the HCDs were already removed. To avoid this
 543                  * crash, add the HCDs here as dummy operation.
 544                  * This code should be removed after pm runtime support
 545                  * has been added to xhci.
 546                  */
 547                 if (hcd->state == HC_STATE_HALT) {
 548                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 549                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 550                 }
 551         }
 552
 553         of_platform_depopulate(dev);
 554
 555         pm_runtime_put_sync(dev);
 556         pm_runtime_disable(dev);
 557
 558         for (i = 0; i < rockchip->num_clocks; i++) {
 559                 if (!pm_runtime_status_suspended(dev))
 560                         clk_disable(rockchip->clks[i]);
 561                 clk_unprepare(rockchip->clks[i]);
 562                 clk_put(rockchip->clks[i]);
 563         }
 564
 565         return 0;
 566 }
 567
 568 #ifdef CONFIG_PM
 569 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 570 {
 571         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 572         int                     i;
 573
 574         for (i = 0; i < rockchip->num_clocks; i++)
 575                 clk_disable(rockchip->clks[i]);
 576
 577         device_init_wakeup(dev, false);
 578
 579         return 0;
 580 }
 581
 582 static int dwc3_rockchip_runtime_resume(struct device *dev)
 583 {
 584         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 585         int                     i;
 586
 587         for (i = 0; i < rockchip->num_clocks; i++)
 588                 clk_enable(rockchip->clks[i]);
 589
 590         device_init_wakeup(dev, true);
 591
 592         return 0;
 593 }
 594
 595 static int dwc3_rockchip_suspend(struct device *dev)
 596 {
 597         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 598         struct dwc3 *dwc = rockchip->dwc;
 599
 600         rockchip->suspended = true;
 601         cancel_work_sync(&rockchip->otg_work);
 602
 603         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 604                 /*
 605                  * If USB HOST connected, we will do phy power
 606                  * on in extcon evt work, so need to do phy
 607                  * power off in suspend. And we just power off
 608                  * USB2 PHY here because USB3 PHY power on operation
 609                  * need to be done while DWC3 controller is in P2
 610                  * state, but after resume DWC3 controller is in
 611                  * P0 state. So we put USB3 PHY in power on state.
 612                  */
 613                 if (extcon_get_cable_state_(rockchip->edev,
 614                                             EXTCON_USB_HOST) > 0)
 615                         phy_power_off(dwc->usb2_generic_phy);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int dwc3_rockchip_resume(struct device *dev)
 622 {
 623         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 624         struct dwc3 *dwc = rockchip->dwc;
 625
 626         rockchip->suspended = false;
 627
 628         if (rockchip->edev)
 629                 schedule_work(&rockchip->otg_work);
 630
 631         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 632                 if (extcon_get_cable_state_(rockchip->edev,
 633                                             EXTCON_USB_HOST) > 0)
 634                         phy_power_on(dwc->usb2_generic_phy);
 635         }
 636
 637         return 0;
 638 }
 639
 640 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 641         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 642         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 643                            dwc3_rockchip_runtime_resume, NULL)
 644 };
 645
 646 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 647 #else
 648 #define DEV_PM_OPS      NULL
 649 #endif /* CONFIG_PM */
 650
 651 static const struct of_device_id rockchip_dwc3_match[] = {
 652         { .compatible = "rockchip,rk3399-dwc3" },
 653         { /* Sentinel */ }
 654 };
 655
 656 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 657
 658 static struct platform_driver dwc3_rockchip_driver = {
 659         .probe          = dwc3_rockchip_probe,
 660         .remove         = dwc3_rockchip_remove,
 661         .driver         = {
 662                 .name   = "rockchip-dwc3",
 663                 .of_match_table = rockchip_dwc3_match,
 664                 .pm     = DEV_PM_OPS,
 665         },
 666 };
 667
 668 module_platform_driver(dwc3_rockchip_driver);
 669
 670 MODULE_ALIAS("platform:rockchip-dwc3");
 671 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 672 MODULE_LICENSE("GPL v2");
 673 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");