drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/reset.h>
  31 #include <linux/usb.h>
  32 #include <linux/usb/hcd.h>
  33
  34 #include "core.h"
  35 #include "io.h"
  36
  37 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  38
  39 struct dwc3_rockchip {
  40         int                     num_clocks;
  41         bool                    connected;
  42         bool                    suspended;
  43         struct device           *dev;
  44         struct clk              **clks;
  45         struct dwc3             *dwc;
  46         struct reset_control    *otg_rst;
  47         struct extcon_dev       *edev;
  48         struct notifier_block   device_nb;
  49         struct notifier_block   host_nb;
  50         struct work_struct      otg_work;
  51         struct mutex            lock;
  52 };
  53
  54 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  55                                          unsigned long event, void *ptr)
  56 {
  57         struct dwc3_rockchip *rockchip =
  58                 container_of(nb, struct dwc3_rockchip, device_nb);
  59
  60         if (!rockchip->suspended)
  61                 schedule_work(&rockchip->otg_work);
  62
  63         return NOTIFY_DONE;
  64 }
  65
  66 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  67                                        unsigned long event, void *ptr)
  68 {
  69         struct dwc3_rockchip *rockchip =
  70                 container_of(nb, struct dwc3_rockchip, host_nb);
  71
  72         if (!rockchip->suspended)
  73                 schedule_work(&rockchip->otg_work);
  74
  75         return NOTIFY_DONE;
  76 }
  77
  78 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  79 {
  80         struct dwc3_rockchip    *rockchip =
  81                 container_of(work, struct dwc3_rockchip, otg_work);
  82         struct dwc3             *dwc = rockchip->dwc;
  83         struct extcon_dev       *edev = rockchip->edev;
  84         struct usb_hcd          *hcd = dev_get_drvdata(&dwc->xhci->dev);
  85         unsigned long           flags;
  86         int                     ret;
  87         u32                     reg;
  88
  89         if (!dwc)
  90                 return;
  91
  92         mutex_lock(&rockchip->lock);
  93
  94         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  95                 if (rockchip->connected)
  96                         goto out;
  97
  98                 /*
  99                  * If dr_mode is host only, never to set
 100                  * the mode to the peripheral mode.
 101                  */
 102                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_HOST))
 103                         goto out;
 104
 105                 /*
 106                  * Assert otg reset can put the dwc in P2 state, it's
 107                  * necessary operation prior to phy power on. However,
 108                  * asserting the otg reset may affect dwc chip operation.
 109                  * The reset will clear all of the dwc controller registers.
 110                  * So we need to reinit the dwc controller after deassert
 111                  * the reset. We use pm runtime to initialize dwc controller.
 112                  * Also, there are no synchronization primitives, meaning
 113                  * the dwc3 core code could at least in theory access chip
 114                  * registers while the reset is asserted, with unknown impact.
 115                  */
 116                 reset_control_assert(rockchip->otg_rst);
 117                 usleep_range(1000, 1200);
 118                 reset_control_deassert(rockchip->otg_rst);
 119
 120                 pm_runtime_get_sync(dwc->dev);
 121
 122                 spin_lock_irqsave(&dwc->lock, flags);
 123                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 124                 spin_unlock_irqrestore(&dwc->lock, flags);
 125
 126                 rockchip->connected = true;
 127                 dev_info(rockchip->dev, "USB peripheral connected\n");
 128         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 129                 if (rockchip->connected)
 130                         goto out;
 131
 132                 /*
 133                  * If dr_mode is device only, never to
 134                  * set the mode to the host mode.
 135                  */
 136                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 137                         goto out;
 138
 139                 /*
 140                  * Assert otg reset can put the dwc in P2 state, it's
 141                  * necessary operation prior to phy power on. However,
 142                  * asserting the otg reset may affect dwc chip operation.
 143                  * The reset will clear all of the dwc controller registers.
 144                  * So we need to reinit the dwc controller after deassert
 145                  * the reset. We use pm runtime to initialize dwc controller.
 146                  * Also, there are no synchronization primitives, meaning
 147                  * the dwc3 core code could at least in theory access chip
 148                  * registers while the reset is asserted, with unknown impact.
 149                  */
 150                 reset_control_assert(rockchip->otg_rst);
 151                 usleep_range(1000, 1200);
 152                 reset_control_deassert(rockchip->otg_rst);
 153
 154                 /*
 155                  * Don't abort on errors. If powering on a phy fails,
 156                  * we still need to init dwc controller and add the
 157                  * HCDs to avoid a crash when unloading the driver.
 158                  */
 159                 ret = phy_power_on(dwc->usb2_generic_phy);
 160                 if (ret < 0)
 161                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 162
 163                 ret = phy_power_on(dwc->usb3_generic_phy);
 164                 if (ret < 0) {
 165                         phy_power_off(dwc->usb2_generic_phy);
 166                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 167                 }
 168
 169                 pm_runtime_get_sync(dwc->dev);
 170
 171                 spin_lock_irqsave(&dwc->lock, flags);
 172                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 173                 spin_unlock_irqrestore(&dwc->lock, flags);
 174
 175                 /*
 176                  * The following sleep helps to ensure that inserted USB3
 177                  * Ethernet devices are discovered if already inserted
 178                  * when booting.
 179                  */
 180                 usleep_range(10000, 11000);
 181
 182                 if (hcd->state == HC_STATE_HALT) {
 183                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 184                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 185                 }
 186
 187                 rockchip->connected = true;
 188                 dev_info(rockchip->dev, "USB HOST connected\n");
 189         } else {
 190                 if (!rockchip->connected)
 191                         goto out;
 192
 193                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 194
 195                 /*
 196                  * xhci does not support runtime pm. If HCDs are not removed
 197                  * here and and re-added after a cable is inserted, USB3
 198                  * connections will not work.
 199                  * A clean(er) solution would be to implement runtime pm
 200                  * support in xhci. After that is available, this code should
 201                  * be removed.
 202                  * HCDs have to be removed here to prevent attempts by the
 203                  * xhci code to access xhci registers after the call to
 204                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 205                  * in a crash under certain circumstances (this was observed
 206                  * on 3399 chromebook if the system is running on battery).
 207                  */
 208                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 209                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 210                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 211
 212                         if (hcd->state != HC_STATE_HALT) {
 213                                 usb_remove_hcd(hcd->shared_hcd);
 214                                 usb_remove_hcd(hcd);
 215                         }
 216
 217                         phy_power_off(dwc->usb2_generic_phy);
 218                         phy_power_off(dwc->usb3_generic_phy);
 219                 }
 220
 221                 pm_runtime_put_sync(dwc->dev);
 222
 223                 rockchip->connected = false;
 224                 dev_info(rockchip->dev, "USB unconnected\n");
 225         }
 226
 227 out:
 228         mutex_unlock(&rockchip->lock);
 229 }
 230
 231 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 232 {
 233         int                     ret;
 234         struct device           *dev = rockchip->dev;
 235         struct extcon_dev       *edev;
 236
 237         if (device_property_read_bool(dev, "extcon")) {
 238                 edev = extcon_get_edev_by_phandle(dev, 0);
 239                 if (IS_ERR(edev)) {
 240                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 241                                 dev_err(dev, "couldn't get extcon device\n");
 242                         return PTR_ERR(edev);
 243                 }
 244
 245                 INIT_WORK(&rockchip->otg_work,
 246                           dwc3_rockchip_otg_extcon_evt_work);
 247
 248                 rockchip->device_nb.notifier_call =
 249                                 dwc3_rockchip_device_notifier;
 250                 ret = extcon_register_notifier(edev, EXTCON_USB,
 251                                                &rockchip->device_nb);
 252                 if (ret < 0) {
 253                         dev_err(dev, "failed to register notifier for USB\n");
 254                         return ret;
 255                 }
 256
 257                 rockchip->host_nb.notifier_call =
 258                                 dwc3_rockchip_host_notifier;
 259                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 260                                                &rockchip->host_nb);
 261                 if (ret < 0) {
 262                         dev_err(dev, "failed to register notifier for USB HOST\n");
 263                         extcon_unregister_notifier(edev, EXTCON_USB,
 264                                                    &rockchip->device_nb);
 265                         return ret;
 266                 }
 267
 268                 rockchip->edev = edev;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 275 {
 276         if (!rockchip->edev)
 277                 return;
 278
 279         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 280                                    &rockchip->device_nb);
 281         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 282                                    &rockchip->host_nb);
 283         cancel_work_sync(&rockchip->otg_work);
 284 }
 285
 286 static int dwc3_rockchip_probe(struct platform_device *pdev)
 287 {
 288         struct dwc3_rockchip    *rockchip;
 289         struct device           *dev = &pdev->dev;
 290         struct device_node      *np = dev->of_node, *child;
 291         struct platform_device  *child_pdev;
 292
 293         unsigned int            count;
 294         int                     ret;
 295         int                     i;
 296
 297         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 298
 299         if (!rockchip)
 300                 return -ENOMEM;
 301
 302         count = of_clk_get_parent_count(np);
 303         if (!count)
 304                 return -ENOENT;
 305
 306         rockchip->num_clocks = count;
 307
 308         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 309                                       sizeof(struct clk *), GFP_KERNEL);
 310         if (!rockchip->clks)
 311                 return -ENOMEM;
 312
 313         platform_set_drvdata(pdev, rockchip);
 314
 315         mutex_init(&rockchip->lock);
 316
 317         rockchip->dev = dev;
 318
 319         mutex_lock(&rockchip->lock);
 320
 321         for (i = 0; i < rockchip->num_clocks; i++) {
 322                 struct clk      *clk;
 323
 324                 clk = of_clk_get(np, i);
 325                 if (IS_ERR(clk)) {
 326                         ret = PTR_ERR(clk);
 327                         goto err0;
 328                 }
 329
 330                 ret = clk_prepare_enable(clk);
 331                 if (ret < 0) {
 332                         clk_put(clk);
 333                         goto err0;
 334                 }
 335
 336                 rockchip->clks[i] = clk;
 337         }
 338
 339         pm_runtime_set_active(dev);
 340         pm_runtime_enable(dev);
 341         ret = pm_runtime_get_sync(dev);
 342         if (ret < 0) {
 343                 dev_err(dev, "get_sync failed with err %d\n", ret);
 344                 goto err1;
 345         }
 346
 347         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 348         if (IS_ERR(rockchip->otg_rst)) {
 349                 dev_err(dev, "could not get reset controller\n");
 350                 ret = PTR_ERR(rockchip->otg_rst);
 351                 goto err1;
 352         }
 353
 354         child = of_get_child_by_name(np, "dwc3");
 355         if (!child) {
 356                 dev_err(dev, "failed to find dwc3 core node\n");
 357                 ret = -ENODEV;
 358                 goto err1;
 359         }
 360
 361         /* Allocate and initialize the core */
 362         ret = of_platform_populate(np, NULL, NULL, dev);
 363         if (ret) {
 364                 dev_err(dev, "failed to create dwc3 core\n");
 365                 goto err1;
 366         }
 367
 368         child_pdev = of_find_device_by_node(child);
 369         if (!child_pdev) {
 370                 dev_err(dev, "failed to find dwc3 core device\n");
 371                 ret = -ENODEV;
 372                 goto err2;
 373         }
 374
 375         rockchip->dwc = platform_get_drvdata(child_pdev);
 376         if (!rockchip->dwc) {
 377                 dev_err(dev, "failed to get drvdata dwc3\n");
 378                 ret = -EPROBE_DEFER;
 379                 goto err2;
 380         }
 381
 382         ret = dwc3_rockchip_extcon_register(rockchip);
 383         if (ret < 0)
 384                 goto err2;
 385
 386         if (rockchip->edev) {
 387                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 388                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 389                 pm_runtime_allow(&child_pdev->dev);
 390
 391                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 392                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 393                         struct usb_hcd *hcd =
 394                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 395                         if (!hcd) {
 396                                 dev_err(dev, "fail to get drvdata hcd\n");
 397                                 ret = -EPROBE_DEFER;
 398                                 goto err3;
 399                         }
 400                         if (hcd->state != HC_STATE_HALT) {
 401                                 usb_remove_hcd(hcd->shared_hcd);
 402                                 usb_remove_hcd(hcd);
 403                         }
 404                 }
 405
 406                 pm_runtime_put_sync(dev);
 407
 408                 if ((extcon_get_cable_state_(rockchip->edev,
 409                                              EXTCON_USB) > 0) ||
 410                     (extcon_get_cable_state_(rockchip->edev,
 411                                              EXTCON_USB_HOST) > 0))
 412                         schedule_work(&rockchip->otg_work);
 413         }
 414
 415         mutex_unlock(&rockchip->lock);
 416
 417         return ret;
 418
 419 err3:
 420         dwc3_rockchip_extcon_unregister(rockchip);
 421
 422 err2:
 423         of_platform_depopulate(dev);
 424
 425 err1:
 426         pm_runtime_put_sync(dev);
 427         pm_runtime_disable(dev);
 428
 429 err0:
 430         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 431                 if (!pm_runtime_status_suspended(dev))
 432                         clk_disable(rockchip->clks[i]);
 433                 clk_unprepare(rockchip->clks[i]);
 434                 clk_put(rockchip->clks[i]);
 435         }
 436
 437         mutex_unlock(&rockchip->lock);
 438
 439         return ret;
 440 }
 441
 442 static int dwc3_rockchip_remove(struct platform_device *pdev)
 443 {
 444         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 445         struct device           *dev = &pdev->dev;
 446         int                     i;
 447
 448         dwc3_rockchip_extcon_unregister(rockchip);
 449
 450         /* Restore hcd state before unregistering xhci */
 451         if (rockchip->edev && !rockchip->connected) {
 452                 struct usb_hcd *hcd =
 453                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 454
 455                 pm_runtime_get_sync(dev);
 456
 457                 /*
 458                  * The xhci code does not expect that HCDs have been removed.
 459                  * It will unconditionally call usb_remove_hcd() when the xhci
 460                  * driver is unloaded in of_platform_depopulate(). This results
 461                  * in a crash if the HCDs were already removed. To avoid this
 462                  * crash, add the HCDs here as dummy operation.
 463                  * This code should be removed after pm runtime support
 464                  * has been added to xhci.
 465                  */
 466                 if (hcd->state == HC_STATE_HALT) {
 467                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 468                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 469                 }
 470         }
 471
 472         of_platform_depopulate(dev);
 473
 474         pm_runtime_put_sync(dev);
 475         pm_runtime_disable(dev);
 476
 477         for (i = 0; i < rockchip->num_clocks; i++) {
 478                 if (!pm_runtime_status_suspended(dev))
 479                         clk_disable(rockchip->clks[i]);
 480                 clk_unprepare(rockchip->clks[i]);
 481                 clk_put(rockchip->clks[i]);
 482         }
 483
 484         return 0;
 485 }
 486
 487 #ifdef CONFIG_PM
 488 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 489 {
 490         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 491         int                     i;
 492
 493         for (i = 0; i < rockchip->num_clocks; i++)
 494                 clk_disable(rockchip->clks[i]);
 495
 496         return 0;
 497 }
 498
 499 static int dwc3_rockchip_runtime_resume(struct device *dev)
 500 {
 501         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 502         int                     i;
 503
 504         for (i = 0; i < rockchip->num_clocks; i++)
 505                 clk_enable(rockchip->clks[i]);
 506
 507         return 0;
 508 }
 509
 510 static int dwc3_rockchip_suspend(struct device *dev)
 511 {
 512         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 513
 514         rockchip->suspended = true;
 515         cancel_work_sync(&rockchip->otg_work);
 516
 517         return 0;
 518 }
 519
 520 static int dwc3_rockchip_resume(struct device *dev)
 521 {
 522         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 523
 524         rockchip->suspended = false;
 525
 526         return 0;
 527 }
 528
 529 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 530         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 531         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 532                            dwc3_rockchip_runtime_resume, NULL)
 533 };
 534
 535 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 536 #else
 537 #define DEV_PM_OPS      NULL
 538 #endif /* CONFIG_PM */
 539
 540 static const struct of_device_id rockchip_dwc3_match[] = {
 541         { .compatible = "rockchip,rk3399-dwc3" },
 542         { /* Sentinel */ }
 543 };
 544
 545 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 546
 547 static struct platform_driver dwc3_rockchip_driver = {
 548         .probe          = dwc3_rockchip_probe,
 549         .remove         = dwc3_rockchip_remove,
 550         .driver         = {
 551                 .name   = "rockchip-dwc3",
 552                 .of_match_table = rockchip_dwc3_match,
 553                 .pm     = DEV_PM_OPS,
 554         },
 555 };
 556
 557 module_platform_driver(dwc3_rockchip_driver);
 558
 559 MODULE_ALIAS("platform:rockchip-dwc3");
 560 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 561 MODULE_LICENSE("GPL v2");
 562 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");