2 * core.h - DesignWare HS OTG Controller common declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
40 #include <linux/phy/phy.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/usb/gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/phy.h>
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
54 #define DWC2_TRACE_SCHEDULER no_printk
55 #define DWC2_TRACE_SCHEDULER_VB no_printk
57 /* Detailed scheduler tracing, but won't overwhelm console */
58 #define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
62 /* Verbose scheduler tracing */
63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
78 static inline u32 dwc2_readl(const void __iomem *addr)
80 u32 value = __raw_readl(addr);
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
90 static inline void dwc2_writel(u32 value, void __iomem *addr)
92 __raw_writel(value, addr);
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
100 #ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
105 /* Normal architectures just use readl/write */
106 static inline u32 dwc2_readl(const void __iomem *addr)
111 static inline void dwc2_writel(u32 value, void __iomem *addr)
115 #ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
121 /* Maximum number of Endpoints/HostChannels */
122 #define MAX_EPS_CHANNELS 16
124 /* Maximum number of dwc2 clocks */
125 #define DWC2_MAX_CLKS 3
127 /* dwc2-hsotg declarations */
128 static const char * const dwc2_hsotg_supply_names[] = {
129 "vusb_d", /* digital USB supply, 1.2V */
130 "vusb_a", /* analog USB supply, 1.1V */
136 * Unfortunately there seems to be a limit of the amount of data that can
137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
138 * packets (which practically means 1 packet and 63 bytes of data) when the
141 * This means if we are wanting to move >127 bytes of data, we need to
142 * split the transactions up, but just doing one packet at a time does
143 * not work (this may be an implicit DATA0 PID on first packet of the
144 * transaction) and doing 2 packets is outside the controller's limits.
146 * If we try to lower the MPS size for EP0, then no transfers work properly
147 * for EP0, and the system will fail basic enumeration. As no cause for this
148 * has currently been found, we cannot support any large IN transfers for
151 #define EP0_MPS_LIMIT 64
154 struct dwc2_hsotg_req;
157 * struct dwc2_hsotg_ep - driver endpoint definition.
158 * @ep: The gadget layer representation of the endpoint.
159 * @name: The driver generated name for the endpoint.
160 * @queue: Queue of requests for this endpoint.
161 * @parent: Reference back to the parent device structure.
162 * @req: The current request that the endpoint is processing. This is
163 * used to indicate an request has been loaded onto the endpoint
164 * and has yet to be completed (maybe due to data move, or simply
165 * awaiting an ack from the core all the data has been completed).
166 * @debugfs: File entry for debugfs file for this endpoint.
167 * @lock: State lock to protect contents of endpoint.
168 * @dir_in: Set to true if this endpoint is of the IN direction, which
169 * means that it is sending data to the Host.
170 * @index: The index for the endpoint registers.
171 * @mc: Multi Count - number of transactions per microframe
172 * @interval - Interval for periodic endpoints, in frames or microframes.
173 * @name: The name array passed to the USB core.
174 * @halted: Set if the endpoint has been halted.
175 * @periodic: Set if this is a periodic ep, such as Interrupt
176 * @isochronous: Set if this is a isochronous ep
177 * @send_zlp: Set if we need to send a zero-length packet.
178 * @total_data: The total number of data bytes done.
179 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
180 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
181 * @last_load: The offset of data for the last start of request.
182 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
183 * @target_frame: Targeted frame num to setup next ISOC transfer
184 * @frame_overrun: Indicates SOF number overrun in DSTS
186 * This is the driver's state for each registered enpoint, allowing it
187 * to keep track of transactions that need doing. Each endpoint has a
188 * lock to protect the state, to try and avoid using an overall lock
189 * for the host controller as much as possible.
191 * For periodic IN endpoints, we have fifo_size and fifo_load to try
192 * and keep track of the amount of data in the periodic FIFO for each
193 * of these as we don't have a status register that tells us how much
194 * is in each of them. (note, this may actually be useless information
195 * as in shared-fifo mode periodic in acts like a single-frame packet
196 * buffer than a fifo)
198 struct dwc2_hsotg_ep {
200 struct list_head queue;
201 struct dwc2_hsotg *parent;
202 struct dwc2_hsotg_req *req;
203 struct dentry *debugfs;
205 unsigned long total_data;
206 unsigned int size_loaded;
207 unsigned int last_load;
208 unsigned int fifo_load;
209 unsigned short fifo_size;
210 unsigned short fifo_index;
212 unsigned char dir_in;
215 unsigned char interval;
217 unsigned int halted:1;
218 unsigned int periodic:1;
219 unsigned int isochronous:1;
220 unsigned int send_zlp:1;
221 unsigned int target_frame;
222 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
229 * struct dwc2_hsotg_req - data transfer request
230 * @req: The USB gadget request
231 * @queue: The list of requests for the endpoint this is queued for.
232 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
234 struct dwc2_hsotg_req {
235 struct usb_request req;
236 struct list_head queue;
240 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
241 #define call_gadget(_hs, _entry) \
243 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
244 (_hs)->driver && (_hs)->driver->_entry) { \
245 spin_unlock(&_hs->lock); \
246 (_hs)->driver->_entry(&(_hs)->gadget); \
247 spin_lock(&_hs->lock); \
251 #define call_gadget(_hs, _entry) do {} while (0)
255 struct dwc2_host_chan;
259 DWC2_L0, /* On state */
260 DWC2_L1, /* LPM sleep state */
261 DWC2_L2, /* USB suspend state */
262 DWC2_L3, /* Off state */
266 * Gadget periodic tx fifo sizes as used by legacy driver
267 * EP0 is not included
269 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
270 768, 0, 0, 0, 0, 0, 0, 0}
272 /* Gadget ep0 states */
273 enum dwc2_ep0_state {
282 * struct dwc2_core_params - Parameters for configuring the core
284 * @otg_cap: Specifies the OTG capabilities.
285 * 0 - HNP and SRP capable
286 * 1 - SRP Only capable
287 * 2 - No HNP/SRP capable (always available)
288 * Defaults to best available option (0, 1, then 2)
289 * @otg_ver: OTG version supported
292 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
293 * the data FIFOs. The driver will automatically detect the
294 * value for this parameter if none is specified.
295 * 0 - Slave (always available)
296 * 1 - DMA (default, if available)
297 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
298 * address DMA mode or descriptor DMA mode for accessing
299 * the data FIFOs. The driver will automatically detect the
300 * value for this if none is specified.
302 * 1 - Descriptor DMA (default, if available)
303 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
304 * address DMA mode or descriptor DMA mode for accessing
305 * the data FIFOs in Full Speed mode only. The driver
306 * will automatically detect the value for this if none is
309 * 1 - Descriptor DMA in FS (default, if available)
310 * @speed: Specifies the maximum speed of operation in host and
311 * device mode. The actual speed depends on the speed of
312 * the attached device and the value of phy_type.
314 * (default when phy_type is UTMI+ or ULPI)
316 * (default when phy_type is Full Speed)
317 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
318 * 1 - Allow dynamic FIFO sizing (default, if available)
319 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
321 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
322 * dynamic FIFO sizing is enabled
324 * Actual maximum value is autodetected and also
326 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
327 * in host mode when dynamic FIFO sizing is enabled
329 * Actual maximum value is autodetected and also
331 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
332 * host mode when dynamic FIFO sizing is enabled
334 * Actual maximum value is autodetected and also
336 * @max_transfer_size: The maximum transfer size supported, in bytes
338 * Actual maximum value is autodetected and also
340 * @max_packet_count: The maximum number of packets in a transfer
342 * Actual maximum value is autodetected and also
344 * @host_channels: The number of host channel registers to use
346 * Actual maximum value is autodetected and also
348 * @phy_type: Specifies the type of PHY interface to use. By default,
349 * the driver will automatically detect the phy_type.
353 * Defaults to best available option (2, 1, then 0)
354 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
355 * is applicable for a phy_type of UTMI+ or ULPI. (For a
356 * ULPI phy_type, this parameter indicates the data width
357 * between the MAC and the ULPI Wrapper.) Also, this
358 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
359 * parameter was set to "8 and 16 bits", meaning that the
360 * core has been configured to work at either data path
362 * 8 or 16 (default 16 if available)
363 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
364 * data rate. This parameter is only applicable if phy_type
366 * 0 - single data rate ULPI interface with 8 bit wide
368 * 1 - double data rate ULPI interface with 4 bit wide
370 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
371 * external supply to drive the VBus
372 * 0 - Internal supply (default)
373 * 1 - External supply
374 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
375 * speed PHY. This parameter is only applicable if phy_type
379 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
382 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
383 * when attached to a Full Speed or Low Speed device in
385 * 0 - Don't support low power mode (default)
386 * 1 - Support low power mode
387 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
388 * when connected to a Low Speed device in host
389 * mode. This parameter is applicable only if
390 * host_support_fs_ls_low_power is enabled.
392 * (default when phy_type is UTMI+ or ULPI)
394 * (default when phy_type is Full Speed)
395 * @ts_dline: Enable Term Select Dline pulsing
398 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
399 * 0 - No (default for core < 2.92a)
400 * 1 - Yes (default for core >= 2.92a)
401 * @ahbcfg: This field allows the default value of the GAHBCFG
402 * register to be overridden
403 * -1 - GAHBCFG value will be set to 0x06
405 * all others - GAHBCFG value will be overridden with
407 * Not all bits can be controlled like this, the
408 * bits defined by GAHBCFG_CTRL_MASK are controlled
409 * by the driver and are ignored in this
410 * configuration value.
411 * @uframe_sched: True to enable the microframe scheduler
412 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
413 * Disable CONIDSTSCHNG controller interrupt in such
417 * @hibernation: Specifies whether the controller support hibernation.
418 * If hibernation is enabled, the controller will enter
419 * hibernation in both peripheral and host mode when
424 * The following parameters may be specified when starting the module. These
425 * parameters define how the DWC_otg controller should be configured. A
426 * value of -1 (or any other out of range value) for any parameter means
427 * to read the value from hardware (if possible) or use the builtin
428 * default described above.
430 struct dwc2_core_params {
432 * Don't add any non-int members here, this will break
433 * dwc2_set_all_params!
439 int dma_desc_fs_enable;
441 int enable_dynamic_fifo;
442 int en_multiple_tx_fifo;
443 int host_rx_fifo_size;
444 int host_nperio_tx_fifo_size;
445 int host_perio_tx_fifo_size;
446 int max_transfer_size;
447 int max_packet_count;
452 int phy_ulpi_ext_vbus;
455 int host_support_fs_ls_low_power;
456 int host_ls_low_power_phy_clk;
461 int external_id_pin_ctl;
466 * struct dwc2_hw_params - Autodetected parameters.
468 * These parameters are the various parameters read from hardware
469 * registers during initialization. They typically contain the best
470 * supported or maximum value that can be configured in the
471 * corresponding dwc2_core_params value.
473 * The values that are not in dwc2_core_params are documented below.
475 * @op_mode Mode of Operation
476 * 0 - HNP- and SRP-Capable OTG (Host & Device)
477 * 1 - SRP-Capable OTG (Host & Device)
478 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
479 * 3 - SRP-Capable Device
481 * 5 - SRP-Capable Host
487 * @power_optimized Are power optimizations enabled?
488 * @num_dev_ep Number of device endpoints available
489 * @num_dev_perio_in_ep Number of device periodic IN endpoints
491 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
494 * @host_perio_tx_q_depth
495 * Host Mode Periodic Request Queue Depth
498 * Non-Periodic Request Queue Depth
500 * @hs_phy_type High-speed PHY interface type
501 * 0 - High-speed interface not supported
505 * @fs_phy_type Full-speed PHY interface type
506 * 0 - Full speed interface not supported
507 * 1 - Dedicated full speed interface
508 * 2 - FS pins shared with UTMI+ pins
509 * 3 - FS pins shared with ULPI pins
510 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
511 * @utmi_phy_data_width UTMI+ PHY data width
515 * @snpsid: Value from SNPSID register
516 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
518 struct dwc2_hw_params {
521 unsigned dma_desc_enable:1;
522 unsigned dma_desc_fs_enable:1;
523 unsigned enable_dynamic_fifo:1;
524 unsigned en_multiple_tx_fifo:1;
525 unsigned host_rx_fifo_size:16;
526 unsigned host_nperio_tx_fifo_size:16;
527 unsigned dev_nperio_tx_fifo_size:16;
528 unsigned host_perio_tx_fifo_size:16;
529 unsigned nperio_tx_q_depth:3;
530 unsigned host_perio_tx_q_depth:3;
531 unsigned dev_token_q_depth:5;
532 unsigned max_transfer_size:26;
533 unsigned max_packet_count:11;
534 unsigned host_channels:5;
535 unsigned hs_phy_type:2;
536 unsigned fs_phy_type:2;
537 unsigned i2c_enable:1;
538 unsigned num_dev_ep:4;
539 unsigned num_dev_perio_in_ep:4;
540 unsigned total_fifo_size:16;
541 unsigned power_optimized:1;
542 unsigned utmi_phy_data_width:2;
547 /* Size of control and EP0 buffers */
548 #define DWC2_CTRL_BUFF_SIZE 8
551 * struct dwc2_gregs_backup - Holds global registers state before entering partial
553 * @gotgctl: Backup of GOTGCTL register
554 * @gintmsk: Backup of GINTMSK register
555 * @gahbcfg: Backup of GAHBCFG register
556 * @gusbcfg: Backup of GUSBCFG register
557 * @grxfsiz: Backup of GRXFSIZ register
558 * @gnptxfsiz: Backup of GNPTXFSIZ register
559 * @gi2cctl: Backup of GI2CCTL register
560 * @hptxfsiz: Backup of HPTXFSIZ register
561 * @gdfifocfg: Backup of GDFIFOCFG register
562 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
563 * @gpwrdn: Backup of GPWRDN register
565 struct dwc2_gregs_backup {
576 u32 dtxfsiz[MAX_EPS_CHANNELS];
582 * struct dwc2_dregs_backup - Holds device registers state before entering partial
584 * @dcfg: Backup of DCFG register
585 * @dctl: Backup of DCTL register
586 * @daintmsk: Backup of DAINTMSK register
587 * @diepmsk: Backup of DIEPMSK register
588 * @doepmsk: Backup of DOEPMSK register
589 * @diepctl: Backup of DIEPCTL register
590 * @dieptsiz: Backup of DIEPTSIZ register
591 * @diepdma: Backup of DIEPDMA register
592 * @doepctl: Backup of DOEPCTL register
593 * @doeptsiz: Backup of DOEPTSIZ register
594 * @doepdma: Backup of DOEPDMA register
596 struct dwc2_dregs_backup {
602 u32 diepctl[MAX_EPS_CHANNELS];
603 u32 dieptsiz[MAX_EPS_CHANNELS];
604 u32 diepdma[MAX_EPS_CHANNELS];
605 u32 doepctl[MAX_EPS_CHANNELS];
606 u32 doeptsiz[MAX_EPS_CHANNELS];
607 u32 doepdma[MAX_EPS_CHANNELS];
612 * struct dwc2_hregs_backup - Holds host registers state before entering partial
614 * @hcfg: Backup of HCFG register
615 * @haintmsk: Backup of HAINTMSK register
616 * @hcintmsk: Backup of HCINTMSK register
617 * @hptr0: Backup of HPTR0 register
618 * @hfir: Backup of HFIR register
620 struct dwc2_hregs_backup {
623 u32 hcintmsk[MAX_EPS_CHANNELS];
630 * Constants related to high speed periodic scheduling
632 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
633 * reservation point of view it's assumed that the schedule goes right back to
634 * the beginning after the end of the schedule.
636 * What does that mean for scheduling things with a long interval? It means
637 * we'll reserve time for them in every possible microframe that they could
638 * ever be scheduled in. ...but we'll still only actually schedule them as
639 * often as they were requested.
641 * We keep our schedule in a "bitmap" structure. This simplifies having
642 * to keep track of and merge intervals: we just let the bitmap code do most
643 * of the heavy lifting. In a way scheduling is much like memory allocation.
645 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
646 * supposed to schedule for periodic transfers). That's according to spec.
648 * Note that though we only schedule 80% of each microframe, the bitmap that we
649 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
650 * space for each uFrame).
653 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
654 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
655 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
656 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
658 #define DWC2_US_PER_UFRAME 125
659 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
661 #define DWC2_HS_SCHEDULE_UFRAMES 8
662 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
663 DWC2_HS_PERIODIC_US_PER_UFRAME)
666 * Constants related to low speed scheduling
668 * For high speed we schedule every 1us. For low speed that's a bit overkill,
669 * so we make up a unit called a "slice" that's worth 25us. There are 40
670 * slices in a full frame and we can schedule 36 of those (90%) for periodic
673 * Our low speed schedule can be as short as 1 frame or could be longer. When
674 * we only schedule 1 frame it means that we'll need to reserve a time every
675 * frame even for things that only transfer very rarely, so something that runs
676 * every 2048 frames will get time reserved in every frame. Our low speed
677 * schedule can be longer and we'll be able to handle more overlap, but that
678 * will come at increased memory cost and increased time to schedule.
680 * Note: one other advantage of a short low speed schedule is that if we mess
681 * up and miss scheduling we can jump in and use any of the slots that we
682 * happened to reserve.
684 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
685 * the schedule. There will be one schedule per TT.
688 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
690 #define DWC2_US_PER_SLICE 25
691 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
693 #define DWC2_ROUND_US_TO_SLICE(us) \
694 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
697 #define DWC2_LS_PERIODIC_US_PER_FRAME \
699 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
700 (DWC2_LS_PERIODIC_US_PER_FRAME / \
703 #define DWC2_LS_SCHEDULE_FRAMES 1
704 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
705 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
708 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
709 * and periodic schedules
711 * These are common for both host and peripheral modes:
713 * @dev: The struct device pointer
714 * @regs: Pointer to controller regs
715 * @hw_params: Parameters that were autodetected from the
717 * @core_params: Parameters that define how the core should be configured
718 * @op_state: The operational State, during transitions (a_host=>
719 * a_peripheral and b_device=>b_host) this may not match
720 * the core, but allows the software to determine
722 * @dr_mode: Requested mode of operation, one of following:
723 * - USB_DR_MODE_PERIPHERAL
726 * @hcd_enabled Host mode sub-driver initialization indicator.
727 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
728 * @ll_hw_enabled Status of low-level hardware resources.
729 * @phy: The otg phy transceiver structure for phy control.
730 * @uphy: The otg phy transceiver structure for old USB phy control.
731 * @plat: The platform specific configuration data. This can be removed once
732 * all SoCs support usb transceiver.
733 * @supplies: Definition of USB power supplies
734 * @phyif: PHY interface width
735 * @lock: Spinlock that protects all the driver data structures
736 * @priv: Stores a pointer to the struct usb_hcd
737 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
738 * transfer are in process of being queued
739 * @srp_success: Stores status of SRP request in the case of a FS PHY
740 * with an I2C interface
741 * @wq_otg: Workqueue object used for handling of some interrupts
742 * @wf_otg: Work object for handling Connector ID Status Change
744 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
745 * @lx_state: Lx state of connected device
746 * @gregs_backup: Backup of global registers during suspend
747 * @dregs_backup: Backup of device registers during suspend
748 * @hregs_backup: Backup of host registers during suspend
750 * These are for host mode:
752 * @flags: Flags for handling root port state changes
753 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
754 * Transfers associated with these QHs are not currently
755 * assigned to a host channel.
756 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
757 * Transfers associated with these QHs are currently
758 * assigned to a host channel.
759 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
760 * non-periodic schedule
761 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
762 * list of QHs for periodic transfers that are _not_
763 * scheduled for the next frame. Each QH in the list has an
764 * interval counter that determines when it needs to be
765 * scheduled for execution. This scheduling mechanism
766 * allows only a simple calculation for periodic bandwidth
767 * used (i.e. must assume that all periodic transfers may
768 * need to execute in the same frame). However, it greatly
769 * simplifies scheduling and should be sufficient for the
770 * vast majority of OTG hosts, which need to connect to a
771 * small number of peripherals at one time. Items move from
772 * this list to periodic_sched_ready when the QH interval
773 * counter is 0 at SOF.
774 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
775 * the next frame, but have not yet been assigned to host
776 * channels. Items move from this list to
777 * periodic_sched_assigned as host channels become
778 * available during the current frame.
779 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
780 * frame that are assigned to host channels. Items move
781 * from this list to periodic_sched_queued as the
782 * transactions for the QH are queued to the DWC_otg
784 * @periodic_sched_queued: List of periodic QHs that have been queued for
785 * execution. Items move from this list to either
786 * periodic_sched_inactive or periodic_sched_ready when the
787 * channel associated with the transfer is released. If the
788 * interval for the QH is 1, the item moves to
789 * periodic_sched_ready because it must be rescheduled for
790 * the next frame. Otherwise, the item moves to
791 * periodic_sched_inactive.
792 * @split_order: List keeping track of channels doing splits, in order.
793 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
794 * This value is in microseconds per (micro)frame. The
795 * assumption is that all periodic transfers may occur in
796 * the same (micro)frame.
797 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
798 * host is in high speed mode; low speed schedules are
799 * stored elsewhere since we need one per TT.
800 * @frame_number: Frame number read from the core at SOF. The value ranges
801 * from 0 to HFNUM_MAX_FRNUM.
802 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
803 * SOF enable/disable.
804 * @free_hc_list: Free host channels in the controller. This is a list of
805 * struct dwc2_host_chan items.
806 * @periodic_channels: Number of host channels assigned to periodic transfers.
807 * Currently assuming that there is a dedicated host
808 * channel for each periodic transaction and at least one
809 * host channel is available for non-periodic transactions.
810 * @non_periodic_channels: Number of host channels assigned to non-periodic
812 * @available_host_channels Number of host channels available for the microframe
814 * @hc_ptr_array: Array of pointers to the host channel descriptors.
815 * Allows accessing a host channel descriptor given the
816 * host channel number. This is useful in interrupt
818 * @status_buf: Buffer used for data received during the status phase of
819 * a control transfer.
820 * @status_buf_dma: DMA address for status_buf
821 * @start_work: Delayed work for handling host A-cable connection
822 * @reset_work: Delayed work for handling a port reset
823 * @otg_port: OTG port number
824 * @frame_list: Frame list
825 * @frame_list_dma: Frame list DMA address
826 * @frame_list_sz: Frame list size
827 * @desc_gen_cache: Kmem cache for generic descriptors
828 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
830 * These are for peripheral mode:
832 * @driver: USB gadget driver
833 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
834 * @num_of_eps: Number of available EPs (excluding EP0)
835 * @debug_root: Root directrory for debugfs.
836 * @debug_file: Main status file for debugfs.
837 * @debug_testmode: Testmode status file for debugfs.
838 * @debug_fifo: FIFO status file for debugfs.
839 * @ep0_reply: Request used for ep0 reply.
840 * @ep0_buff: Buffer for EP0 reply data, if needed.
841 * @ctrl_buff: Buffer for EP0 control requests.
842 * @ctrl_req: Request for EP0 control packets.
843 * @ep0_state: EP0 control transfers state
844 * @test_mode: USB test mode requested by the host
845 * @eps: The endpoints being supplied to the gadget framework
846 * @g_using_dma: Indicate if dma usage is enabled
847 * @g_rx_fifo_sz: Contains rx fifo size value
848 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
849 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
854 /** Params detected from hardware */
855 struct dwc2_hw_params hw_params;
856 /** Params to actually use */
857 struct dwc2_core_params *core_params;
858 enum usb_otg_state op_state;
859 enum usb_dr_mode dr_mode;
860 unsigned int hcd_enabled:1;
861 unsigned int gadget_enabled:1;
862 unsigned int ll_hw_enabled:1;
865 struct work_struct phy_rst_work;
866 struct usb_phy *uphy;
867 struct dwc2_hsotg_plat *plat;
868 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
874 struct clk *clks[DWC2_MAX_CLKS];
876 unsigned int queuing_high_bandwidth:1;
877 unsigned int srp_success:1;
879 struct workqueue_struct *wq_otg;
880 struct work_struct wf_otg;
881 struct timer_list wkp_timer;
882 enum dwc2_lx_state lx_state;
883 struct dwc2_gregs_backup gr_backup;
884 struct dwc2_dregs_backup dr_backup;
885 struct dwc2_hregs_backup hr_backup;
887 struct dentry *debug_root;
888 struct debugfs_regset32 *regset;
890 /* DWC OTG HW Release versions */
891 #define DWC2_CORE_REV_2_71a 0x4f54271a
892 #define DWC2_CORE_REV_2_90a 0x4f54290a
893 #define DWC2_CORE_REV_2_92a 0x4f54292a
894 #define DWC2_CORE_REV_2_94a 0x4f54294a
895 #define DWC2_CORE_REV_3_00a 0x4f54300a
897 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
898 union dwc2_hcd_internal_flags {
901 unsigned port_connect_status_change:1;
902 unsigned port_connect_status:1;
903 unsigned port_reset_change:1;
904 unsigned port_enable_change:1;
905 unsigned port_suspend_change:1;
906 unsigned port_over_current_change:1;
907 unsigned port_l1_change:1;
908 unsigned reserved:25;
912 struct list_head non_periodic_sched_inactive;
913 struct list_head non_periodic_sched_active;
914 struct list_head *non_periodic_qh_ptr;
915 struct list_head periodic_sched_inactive;
916 struct list_head periodic_sched_ready;
917 struct list_head periodic_sched_assigned;
918 struct list_head periodic_sched_queued;
919 struct list_head split_order;
921 unsigned long hs_periodic_bitmap[
922 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
924 u16 periodic_qh_count;
930 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
931 #define FRAME_NUM_ARRAY_SIZE 1000
932 u16 *frame_num_array;
933 u16 *last_frame_num_array;
935 int dumped_frame_num_array;
938 struct list_head free_hc_list;
939 int periodic_channels;
940 int non_periodic_channels;
941 int available_host_channels;
942 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
944 dma_addr_t status_buf_dma;
945 #define DWC2_HCD_STATUS_BUF_SIZE 64
947 struct delayed_work start_work;
948 struct delayed_work reset_work;
951 dma_addr_t frame_list_dma;
953 struct kmem_cache *desc_gen_cache;
954 struct kmem_cache *desc_hsisoc_cache;
960 u32 hfnum_7_samples_a;
961 u64 hfnum_7_frrem_accum_a;
962 u32 hfnum_0_samples_a;
963 u64 hfnum_0_frrem_accum_a;
964 u32 hfnum_other_samples_a;
965 u64 hfnum_other_frrem_accum_a;
967 u32 hfnum_7_samples_b;
968 u64 hfnum_7_frrem_accum_b;
969 u32 hfnum_0_samples_b;
970 u64 hfnum_0_frrem_accum_b;
971 u32 hfnum_other_samples_b;
972 u64 hfnum_other_frrem_accum_b;
974 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
976 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
977 /* Gadget structures */
978 struct usb_gadget_driver *driver;
980 unsigned int dedicated_fifos:1;
981 unsigned char num_of_eps;
984 struct usb_request *ep0_reply;
985 struct usb_request *ctrl_req;
988 enum dwc2_ep0_state ep0_state;
991 struct usb_gadget gadget;
992 unsigned int enabled:1;
993 unsigned int connected:1;
994 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
995 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
998 u32 g_np_g_tx_fifo_sz;
999 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
1000 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1003 /* Reasons for halting a host channel */
1004 enum dwc2_halt_status {
1005 DWC2_HC_XFER_NO_HALT_STATUS,
1006 DWC2_HC_XFER_COMPLETE,
1007 DWC2_HC_XFER_URB_COMPLETE,
1012 DWC2_HC_XFER_XACT_ERR,
1013 DWC2_HC_XFER_FRAME_OVERRUN,
1014 DWC2_HC_XFER_BABBLE_ERR,
1015 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1016 DWC2_HC_XFER_AHB_ERR,
1017 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1018 DWC2_HC_XFER_URB_DEQUEUE,
1022 * The following functions support initialization of the core driver component
1023 * and the DWC_otg controller
1025 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
1026 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1027 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1028 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
1030 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1032 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1035 * Common core Functions.
1036 * The following functions support managing the DWC_otg controller in either
1037 * device or host mode.
1039 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1040 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1041 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1043 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1044 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1046 /* This function should be called on every hardware interrupt. */
1047 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1049 /* OTG Core Parameters */
1052 * Specifies the OTG capabilities. The driver will automatically
1053 * detect the value for this parameter if none is specified.
1054 * 0 - HNP and SRP capable (default)
1055 * 1 - SRP Only capable
1056 * 2 - No HNP/SRP capable
1058 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
1059 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
1060 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
1061 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
1064 * Specifies whether to use slave or DMA mode for accessing the data
1065 * FIFOs. The driver will automatically detect the value for this
1066 * parameter if none is specified.
1068 * 1 - DMA (default, if available)
1070 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
1073 * When DMA mode is enabled specifies whether to use
1074 * address DMA or DMA Descritor mode for accessing the data
1075 * FIFOs in device mode. The driver will automatically detect
1076 * the value for this parameter if none is specified.
1078 * 1 - DMA Descriptor(default, if available)
1080 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
1083 * When DMA mode is enabled specifies whether to use
1084 * address DMA or DMA Descritor mode with full speed devices
1085 * for accessing the data FIFOs in host mode.
1087 * 1 - FS DMA Descriptor(default, if available)
1089 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
1093 * Specifies the maximum speed of operation in host and device mode.
1094 * The actual speed depends on the speed of the attached device and
1095 * the value of phy_type. The actual speed depends on the speed of the
1097 * 0 - High Speed (default)
1100 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
1101 #define DWC2_SPEED_PARAM_HIGH 0
1102 #define DWC2_SPEED_PARAM_FULL 1
1105 * Specifies whether low power mode is supported when attached
1106 * to a Full Speed or Low Speed device in host mode.
1108 * 0 - Don't support low power mode (default)
1109 * 1 - Support low power mode
1111 extern void dwc2_set_param_host_support_fs_ls_low_power(
1112 struct dwc2_hsotg *hsotg, int val);
1115 * Specifies the PHY clock rate in low power mode when connected to a
1116 * Low Speed device in host mode. This parameter is applicable only if
1117 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
1118 * then defaults to 6 MHZ otherwise 48 MHZ.
1123 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
1125 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
1126 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
1129 * 0 - Use cC FIFO size parameters
1130 * 1 - Allow dynamic FIFO sizing (default)
1132 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
1136 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
1137 * FIFO sizing is enabled.
1138 * 16 to 32768 (default 1024)
1140 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
1143 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
1144 * when Dynamic FIFO sizing is enabled in the core.
1145 * 16 to 32768 (default 256)
1147 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1151 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
1152 * FIFO sizing is enabled.
1153 * 16 to 32768 (default 256)
1155 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1159 * The maximum transfer size supported in bytes.
1160 * 2047 to 65,535 (default 65,535)
1162 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
1165 * The maximum number of packets in a transfer.
1166 * 15 to 511 (default 511)
1168 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
1171 * The number of host channel registers to use.
1172 * 1 to 16 (default 11)
1173 * Note: The FPGA configuration supports a maximum of 11 host channels.
1175 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
1178 * Specifies the type of PHY interface to use. By default, the driver
1179 * will automatically detect the phy_type.
1181 * 0 - Full Speed PHY
1182 * 1 - UTMI+ (default)
1185 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
1186 #define DWC2_PHY_TYPE_PARAM_FS 0
1187 #define DWC2_PHY_TYPE_PARAM_UTMI 1
1188 #define DWC2_PHY_TYPE_PARAM_ULPI 2
1191 * Specifies the UTMI+ Data Width. This parameter is
1192 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1193 * PHY_TYPE, this parameter indicates the data width between
1194 * the MAC and the ULPI Wrapper.) Also, this parameter is
1195 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1196 * to "8 and 16 bits", meaning that the core has been
1197 * configured to work at either data path width.
1199 * 8 or 16 bits (default 16)
1201 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
1204 * Specifies whether the ULPI operates at double or single
1205 * data rate. This parameter is only applicable if PHY_TYPE is
1208 * 0 - single data rate ULPI interface with 8 bit wide data
1210 * 1 - double data rate ULPI interface with 4 bit wide data
1213 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
1216 * Specifies whether to use the internal or external supply to
1217 * drive the vbus with a ULPI phy.
1219 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
1220 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1221 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1224 * Specifies whether to use the I2Cinterface for full speed PHY. This
1225 * parameter is only applicable if PHY_TYPE is FS.
1229 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
1231 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
1233 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
1236 * Specifies whether dedicated transmit FIFOs are
1237 * enabled for non periodic IN endpoints in device mode
1241 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1244 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
1246 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
1248 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
1250 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1251 const struct dwc2_core_params *params);
1253 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1255 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1257 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1258 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1261 * The following functions check the controller's OTG operation mode
1262 * capability (GHWCFG2.OTG_MODE).
1264 * These functions can be used before the internal hsotg->hw_params
1265 * are read in and cached so they always read directly from the
1268 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1269 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1270 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1271 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1274 * Returns the mode of operation, host or device
1276 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1278 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1280 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1282 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1286 * Dump core registers and SPRAM
1288 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1289 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1290 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1293 * Return OTG version - either 1.3 or 2.0
1295 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1297 /* Gadget defines */
1298 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1299 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1300 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1301 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1302 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1303 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1305 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1306 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1307 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1308 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1309 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1310 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
1312 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1314 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1316 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1318 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1320 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1322 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1323 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1324 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1327 #define dwc2_is_device_connected(hsotg) (0)
1328 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1330 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1334 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1335 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1336 extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1337 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1338 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1339 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1340 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1341 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1343 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1345 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1348 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1349 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1350 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1351 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1352 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
1354 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1356 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1361 #endif /* __DWC2_CORE_H__ */