2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
17 * @brief Hardware drivers.
21 * @brief Struct definitions for the Invensense mpu driver.
24 #ifndef _INV_MPU_IIO_H_
25 #define _INV_MPU_IIO_H_
27 #include <linux/i2c.h>
28 #include <linux/kfifo.h>
29 #include <linux/miscdevice.h>
30 #include <linux/spinlock.h>
31 #ifdef INV_KERNEL_3_10
32 #include <linux/mpu.h>
33 #include <linux/iio/iio.h>
34 #include <linux/iio/buffer.h>
36 #include <linux/mpu.h>
45 * struct inv_reg_map_s - Notable slave registers.
46 * @sample_rate_div: Divider applied to gyro output rate.
47 * @lpf: Configures internal LPF.
48 * @bank_sel: Selects between memory banks.
49 * @user_ctrl: Enables/resets the FIFO.
50 * @fifo_en: Determines which data will appear in FIFO.
51 * @gyro_config: gyro config register.
52 * @accl_config: accel config register
53 * @fifo_count_h: Upper byte of FIFO count.
54 * @fifo_r_w: FIFO register.
55 * @raw_gyro Address of first gyro register.
56 * @raw_accl Address of first accel register.
57 * @temperature temperature register
58 * @int_enable: Interrupt enable register.
59 * @int_status: Interrupt flags.
60 * @pwr_mgmt_1: Controls chip's power state and clock source.
61 * @pwr_mgmt_2: Controls power state of individual sensors.
62 * @mem_start_addr: Address of first memory read.
63 * @mem_r_w: Access to memory.
64 * @prgm_strt_addrh firmware program start address register
66 struct inv_reg_map_s {
101 * struct test_setup_t - set up parameters for self test.
102 * @gyro_sens: sensitity for gyro.
103 * @sample_rate: sample rate, i.e, fifo rate.
104 * @lpf: low pass filter.
105 * @fsr: full scale range.
106 * @accl_fs: accel full scale range.
107 * @accl_sens: accel sensitivity
109 struct test_setup_t {
119 * struct inv_hw_s - Other important hardware information.
120 * @num_reg: Number of registers on device.
121 * @name: name of the chip
129 * struct inv_chip_config_s - Cached chip configuration data.
130 * @fsr: Full scale range.
131 * @lpf: Digital low pass filter frequency.
132 * @accl_fs: accel full scale range.
133 * @self_test_run_once flag for self test run ever.
134 * @has_footer: MPU3050 specific work around.
135 * @has_compass: has compass or not.
136 * @enable: master enable to enable output
137 * @accl_enable: enable accel functionality
138 * @accl_fifo_enable: enable accel data output
139 * @gyro_enable: enable gyro functionality
140 * @gyro_fifo_enable: enable gyro data output
141 * @compass_enable: enable compass
142 * @compass_fifo_enable: enable compass data output
143 * @is_asleep: 1 if chip is powered down.
144 * @dmp_on: dmp is on/off.
145 * @dmp_int_on: dmp interrupt on/off.
146 * @dmp_event_int_on: dmp event interrupt on/off.
147 * @firmware_loaded: flag indicate firmware loaded or not.
148 * @lpa_mod: low power mode.
149 * @tap_on: tap on/off.
150 * @quaternion_on: send quaternion data on/off.
151 * @display_orient_on: display orientation on/off.
152 * @normal_compass_measure: discard first compass data after reset.
153 * @smd_enable: disable/enable SMD function.
154 * @lpa_freq: low power frequency
155 * @prog_start_addr: firmware program start address.
156 * @fifo_rate: current FIFO update rate.
157 * @new_fifo_rate: set FIFO update rate
158 * @dmp_output_rate: current dmp output rate.
160 struct inv_chip_config_s {
164 u32 self_test_run_once:1;
169 u32 accl_fifo_enable:1;
171 u32 gyro_fifo_enable:1;
172 u32 compass_enable:1;
173 u32 compass_fifo_enable:1;
177 u32 dmp_event_int_on:1;
178 u32 firmware_loaded:1;
182 u32 display_orient_on:1;
183 u32 normal_compass_measure:1;
193 * struct inv_chip_info_s - Chip related information.
194 * @product_id: Product id.
195 * @product_revision: Product revision.
196 * @silicon_revision: Silicon revision.
197 * @software_revision: software revision.
198 * @multi: accel specific multiplier.
199 * @compass_sens: compass sensitivity.
200 * @gyro_sens_trim: Gyro sensitivity trim factor.
201 * @accl_sens_trim: accel sensitivity trim factor.
203 struct inv_chip_info_s {
207 u8 software_revision;
214 enum inv_channel_num {
215 INV_CHANNEL_NUM_GYRO = 4,
216 INV_CHANNEL_NUM_GYRO_ACCL = 7,
217 INV_CHANNEL_NUM_GYRO_ACCL_QUANTERNION = 11,
218 INV_CHANNEL_NUM_GYRO_ACCL_QUANTERNION_MAGN = 14,
222 * struct inv_tap_s structure to store tap data.
223 * @min_count: minimum taps counted.
224 * @thresh: tap threshold.
234 * struct accel_mot_int_s structure to store motion interrupt data
235 * @mot_thr: motion threshold.
236 * @mot_dur: motion duration.
237 * @mot_on: flag to indicate motion detection on;
239 struct accel_mot_int_s {
246 * struct self_test_setting - self test settables from sysfs
247 * samples: number of samples used in self test.
248 * threshold: threshold fail/pass criterion in self test.
249 * This value is in the percentage multiplied by 100.
250 * So 14% would be 14.
252 struct self_test_setting {
258 * struct inv_smd_s significant motion detection structure.
259 * threshold: accel threshold for motion detection.
260 * delay: delay time to confirm 2nd motion.
261 * delay2: delay window parameter.
269 struct inv_mpu_slave;
271 * struct inv_mpu_iio_s - Driver state variables.
272 * @chip_config: Cached attribute information.
273 * @chip_info: Chip information from read-only registers.
274 * @trig; iio trigger.
275 * @tap: tap data structure.
276 * @smd: SMD data structure.
277 * @reg: Map of important registers.
278 * @self_test: self test settings.
279 * @hw: Other hardware-specific information.
280 * @chip_type: chip type.
281 * @time_stamp_lock: spin lock to time stamp.
282 * @client: i2c client handle.
283 * @plat_data: platform data.
284 * @mpu_slave: mpu slave handle.
285 * (*set_power_state)(struct inv_mpu_iio_s *, int on): function ptr
286 * (*switch_gyro_engine)(struct inv_mpu_iio_s *, int on): function ptr
287 * (*switch_accl_engine)(struct inv_mpu_iio_s *, int on): function ptr
288 * (*compass_en)(struct inv_mpu_iio_s *, struct iio_buffer *, bool);
289 * (*quaternion_en)(struct inv_mpu_iio_s *, struct iio_buffer *, bool)
290 * (*gyro_en)(struct inv_mpu_iio_s *, struct iio_buffer *, bool): func ptr.
291 * (*accl_en)(struct inv_mpu_iio_s *, struct iio_buffer *, bool): func ptr.
292 * (*init_config)(struct iio_dev *indio_dev): function ptr
293 * void (*setup_reg)(struct inv_reg_map_s *reg): function ptr
294 * @timestamps: kfifo queue to store time stamp.
295 * @compass_st_upper: compass self test upper limit.
296 * @compass_st_lower: compass self test lower limit.
297 * @irq: irq number store.
298 * @accel_bias: accel bias store.
299 * @gyro_bias: gyro bias store.
300 * @raw_gyro: raw gyro data.
301 * @raw_accel: raw accel data.
302 * @raw_compass: raw compass.
303 * @raw_quaternion raw quaternion data.
304 * @int input_accel_bias[3]: accel bias from sysfs.
305 * @compass_scale: compass scale.
306 * @i2c_addr: i2c address.
307 * @compass_divider: slow down compass rate.
308 * @compass_dmp_divider: slow down compass rate for dmp.
309 * @compass_counter: slow down compass rate.
310 * @sample_divider: sample divider for dmp.
311 * @fifo_divider: fifo divider for dmp.
312 * @display_orient_data:display orient data.
313 * @tap_data: tap data.
314 * @num_channels: number of channels for current chip.
315 * @sl_handle: Handle to I2C port.
316 * @irq_dur_ns: duration between each irq.
317 * @last_isr_time: last isr time.
318 * @mpu6500_last_motion_time: MPU6500 last real motion interrupt time.
319 * @name: name for distiguish MPU6050 and MPU6500 in MPU6XXX.
321 struct inv_mpu_iio_s {
322 #define TIMESTAMP_FIFO_SIZE 16
323 struct inv_chip_config_s chip_config;
324 struct inv_chip_info_s chip_info;
325 struct iio_trigger *trig;
326 struct inv_tap_s tap;
327 struct inv_smd_s smd;
328 struct inv_reg_map_s reg;
329 struct self_test_setting self_test;
330 const struct inv_hw_s *hw;
331 enum inv_devices chip_type;
332 spinlock_t time_stamp_lock;
333 struct i2c_client *client;
334 struct mpu_platform_data plat_data;
335 struct inv_mpu_slave *mpu_slave;
336 struct accel_mot_int_s mot_int;
337 int (*set_power_state)(struct inv_mpu_iio_s *, bool on);
338 int (*switch_gyro_engine)(struct inv_mpu_iio_s *, bool on);
339 int (*switch_accl_engine)(struct inv_mpu_iio_s *, bool on);
340 int (*compass_en)(struct inv_mpu_iio_s *,
341 struct iio_buffer *ring, bool on);
342 int (*quaternion_en)(struct inv_mpu_iio_s *,
343 struct iio_buffer *ring, bool on);
344 int (*gyro_en)(struct inv_mpu_iio_s *,
345 struct iio_buffer *ring, bool on);
346 int (*accl_en)(struct inv_mpu_iio_s *,
347 struct iio_buffer *ring, bool on);
348 int (*init_config)(struct iio_dev *indio_dev);
349 void (*setup_reg)(struct inv_reg_map_s *reg);
350 DECLARE_KFIFO(timestamps, u64, TIMESTAMP_FIFO_SIZE);
351 const short *compass_st_upper;
352 const short *compass_st_lower;
358 short raw_compass[3];
359 int raw_quaternion[4];
360 int input_accel_bias[3];
365 u8 compass_dmp_divider;
368 u8 display_orient_data;
370 enum inv_channel_num num_channels;
374 u64 mpu6500_last_motion_time;
376 u8 secondary_name[20];
379 /* produces an unique identifier for each device based on the
380 combination of product version and product revision */
381 struct prod_rev_map_t {
389 * struct inv_mpu_slave - MPU slave structure.
390 * @suspend: suspend operation.
391 * @resume: resume operation.
392 * @setup: setup chip. initialization.
393 * @combine_data: combine raw data into meaningful data.
394 * @get_mode: get current chip mode.
395 * @set_lpf set low pass filter.
396 * @set_fs set full scale
398 struct inv_mpu_slave {
399 int (*suspend)(struct inv_mpu_iio_s *);
400 int (*resume)(struct inv_mpu_iio_s *);
401 int (*setup)(struct inv_mpu_iio_s *);
402 int (*combine_data)(u8 *in, short *out);
403 int (*get_mode)(void);
404 int (*set_lpf)(struct inv_mpu_iio_s *, int rate);
405 int (*set_fs)(struct inv_mpu_iio_s *, int fs);
408 /* AKM definitions */
409 #define REG_AKM_ID 0x00
410 #define REG_AKM_STATUS 0x02
411 #define REG_AKM_MEASURE_DATA 0x03
412 #define REG_AKM_MODE 0x0A
413 #define REG_AKM_ST_CTRL 0x0C
414 #define REG_AKM_SENSITIVITY 0x10
415 #define REG_AKM8963_CNTL1 0x0A
417 #define DATA_AKM_ID 0x48
418 #define DATA_AKM_MODE_PD 0x00
419 #define DATA_AKM_MODE_SM 0x01
420 #define DATA_AKM_MODE_ST 0x08
421 #define DATA_AKM_MODE_FR 0x0F
422 #define DATA_AKM_SELF_TEST 0x40
423 #define DATA_AKM_DRDY 0x01
424 #define DATA_AKM8963_BIT 0x10
425 #define DATA_AKM_STAT_MASK 0x0C
427 #define DATA_AKM8975_SCALE (9830 * (1L << 15))
428 #define DATA_AKM8972_SCALE (19661 * (1L << 15))
429 #define DATA_AKM8963_SCALE0 (19661 * (1L << 15))
430 #define DATA_AKM8963_SCALE1 (4915 * (1L << 15))
431 #define AKM8963_SCALE_SHIFT 4
432 #define NUM_BYTES_COMPASS_SLAVE 8
434 /*register and associated bit definition*/
435 #define REG_3050_FIFO_EN 0x12
436 #define BITS_3050_ACCL_OUT 0x0E
438 #define REG_3050_AUX_VDDIO 0x13
439 #define BIT_3050_VDDIO 0x04
441 #define REG_3050_SLAVE_ADDR 0x14
442 #define REG_3050_SAMPLE_RATE_DIV 0x15
443 #define REG_3050_LPF 0x16
444 #define REG_3050_INT_ENABLE 0x17
445 #define REG_3050_AUX_BST_ADDR 0x18
446 #define REG_3050_INT_STATUS 0x1A
447 #define REG_3050_TEMPERATURE 0x1B
448 #define REG_3050_RAW_GYRO 0x1D
449 #define REG_3050_AUX_XOUT_H 0x23
450 #define REG_3050_FIFO_COUNT_H 0x3A
451 #define REG_3050_FIFO_R_W 0x3C
453 #define REG_3050_USER_CTRL 0x3D
454 #define BIT_3050_AUX_IF_EN 0x20
455 #define BIT_3050_AUX_IF_RST 0x08
456 #define BIT_3050_FIFO_RST 0x02
458 #define REG_3050_PWR_MGMT_1 0x3E
459 #define BITS_3050_POWER1 0x30
460 #define BITS_3050_POWER2 0x10
461 #define BITS_3050_GYRO_STANDBY 0x38
463 #define REG_3500_OTP 0x0
465 #define REG_YGOFFS_TC 0x1
466 #define BIT_I2C_MST_VDDIO 0x80
468 #define REG_XA_OFFS_L_TC 0x7
469 #define REG_PRODUCT_ID 0xC
470 #define REG_ST_GCT_X 0xD
471 #define REG_SAMPLE_RATE_DIV 0x19
472 #define REG_CONFIG 0x1A
474 #define REG_GYRO_CONFIG 0x1B
475 #define BITS_SELF_TEST_EN 0xE0
477 #define REG_ACCEL_CONFIG 0x1C
478 #define REG_ACCEL_MOT_THR 0x1F
479 #define REG_ACCEL_MOT_DUR 0x20
481 #define REG_FIFO_EN 0x23
482 #define BIT_ACCEL_OUT 0x08
483 #define BITS_GYRO_OUT 0x70
486 #define REG_I2C_MST_CTRL 0x24
487 #define BIT_WAIT_FOR_ES 0x40
489 #define REG_I2C_SLV0_ADDR 0x25
490 #define BIT_I2C_READ 0x80
492 #define REG_I2C_SLV0_REG 0x26
494 #define REG_I2C_SLV0_CTRL 0x27
495 #define BIT_SLV_EN 0x80
497 #define REG_I2C_SLV1_ADDR 0x28
498 #define REG_I2C_SLV1_REG 0x29
499 #define REG_I2C_SLV1_CTRL 0x2A
501 #define REG_I2C_SLV2_ADDR 0x2B
502 #define REG_I2C_SLV2_REG 0x2C
503 #define REG_I2C_SLV2_CTRL 0x2D
505 #define REG_I2C_SLV4_CTRL 0x34
507 #define REG_INT_PIN_CFG 0x37
508 #define BIT_BYPASS_EN 0x2
510 #define REG_INT_ENABLE 0x38
511 #define BIT_DATA_RDY_EN 0x01
512 #define BIT_DMP_INT_EN 0x02
513 #define BIT_ZMOT_EN 0x20
514 #define BIT_MOT_EN 0x40
515 #define BIT_6500_WOM_EN 0x40
517 #define REG_DMP_INT_STATUS 0x39
518 #define SMD_INT_ON 0x04
520 #define REG_INT_STATUS 0x3A
521 #define BIT_MOT_INT 0x40
522 #define BIT_ZMOT_INT 0x20
524 #define REG_RAW_ACCEL 0x3B
525 #define REG_TEMPERATURE 0x41
526 #define REG_RAW_GYRO 0x43
527 #define REG_EXT_SENS_DATA_00 0x49
529 #define REG_ACCEL_INTEL_STATUS 0x61
531 #define REG_I2C_SLV1_DO 0x64
533 #define REG_I2C_MST_DELAY_CTRL 0x67
534 #define BIT_SLV0_DLY_EN 0x01
535 #define BIT_SLV1_DLY_EN 0x02
536 #define BIT_SLV2_DLY_EN 0x04
538 #define REG_USER_CTRL 0x6A
539 #define BIT_FIFO_RST 0x04
540 #define BIT_DMP_RST 0x08
541 #define BIT_I2C_MST_EN 0x20
542 #define BIT_FIFO_EN 0x40
543 #define BIT_DMP_EN 0x80
545 #define REG_PWR_MGMT_1 0x6B
546 #define BIT_H_RESET 0x80
547 #define BIT_SLEEP 0x40
548 #define BIT_CYCLE 0x20
549 #define BIT_CLK_MASK 0x7
551 #define REG_PWR_MGMT_2 0x6C
552 #define BIT_PWR_ACCL_STBY 0x38
553 #define BIT_PWR_GYRO_STBY 0x07
554 #define BIT_LPA_FREQ 0xC0
556 #define REG_BANK_SEL 0x6D
557 #define REG_MEM_START_ADDR 0x6E
558 #define REG_MEM_RW 0x6F
559 #define REG_PRGM_STRT_ADDRH 0x70
560 #define REG_FIFO_COUNT_H 0x72
561 #define REG_FIFO_R_W 0x74
562 #define REG_WHOAMI 0x75
564 #define REG_6500_XG_ST_DATA 0x0
565 #define REG_6500_XA_ST_DATA 0xD
566 #define REG_6500_ACCEL_CONFIG2 0x1D
567 #define BIT_ACCEL_FCHOCIE_B 0x08
568 #define BIT_FIFO_SIZE_1K 0x40
571 #define REG_6500_LP_ACCEL_ODR 0x1E
572 #define REG_6500_ACCEL_WOM_THR 0x1F
574 #define REG_6500_ACCEL_INTEL_CTRL 0x69
575 #define BIT_ACCEL_INTEL_ENABLE 0x80
576 #define BIT_ACCEL_INTEL_MODE 0x40
578 /* data definitions */
579 #define DMP_START_ADDR 0x400
580 #define DMP_MASK_TAP 0x3f
581 #define DMP_MASK_DIS_ORIEN 0xC0
582 #define DMP_DIS_ORIEN_SHIFT 6
584 #define BYTES_FOR_DMP 16
585 #define BYTES_FOR_EVENTS 4
586 #define QUATERNION_BYTES 16
587 #define BYTES_PER_SENSOR 6
588 #define MPU3050_FOOTER_SIZE 2
589 #define FIFO_COUNT_BYTE 2
590 #define FIFO_THRESHOLD 500
591 #define POWER_UP_TIME 100
592 #define SENSOR_UP_TIME 30
593 #define REG_UP_TIME 5
594 #define INV_MPU_SAMPLE_RATE_CHANGE_STABLE 50
595 #define MPU_MEM_BANK_SIZE 256
597 #define MPU6XXX_MAX_MOTION_THRESH (255*4)
598 #define MPU6XXX_MOTION_THRESH_SHIFT 5
599 #define MPU6050_MOTION_DUR_DEFAULT 1
600 #define MPU6050_ID 0x68
601 #define MPU6050_MAX_MOTION_DUR 255
602 #define MPU_TEMP_SHIFT 16
603 #define LPA_FREQ_SHIFT 6
604 #define COMPASS_RATE_SCALE 10
605 #define MAX_GYRO_FS_PARAM 3
606 #define MAX_ACCL_FS_PARAM 3
607 #define MAX_LPA_FREQ_PARAM 3
608 #define MPU6XXX_MAX_MPU_MEM (256 * 12)
610 #define INIT_MOT_DUR 128
611 #define INIT_MOT_THR 128
612 #define INIT_ZMOT_DUR 128
613 #define INIT_ZMOT_THR 128
614 #define INIT_ST_SAMPLES 50
615 #define INIT_ST_THRESHOLD 14
616 #define ST_THRESHOLD_MULTIPLIER 10
617 #define ST_MAX_SAMPLES 500
618 #define ST_MAX_THRESHOLD 100
620 /*---- MPU6500 ----*/
621 #define MPU6500_ID 0x70 /* unique WHOAMI */
622 #define MPU6500_PRODUCT_REVISION 1
623 #define MPU6500_MEM_REV_ADDR 0x16
624 #define INV_MPU_REV_MASK 0xF
625 #define MPU6500_REV 2
627 /*---- MPU6515 ----*/
628 #define MPU6515_ID 0x74 /* unique WHOAMI */
630 /*---- MPU9250 ----*/
631 #define MPU9250_ID 0x71 /* unique WHOAMI */
634 #define GYRO_CONFIG_FSR_SHIFT 3
635 #define ACCL_CONFIG_FSR_SHIFT 3
636 #define GYRO_DPS_SCALE 250
637 #define MEM_ADDR_PROD_REV 0x6
638 #define SOFT_PROD_VER_BYTES 5
639 #define CRC_FIRMWARE_SEED 0
640 #define SELF_TEST_SUCCESS 1
641 #define MS_PER_DMP_TICK 20
643 /* init parameters */
644 #define INIT_FIFO_RATE 50
645 #define INIT_DMP_OUTPUT_RATE 25
646 #define INIT_DUR_TIME ((1000 / INIT_FIFO_RATE) * 1000 * 1000)
647 #define INIT_TAP_THRESHOLD 100
648 #define INIT_TAP_TIME 100
649 #define INIT_TAP_MIN_COUNT 2
650 #define MPU_INIT_SMD_DELAY_THLD 3
651 #define MPU_INIT_SMD_DELAY2_THLD 1
652 #define MPU_INIT_SMD_THLD 1500
653 #define MPU_DEFAULT_DMP_FREQ 200
654 #define MPL_PROD_KEY(ver, rev) (ver * 100 + rev)
655 #define NUM_OF_PROD_REVS (ARRAY_SIZE(prod_rev_map))
656 /*---- MPU6050 Silicon Revisions ----*/
657 #define MPU_SILICON_REV_A2 1 /* MPU6050A2 Device */
658 #define MPU_SILICON_REV_B1 2 /* MPU6050B1 Device */
660 #define BIT_PRFTCH_EN 0x40
661 #define BIT_CFG_USER_BANK 0x20
662 #define BITS_MEM_SEL 0x1f
664 #define TIME_STAMP_TOR 5
665 #define MAX_CATCH_UP 5
666 #define DEFAULT_ACCL_TRIM 16384
667 #define DEFAULT_GYRO_TRIM 131
668 #define MAX_FIFO_RATE 1000
669 #define MAX_DMP_OUTPUT_RATE 200
670 #define MIN_FIFO_RATE 4
671 #define ONE_K_HZ 1000
672 #define NS_PER_MS_SHIFT 20
674 /*tap related defines */
676 #define INV_NUM_TAP_AXES 3
678 #define INV_TAP_AXIS_X_POS 0x20
679 #define INV_TAP_AXIS_X_NEG 0x10
680 #define INV_TAP_AXIS_Y_POS 0x08
681 #define INV_TAP_AXIS_Y_NEG 0x04
682 #define INV_TAP_AXIS_Z_POS 0x02
683 #define INV_TAP_AXIS_Z_NEG 0x01
684 #define INV_TAP_ALL_DIRECTIONS 0x3f
686 #define INV_TAP_AXIS_X 0x1
687 #define INV_TAP_AXIS_Y 0x2
688 #define INV_TAP_AXIS_Z 0x4
690 #define INV_TAP_AXIS_ALL \
695 #define INT_SRC_TAP 0x01
696 #define INT_SRC_DISPLAY_ORIENT 0x08
697 #define INT_SRC_SHAKE 0x10
699 #define INV_X_AXIS_INDEX 0x00
700 #define INV_Y_AXIS_INDEX 0x01
701 #define INV_Z_AXIS_INDEX 0x02
703 #define INV_ELEMENT_1 0x0001
704 #define INV_ELEMENT_2 0x0002
705 #define INV_ELEMENT_3 0x0004
706 #define INV_ELEMENT_4 0x0008
707 #define INV_ELEMENT_5 0x0010
708 #define INV_ELEMENT_6 0x0020
709 #define INV_ELEMENT_7 0x0040
710 #define INV_ELEMENT_8 0x0080
711 #define INV_ALL 0xFFFF
712 #define INV_ELEMENT_MASK 0x00FF
713 #define INV_GYRO_ACC_MASK 0x007E
714 #define INV_ACCL_MASK 0x70
715 #define INV_GYRO_MASK 0xE
716 /* scan element definition */
718 INV_MPU_SCAN_QUAT_R = 0,
731 INV_MPU_SCAN_TIMESTAMP,
735 INV_FILTER_256HZ_NOLPF2 = 0,
742 INV_FILTER_2100HZ_NOLPF,
746 enum inv_slave_mode {
751 /*==== MPU6050B1 MEMORY ====*/
752 enum MPU_MEMORY_BANKS {
765 MPU_MEM_NUM_RAM_BANKS,
766 MPU_MEM_OTP_BANK_0 = 16
769 /* IIO attribute address */
770 enum MPU_IIO_ATTR_ADDR {
773 ATTR_DMP_SMD_DELAY_THLD,
774 ATTR_DMP_SMD_DELAY_THLD2,
776 ATTR_DMP_TAP_THRESHOLD,
777 ATTR_DMP_TAP_MIN_COUNT,
779 ATTR_DMP_DISPLAY_ORIENTATION_ON,
780 /* *****above this line, are DMP features, power needs on/off */
781 /* *****below this line, are DMP features, no power needed */
784 ATTR_DMP_EVENT_INT_ON,
785 ATTR_DMP_OUTPUT_RATE,
786 ATTR_DMP_QUATERNION_ON,
787 /* *****above this line, it is all DMP related features */
788 /* *****below this line, it is all non-DMP related features */
790 ATTR_MOTION_LPA_FREQ,
791 ATTR_MOTION_LPA_THRESHOLD,
792 /* *****above this line, it is non-DMP, power needs on/off */
793 /* *****below this line, it is non-DMP, no needs to on/off power */
794 ATTR_SELF_TEST_SAMPLES,
795 ATTR_SELF_TEST_THRESHOLD,
799 ATTR_POWER_STATE, /* this is fake sysfs for compatibility */
800 ATTR_FIRMWARE_LOADED,
802 /* *****below this line, it is attributes only has show methods */
803 ATTR_SELF_TEST, /* this has show-only methods but needs power on/off */
808 #ifdef CONFIG_INV_TESTING
811 ATTR_DEBUG_SMD_ENABLE_TESTP1,
812 ATTR_DEBUG_SMD_ENABLE_TESTP2,
813 ATTR_DEBUG_SMD_EXE_STATE,
814 ATTR_DEBUG_SMD_DELAY_CNTR
834 enum inv_clock_sel_e {
835 INV_CLK_INTERNAL = 0,
840 ssize_t inv_dmp_firmware_write(struct file *fp, struct kobject *kobj,
841 struct bin_attribute *attr, char *buf, loff_t pos, size_t size);
842 ssize_t inv_dmp_firmware_read(struct file *filp,
843 struct kobject *kobj,
844 struct bin_attribute *bin_attr,
845 char *buf, loff_t off, size_t count);
847 int inv_mpu_configure_ring(struct iio_dev *indio_dev);
848 int inv_mpu_probe_trigger(struct iio_dev *indio_dev);
849 void inv_mpu_unconfigure_ring(struct iio_dev *indio_dev);
850 void inv_mpu_remove_trigger(struct iio_dev *indio_dev);
851 int inv_init_config_mpu3050(struct iio_dev *indio_dev);
852 int inv_get_silicon_rev_mpu6050(struct inv_mpu_iio_s *st);
853 int inv_get_silicon_rev_mpu6500(struct inv_mpu_iio_s *st);
854 int set_3050_bypass(struct inv_mpu_iio_s *st, bool enable);
855 int inv_register_mpu3050_slave(struct inv_mpu_iio_s *st);
856 void inv_setup_reg_mpu3050(struct inv_reg_map_s *reg);
857 int inv_switch_3050_gyro_engine(struct inv_mpu_iio_s *st, bool en);
858 int inv_switch_3050_accl_engine(struct inv_mpu_iio_s *st, bool en);
859 int set_power_mpu3050(struct inv_mpu_iio_s *st, bool power_on);
860 int inv_set_interrupt_on_gesture_event(struct inv_mpu_iio_s *st, bool on);
861 int inv_send_quaternion(struct inv_mpu_iio_s *st, bool on);
862 int inv_set_display_orient_interrupt_dmp(struct inv_mpu_iio_s *st, bool on);
863 int inv_set_fifo_rate(struct inv_mpu_iio_s *st, u16 fifo_rate);
864 u16 inv_dmp_get_address(u16 key);
865 int inv_q30_mult(int a, int b);
866 int inv_set_tap_threshold_dmp(struct inv_mpu_iio_s *st,
867 u32 axis, u16 threshold);
868 int inv_set_min_taps_dmp(struct inv_mpu_iio_s *st, u16 min_taps);
869 int inv_set_tap_time_dmp(struct inv_mpu_iio_s *st, u16 time);
870 int inv_enable_tap_dmp(struct inv_mpu_iio_s *st, bool on);
871 int inv_i2c_read_base(struct inv_mpu_iio_s *st, u16 i2c_addr,
872 u8 reg, u16 length, u8 *data);
873 int inv_i2c_single_write_base(struct inv_mpu_iio_s *st,
874 u16 i2c_addr, u8 reg, u8 data);
875 int inv_do_test(struct inv_mpu_iio_s *st, int self_test_flag,
876 int *gyro_result, int *accl_result);
877 int inv_hw_self_test(struct inv_mpu_iio_s *st);
878 void inv_recover_setting(struct inv_mpu_iio_s *st);
879 int inv_power_up_self_test(struct inv_mpu_iio_s *st);
880 s64 get_time_ns(void);
881 int write_be32_key_to_mem(struct inv_mpu_iio_s *st,
883 int inv_set_accel_bias_dmp(struct inv_mpu_iio_s *st);
884 int inv_send_sensor_data(struct inv_mpu_iio_s *st, u16 elements);
885 int inv_send_interrupt_word(struct inv_mpu_iio_s *st, bool on);
886 int mpu_memory_write(struct inv_mpu_iio_s *st, u8 mpu_addr, u16 mem_addr,
887 u32 len, u8 const *data);
888 int mpu_memory_read(struct inv_mpu_iio_s *st, u8 mpu_addr, u16 mem_addr,
890 int mpu_memory_write_unaligned(struct inv_mpu_iio_s *st, u16 key, int len,
892 /* used to print i2c data using pr_debug */
893 char *wr_pr_debug_begin(u8 const *data, u32 len, char *string);
894 char *wr_pr_debug_end(char *string);
896 #define mem_w(a, b, c) \
897 mpu_memory_write(st, st->i2c_addr, a, b, c)
898 #define mem_w_key(key, b, c) mpu_memory_write_unaligned(st, key, b, c)
899 #define inv_i2c_read(st, reg, len, data) \
900 inv_i2c_read_base(st, st->i2c_addr, reg, len, data)
901 #define inv_i2c_single_write(st, reg, data) \
902 inv_i2c_single_write_base(st, st->i2c_addr, reg, data)
903 #define inv_secondary_read(reg, len, data) \
904 inv_i2c_read_base(st, st->plat_data.secondary_i2c_addr, reg, len, data)
905 #define inv_secondary_write(reg, data) \
906 inv_i2c_single_write_base(st, st->plat_data.secondary_i2c_addr, \
909 #endif /* #ifndef _INV_MPU_IIO_H_ */