drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/err.h>
  14 #include <linux/pm_clock.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/clk.h>
  19 #include <linux/regmap.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <dt-bindings/power/rk3288-power.h>
  22 #include <dt-bindings/power/rk3328-power.h>
  23 #include <dt-bindings/power/rk3366-power.h>
  24 #include <dt-bindings/power/rk3368-power.h>
  25 #include <dt-bindings/power/rk3399-power.h>
  26
  27 struct rockchip_domain_info {
  28         int pwr_mask;
  29         int status_mask;
  30         int req_mask;
  31         int idle_mask;
  32         int ack_mask;
  33         bool active_wakeup;
  34         int pwr_w_mask;
  35         int req_w_mask;
  36 };
  37
  38 struct rockchip_pmu_info {
  39         u32 pwr_offset;
  40         u32 status_offset;
  41         u32 req_offset;
  42         u32 idle_offset;
  43         u32 ack_offset;
  44
  45         u32 core_pwrcnt_offset;
  46         u32 gpu_pwrcnt_offset;
  47
  48         unsigned int core_power_transition_time;
  49         unsigned int gpu_power_transition_time;
  50
  51         int num_domains;
  52         const struct rockchip_domain_info *domain_info;
  53 };
  54
  55 #define MAX_QOS_REGS_NUM        5
  56 #define QOS_PRIORITY            0x08
  57 #define QOS_MODE                0x0c
  58 #define QOS_BANDWIDTH           0x10
  59 #define QOS_SATURATION          0x14
  60 #define QOS_EXTCONTROL          0x18
  61
  62 struct rockchip_pm_domain {
  63         struct generic_pm_domain genpd;
  64         const struct rockchip_domain_info *info;
  65         struct rockchip_pmu *pmu;
  66         int num_qos;
  67         struct regmap **qos_regmap;
  68         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  69         int num_clks;
  70         struct clk *clks[];
  71 };
  72
  73 struct rockchip_pmu {
  74         struct device *dev;
  75         struct regmap *regmap;
  76         const struct rockchip_pmu_info *info;
  77         struct mutex mutex; /* mutex lock for pmu */
  78         struct genpd_onecell_data genpd_data;
  79         struct generic_pm_domain *domains[];
  80 };
  81
  82 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  83
  84 #define DOMAIN(pwr, status, req, idle, ack, wakeup)     \
  85 {                                               \
  86         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  87         .status_mask = (status >= 0) ? BIT(status) : 0, \
  88         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  89         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  90         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  91         .active_wakeup = wakeup,                        \
  92 }
  93
  94 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup)   \
  95 {                                                       \
  96         .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0,   \
  97         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  98         .status_mask = (status >= 0) ? BIT(status) : 0, \
  99         .req_w_mask = (req >= 0) ?  BIT(req + 16) : 0,  \
 100         .req_mask = (req >= 0) ?  BIT(req) : 0,         \
 101         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
 102         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
 103         .active_wakeup = wakeup,                        \
 104 }
 105
 106 #define DOMAIN_RK3288(pwr, status, req, wakeup)         \
 107         DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
 108
 109 #define DOMAIN_RK3328(pwr, status, req, wakeup)         \
 110         DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
 111
 112 #define DOMAIN_RK3368(pwr, status, req, wakeup)         \
 113         DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
 114
 115 #define DOMAIN_RK3399(pwr, status, req, wakeup)         \
 116         DOMAIN(pwr, status, req, req, req, wakeup)
 117
 118 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 119 {
 120         struct rockchip_pmu *pmu = pd->pmu;
 121         const struct rockchip_domain_info *pd_info = pd->info;
 122         unsigned int val;
 123
 124         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 125         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 126 }
 127
 128 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
 129 {
 130         unsigned int val;
 131
 132         regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 133         return val;
 134 }
 135
 136 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 137                                          bool idle)
 138 {
 139         const struct rockchip_domain_info *pd_info = pd->info;
 140         struct generic_pm_domain *genpd = &pd->genpd;
 141         struct rockchip_pmu *pmu = pd->pmu;
 142         unsigned int target_ack;
 143         unsigned int val;
 144         bool is_idle;
 145         int ret;
 146
 147         if (pd_info->req_mask == 0)
 148                 return 0;
 149         else if (pd_info->req_w_mask)
 150                 regmap_write(pmu->regmap, pmu->info->req_offset,
 151                              idle ? (pd_info->req_mask | pd_info->req_w_mask) :
 152                              pd_info->req_w_mask);
 153         else
 154                 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 155                                    pd_info->req_mask, idle ? -1U : 0);
 156
 157         dsb(sy);
 158
 159         /* Wait util idle_ack = 1 */
 160         target_ack = idle ? pd_info->ack_mask : 0;
 161         ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
 162                                         (val & pd_info->ack_mask) == target_ack,
 163                                         0, 10000);
 164         if (ret) {
 165                 dev_err(pmu->dev,
 166                         "failed to get ack on domain '%s', val=0x%x\n",
 167                         genpd->name, val);
 168                 return ret;
 169         }
 170
 171         ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
 172                                         is_idle, is_idle == idle, 0, 10000);
 173         if (ret) {
 174                 dev_err(pmu->dev,
 175                         "failed to set idle on domain '%s', val=%d\n",
 176                         genpd->name, is_idle);
 177                 return ret;
 178         }
 179
 180         return 0;
 181 }
 182
 183 int rockchip_pmu_idle_request(struct device *dev, bool idle)
 184 {
 185         struct generic_pm_domain *genpd;
 186         struct rockchip_pm_domain *pd;
 187         int ret;
 188
 189         if (IS_ERR_OR_NULL(dev))
 190                 return -EINVAL;
 191
 192         if (IS_ERR_OR_NULL(dev->pm_domain))
 193                 return -EINVAL;
 194
 195         genpd = pd_to_genpd(dev->pm_domain);
 196         pd = to_rockchip_pd(genpd);
 197
 198         mutex_lock(&pd->pmu->mutex);
 199         ret = rockchip_pmu_set_idle_request(pd, idle);
 200         mutex_unlock(&pd->pmu->mutex);
 201
 202         return ret;
 203 }
 204 EXPORT_SYMBOL(rockchip_pmu_idle_request);
 205
 206 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 207 {
 208         int i;
 209
 210         for (i = 0; i < pd->num_qos; i++) {
 211                 regmap_read(pd->qos_regmap[i],
 212                             QOS_PRIORITY,
 213                             &pd->qos_save_regs[0][i]);
 214                 regmap_read(pd->qos_regmap[i],
 215                             QOS_MODE,
 216                             &pd->qos_save_regs[1][i]);
 217                 regmap_read(pd->qos_regmap[i],
 218                             QOS_BANDWIDTH,
 219                             &pd->qos_save_regs[2][i]);
 220                 regmap_read(pd->qos_regmap[i],
 221                             QOS_SATURATION,
 222                             &pd->qos_save_regs[3][i]);
 223                 regmap_read(pd->qos_regmap[i],
 224                             QOS_EXTCONTROL,
 225                             &pd->qos_save_regs[4][i]);
 226         }
 227         return 0;
 228 }
 229
 230 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 231 {
 232         int i;
 233
 234         for (i = 0; i < pd->num_qos; i++) {
 235                 regmap_write(pd->qos_regmap[i],
 236                              QOS_PRIORITY,
 237                              pd->qos_save_regs[0][i]);
 238                 regmap_write(pd->qos_regmap[i],
 239                              QOS_MODE,
 240                              pd->qos_save_regs[1][i]);
 241                 regmap_write(pd->qos_regmap[i],
 242                              QOS_BANDWIDTH,
 243                              pd->qos_save_regs[2][i]);
 244                 regmap_write(pd->qos_regmap[i],
 245                              QOS_SATURATION,
 246                              pd->qos_save_regs[3][i]);
 247                 regmap_write(pd->qos_regmap[i],
 248                              QOS_EXTCONTROL,
 249                              pd->qos_save_regs[4][i]);
 250         }
 251
 252         return 0;
 253 }
 254
 255 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 256 {
 257         struct rockchip_pmu *pmu = pd->pmu;
 258         unsigned int val;
 259
 260         /* check idle status for idle-only domains */
 261         if (pd->info->status_mask == 0)
 262                 return !rockchip_pmu_domain_is_idle(pd);
 263
 264         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 265
 266         /* 1'b0: power on, 1'b1: power off */
 267         return !(val & pd->info->status_mask);
 268 }
 269
 270 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 271                                              bool on)
 272 {
 273         struct rockchip_pmu *pmu = pd->pmu;
 274         struct generic_pm_domain *genpd = &pd->genpd;
 275         bool is_on;
 276
 277         if (pd->info->pwr_mask == 0)
 278                 return;
 279         else if (pd->info->pwr_w_mask)
 280                 regmap_write(pmu->regmap, pmu->info->pwr_offset,
 281                              on ? pd->info->pwr_mask :
 282                              (pd->info->pwr_mask | pd->info->pwr_w_mask));
 283         else
 284                 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 285                                    pd->info->pwr_mask, on ? 0 : -1U);
 286
 287         dsb(sy);
 288
 289         if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
 290                                       is_on == on, 0, 10000)) {
 291                 dev_err(pmu->dev,
 292                         "failed to set domain '%s', val=%d\n",
 293                         genpd->name, is_on);
 294                 return;
 295         }
 296 }
 297
 298 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 299 {
 300         int i;
 301
 302         mutex_lock(&pd->pmu->mutex);
 303
 304         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 305                 for (i = 0; i < pd->num_clks; i++)
 306                         clk_enable(pd->clks[i]);
 307
 308                 if (!power_on) {
 309                         rockchip_pmu_save_qos(pd);
 310
 311                         /* if powering down, idle request to NIU first */
 312                         rockchip_pmu_set_idle_request(pd, true);
 313                 }
 314
 315                 rockchip_do_pmu_set_power_domain(pd, power_on);
 316
 317                 if (power_on) {
 318                         /* if powering up, leave idle mode */
 319                         rockchip_pmu_set_idle_request(pd, false);
 320
 321                         rockchip_pmu_restore_qos(pd);
 322                 }
 323
 324                 for (i = pd->num_clks - 1; i >= 0; i--)
 325                         clk_disable(pd->clks[i]);
 326         }
 327
 328         mutex_unlock(&pd->pmu->mutex);
 329         return 0;
 330 }
 331
 332 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 333 {
 334         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 335
 336         return rockchip_pd_power(pd, true);
 337 }
 338
 339 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 340 {
 341         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 342
 343         return rockchip_pd_power(pd, false);
 344 }
 345
 346 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 347                                   struct device *dev)
 348 {
 349         struct clk *clk;
 350         int i;
 351         int error;
 352
 353         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 354
 355         error = pm_clk_create(dev);
 356         if (error) {
 357                 dev_err(dev, "pm_clk_create failed %d\n", error);
 358                 return error;
 359         }
 360
 361         i = 0;
 362         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 363                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 364                 error = pm_clk_add_clk(dev, clk);
 365                 if (error) {
 366                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 367                         clk_put(clk);
 368                         pm_clk_destroy(dev);
 369                         return error;
 370                 }
 371         }
 372
 373         return 0;
 374 }
 375
 376 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 377                                    struct device *dev)
 378 {
 379         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 380
 381         pm_clk_destroy(dev);
 382 }
 383
 384 static bool rockchip_active_wakeup(struct device *dev)
 385 {
 386         struct generic_pm_domain *genpd;
 387         struct rockchip_pm_domain *pd;
 388
 389         genpd = pd_to_genpd(dev->pm_domain);
 390         pd = container_of(genpd, struct rockchip_pm_domain, genpd);
 391
 392         return pd->info->active_wakeup;
 393 }
 394
 395 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 396                                       struct device_node *node)
 397 {
 398         const struct rockchip_domain_info *pd_info;
 399         struct rockchip_pm_domain *pd;
 400         struct device_node *qos_node;
 401         struct clk *clk;
 402         int clk_cnt;
 403         int i, j;
 404         u32 id;
 405         int error;
 406
 407         error = of_property_read_u32(node, "reg", &id);
 408         if (error) {
 409                 dev_err(pmu->dev,
 410                         "%s: failed to retrieve domain id (reg): %d\n",
 411                         node->name, error);
 412                 return -EINVAL;
 413         }
 414
 415         if (id >= pmu->info->num_domains) {
 416                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 417                         node->name, id);
 418                 return -EINVAL;
 419         }
 420
 421         pd_info = &pmu->info->domain_info[id];
 422         if (!pd_info) {
 423                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 424                         node->name, id);
 425                 return -EINVAL;
 426         }
 427
 428         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 429         pd = devm_kzalloc(pmu->dev,
 430                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 431                           GFP_KERNEL);
 432         if (!pd)
 433                 return -ENOMEM;
 434
 435         pd->info = pd_info;
 436         pd->pmu = pmu;
 437
 438         for (i = 0; i < clk_cnt; i++) {
 439                 clk = of_clk_get(node, i);
 440                 if (IS_ERR(clk)) {
 441                         error = PTR_ERR(clk);
 442                         dev_err(pmu->dev,
 443                                 "%s: failed to get clk at index %d: %d\n",
 444                                 node->name, i, error);
 445                         goto err_out;
 446                 }
 447
 448                 error = clk_prepare(clk);
 449                 if (error) {
 450                         dev_err(pmu->dev,
 451                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 452                                 node->name, clk, i, error);
 453                         clk_put(clk);
 454                         goto err_out;
 455                 }
 456
 457                 pd->clks[pd->num_clks++] = clk;
 458
 459                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 460                         clk, node->name);
 461         }
 462
 463         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 464                                                  NULL);
 465
 466         if (pd->num_qos > 0) {
 467                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 468                                               sizeof(*pd->qos_regmap),
 469                                               GFP_KERNEL);
 470                 if (!pd->qos_regmap) {
 471                         error = -ENOMEM;
 472                         goto err_out;
 473                 }
 474
 475                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 476                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 477                                                             pd->num_qos,
 478                                                             sizeof(u32),
 479                                                             GFP_KERNEL);
 480                         if (!pd->qos_save_regs[j]) {
 481                                 error = -ENOMEM;
 482                                 goto err_out;
 483                         }
 484                 }
 485
 486                 for (j = 0; j < pd->num_qos; j++) {
 487                         qos_node = of_parse_phandle(node, "pm_qos", j);
 488                         if (!qos_node) {
 489                                 error = -ENODEV;
 490                                 goto err_out;
 491                         }
 492                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 493                         if (IS_ERR(pd->qos_regmap[j])) {
 494                                 error = -ENODEV;
 495                                 of_node_put(qos_node);
 496                                 goto err_out;
 497                         }
 498                         of_node_put(qos_node);
 499                 }
 500         }
 501
 502         error = rockchip_pd_power(pd, true);
 503         if (error) {
 504                 dev_err(pmu->dev,
 505                         "failed to power on domain '%s': %d\n",
 506                         node->name, error);
 507                 goto err_out;
 508         }
 509
 510         pd->genpd.name = node->name;
 511         pd->genpd.power_off = rockchip_pd_power_off;
 512         pd->genpd.power_on = rockchip_pd_power_on;
 513         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 514         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 515         pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
 516         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 517         pm_genpd_init(&pd->genpd, NULL, false);
 518
 519         pmu->genpd_data.domains[id] = &pd->genpd;
 520         return 0;
 521
 522 err_out:
 523         while (--i >= 0) {
 524                 clk_unprepare(pd->clks[i]);
 525                 clk_put(pd->clks[i]);
 526         }
 527         return error;
 528 }
 529
 530 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 531 {
 532         int i;
 533
 534         for (i = 0; i < pd->num_clks; i++) {
 535                 clk_unprepare(pd->clks[i]);
 536                 clk_put(pd->clks[i]);
 537         }
 538
 539         /* protect the zeroing of pm->num_clks */
 540         mutex_lock(&pd->pmu->mutex);
 541         pd->num_clks = 0;
 542         mutex_unlock(&pd->pmu->mutex);
 543
 544         /* devm will free our memory */
 545 }
 546
 547 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 548 {
 549         struct generic_pm_domain *genpd;
 550         struct rockchip_pm_domain *pd;
 551         int i;
 552
 553         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 554                 genpd = pmu->genpd_data.domains[i];
 555                 if (genpd) {
 556                         pd = to_rockchip_pd(genpd);
 557                         rockchip_pm_remove_one_domain(pd);
 558                 }
 559         }
 560
 561         /* devm will free our memory */
 562 }
 563
 564 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 565                                       u32 domain_reg_offset,
 566                                       unsigned int count)
 567 {
 568         /* First configure domain power down transition count ... */
 569         regmap_write(pmu->regmap, domain_reg_offset, count);
 570         /* ... and then power up count. */
 571         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 572 }
 573
 574 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 575                                      struct device_node *parent)
 576 {
 577         struct device_node *np;
 578         struct generic_pm_domain *child_domain, *parent_domain;
 579         int error;
 580
 581         for_each_child_of_node(parent, np) {
 582                 u32 idx;
 583
 584                 error = of_property_read_u32(parent, "reg", &idx);
 585                 if (error) {
 586                         dev_err(pmu->dev,
 587                                 "%s: failed to retrieve domain id (reg): %d\n",
 588                                 parent->name, error);
 589                         goto err_out;
 590                 }
 591                 parent_domain = pmu->genpd_data.domains[idx];
 592
 593                 error = rockchip_pm_add_one_domain(pmu, np);
 594                 if (error) {
 595                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 596                                 np->name, error);
 597                         goto err_out;
 598                 }
 599
 600                 error = of_property_read_u32(np, "reg", &idx);
 601                 if (error) {
 602                         dev_err(pmu->dev,
 603                                 "%s: failed to retrieve domain id (reg): %d\n",
 604                                 np->name, error);
 605                         goto err_out;
 606                 }
 607                 child_domain = pmu->genpd_data.domains[idx];
 608
 609                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 610                 if (error) {
 611                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 612                                 parent_domain->name, child_domain->name, error);
 613                         goto err_out;
 614                 } else {
 615                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 616                                 parent_domain->name, child_domain->name);
 617                 }
 618
 619                 rockchip_pm_add_subdomain(pmu, np);
 620         }
 621
 622         return 0;
 623
 624 err_out:
 625         of_node_put(np);
 626         return error;
 627 }
 628
 629 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 630 {
 631         struct device *dev = &pdev->dev;
 632         struct device_node *np = dev->of_node;
 633         struct device_node *node;
 634         struct device *parent;
 635         struct rockchip_pmu *pmu;
 636         const struct of_device_id *match;
 637         const struct rockchip_pmu_info *pmu_info;
 638         int error;
 639
 640         if (!np) {
 641                 dev_err(dev, "device tree node not found\n");
 642                 return -ENODEV;
 643         }
 644
 645         match = of_match_device(dev->driver->of_match_table, dev);
 646         if (!match || !match->data) {
 647                 dev_err(dev, "missing pmu data\n");
 648                 return -EINVAL;
 649         }
 650
 651         pmu_info = match->data;
 652
 653         pmu = devm_kzalloc(dev,
 654                            sizeof(*pmu) +
 655                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 656                            GFP_KERNEL);
 657         if (!pmu)
 658                 return -ENOMEM;
 659
 660         pmu->dev = &pdev->dev;
 661         mutex_init(&pmu->mutex);
 662
 663         pmu->info = pmu_info;
 664
 665         pmu->genpd_data.domains = pmu->domains;
 666         pmu->genpd_data.num_domains = pmu_info->num_domains;
 667
 668         parent = dev->parent;
 669         if (!parent) {
 670                 dev_err(dev, "no parent for syscon devices\n");
 671                 return -ENODEV;
 672         }
 673
 674         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 675         if (IS_ERR(pmu->regmap)) {
 676                 dev_err(dev, "no regmap available\n");
 677                 return PTR_ERR(pmu->regmap);
 678         }
 679
 680         /*
 681          * Configure power up and down transition delays for CORE
 682          * and GPU domains.
 683          */
 684         if (pmu_info->core_pwrcnt_offset)
 685                 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 686                                           pmu_info->core_power_transition_time);
 687         if (pmu_info->gpu_pwrcnt_offset)
 688                 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 689                                           pmu_info->gpu_power_transition_time);
 690
 691         error = -ENODEV;
 692
 693         for_each_available_child_of_node(np, node) {
 694                 error = rockchip_pm_add_one_domain(pmu, node);
 695                 if (error) {
 696                         dev_err(dev, "failed to handle node %s: %d\n",
 697                                 node->name, error);
 698                         of_node_put(node);
 699                         goto err_out;
 700                 }
 701
 702                 error = rockchip_pm_add_subdomain(pmu, node);
 703                 if (error < 0) {
 704                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 705                                 node->name, error);
 706                         of_node_put(node);
 707                         goto err_out;
 708                 }
 709         }
 710
 711         if (error) {
 712                 dev_dbg(dev, "no power domains defined\n");
 713                 goto err_out;
 714         }
 715
 716         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 717
 718         return 0;
 719
 720 err_out:
 721         rockchip_pm_domain_cleanup(pmu);
 722         return error;
 723 }
 724
 725 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 726         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4, false),
 727         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9, false),
 728         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3, false),
 729         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2, false),
 730 };
 731
 732 static const struct rockchip_domain_info rk3328_pm_domains[] = {
 733         [RK3328_PD_CORE]        = DOMAIN_RK3328(-1, 0, 0, false),
 734         [RK3328_PD_GPU]         = DOMAIN_RK3328(-1, 1, 1, false),
 735         [RK3328_PD_BUS]         = DOMAIN_RK3328(-1, 2, 2, true),
 736         [RK3328_PD_MSCH]        = DOMAIN_RK3328(-1, 3, 3, true),
 737         [RK3328_PD_PERI]        = DOMAIN_RK3328(-1, 4, 4, true),
 738         [RK3328_PD_VIDEO]       = DOMAIN_RK3328(-1, 5, 5, false),
 739         [RK3328_PD_HEVC]        = DOMAIN_RK3328(-1, 6, 6, false),
 740         [RK3328_PD_VIO]         = DOMAIN_RK3328(-1, 8, 8, false),
 741         [RK3328_PD_VPU]         = DOMAIN_RK3328(-1, 9, 9, false),
 742 };
 743
 744 static const struct rockchip_domain_info rk3366_pm_domains[] = {
 745         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6, true),
 746         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8, false),
 747         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7, false),
 748         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7, false),
 749         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9, false),
 750         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7, false),
 751         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2, false),
 752 };
 753
 754 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 755         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6, true),
 756         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8, false),
 757         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7, false),
 758         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2, false),
 759         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2, false),
 760 };
 761
 762 static const struct rockchip_domain_info rk3399_pm_domains[] = {
 763         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1, false),
 764         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1, false),
 765         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1, true),
 766         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15, true),
 767         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16, true),
 768         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1, true),
 769         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2, true),
 770         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14, true),
 771         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17, false),
 772         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0, false),
 773         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3, false),
 774         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4, false),
 775         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5, false),
 776         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6, false),
 777         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1, false),
 778         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7, false),
 779         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8, false),
 780         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9, false),
 781         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10, false),
 782         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11, false),
 783         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23, true),
 784         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24, true),
 785         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12, true),
 786         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22, false),
 787         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27, true),
 788         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28, true),
 789         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29, true),
 790 };
 791
 792 static const struct rockchip_pmu_info rk3288_pmu = {
 793         .pwr_offset = 0x08,
 794         .status_offset = 0x0c,
 795         .req_offset = 0x10,
 796         .idle_offset = 0x14,
 797         .ack_offset = 0x14,
 798
 799         .core_pwrcnt_offset = 0x34,
 800         .gpu_pwrcnt_offset = 0x3c,
 801
 802         .core_power_transition_time = 24, /* 1us */
 803         .gpu_power_transition_time = 24, /* 1us */
 804
 805         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 806         .domain_info = rk3288_pm_domains,
 807 };
 808
 809 static const struct rockchip_pmu_info rk3328_pmu = {
 810         .req_offset = 0x414,
 811         .idle_offset = 0x484,
 812         .ack_offset = 0x484,
 813
 814         .num_domains = ARRAY_SIZE(rk3328_pm_domains),
 815         .domain_info = rk3328_pm_domains,
 816 };
 817
 818 static const struct rockchip_pmu_info rk3366_pmu = {
 819         .pwr_offset = 0x0c,
 820         .status_offset = 0x10,
 821         .req_offset = 0x3c,
 822         .idle_offset = 0x40,
 823         .ack_offset = 0x40,
 824
 825         .core_pwrcnt_offset = 0x48,
 826         .gpu_pwrcnt_offset = 0x50,
 827
 828         .core_power_transition_time = 24,
 829         .gpu_power_transition_time = 24,
 830
 831         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
 832         .domain_info = rk3366_pm_domains,
 833 };
 834
 835 static const struct rockchip_pmu_info rk3368_pmu = {
 836         .pwr_offset = 0x0c,
 837         .status_offset = 0x10,
 838         .req_offset = 0x3c,
 839         .idle_offset = 0x40,
 840         .ack_offset = 0x40,
 841
 842         .core_pwrcnt_offset = 0x48,
 843         .gpu_pwrcnt_offset = 0x50,
 844
 845         .core_power_transition_time = 24,
 846         .gpu_power_transition_time = 24,
 847
 848         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 849         .domain_info = rk3368_pm_domains,
 850 };
 851
 852 static const struct rockchip_pmu_info rk3399_pmu = {
 853         .pwr_offset = 0x14,
 854         .status_offset = 0x18,
 855         .req_offset = 0x60,
 856         .idle_offset = 0x64,
 857         .ack_offset = 0x68,
 858
 859         .core_pwrcnt_offset = 0xac,
 860         .gpu_pwrcnt_offset = 0xac,
 861
 862         .core_power_transition_time = 6, /* 0.25us */
 863         .gpu_power_transition_time = 6, /* 0.25us */
 864
 865         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
 866         .domain_info = rk3399_pm_domains,
 867 };
 868
 869 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 870         {
 871                 .compatible = "rockchip,rk3288-power-controller",
 872                 .data = (void *)&rk3288_pmu,
 873         },
 874         {
 875                 .compatible = "rockchip,rk3328-power-controller",
 876                 .data = (void *)&rk3328_pmu,
 877         },
 878         {
 879                 .compatible = "rockchip,rk3366-power-controller",
 880                 .data = (void *)&rk3366_pmu,
 881         },
 882         {
 883                 .compatible = "rockchip,rk3368-power-controller",
 884                 .data = (void *)&rk3368_pmu,
 885         },
 886         {
 887                 .compatible = "rockchip,rk3399-power-controller",
 888                 .data = (void *)&rk3399_pmu,
 889         },
 890         { /* sentinel */ },
 891 };
 892
 893 static struct platform_driver rockchip_pm_domain_driver = {
 894         .probe = rockchip_pm_domain_probe,
 895         .driver = {
 896                 .name   = "rockchip-pm-domain",
 897                 .of_match_table = rockchip_pm_domain_dt_match,
 898                 /*
 899                  * We can't forcibly eject devices form power domain,
 900                  * so we can't really remove power domains once they
 901                  * were added.
 902                  */
 903                 .suppress_bind_attrs = true,
 904         },
 905 };
 906
 907 static int __init rockchip_pm_domain_drv_register(void)
 908 {
 909         return platform_driver_register(&rockchip_pm_domain_driver);
 910 }
 911 postcore_initcall(rockchip_pm_domain_drv_register);