drivers/phy/phy-rockchip-usb.c

   1 /*
   2  * Rockchip usb PHY driver
   3  *
   4  * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/phy/phy.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/reset.h>
  31 #include <linux/regmap.h>
  32 #include <linux/mfd/syscon.h>
  33
  34 /*
  35  * The higher 16-bit of this register is used for write protection
  36  * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
  37  */
  38 #define SIDDQ_WRITE_ENA BIT(29)
  39 #define SIDDQ_ON                BIT(13)
  40 #define SIDDQ_OFF               (0 << 13)
  41
  42 #define USB2_PHY_WRITE_ENA      (0xffff << 16)
  43 #define USB2_PHY_SUSPEND        (0x5 << 0 | 0xd << 4 | 0x1 << 8)
  44 #define USB2_PHY_RESUME (0)
  45
  46 #define UTMI_SEL_GRF_WR_ENA     (0x3 << 16)
  47 #define UTMI_SEL_GRF_SUSPEND    (0x1 << 0)
  48 #define UTMI_SEL_GRF_RESUME     (0x2 << 0)
  49
  50 struct rockchip_usb_phys {
  51         int reg;
  52         const char *pll_name;
  53 };
  54
  55 struct rockchip_usb_phy_pdata {
  56         struct rockchip_usb_phys *phys;
  57         unsigned int phy_pw_on;
  58         unsigned int phy_pw_off;
  59         bool siddq_ctl;
  60 };
  61
  62 struct rockchip_usb_phy_base {
  63         struct device *dev;
  64         struct regmap *reg_base;
  65         struct gpio_desc *vbus_drv_gpio;
  66         const struct rockchip_usb_phy_pdata *pdata;
  67 };
  68
  69 struct rockchip_usb_phy {
  70         struct rockchip_usb_phy_base *base;
  71         struct device_node *np;
  72         unsigned int    reg_offset;
  73         struct clk      *clk;
  74         struct clk      *clk480m;
  75         struct clk_hw   clk480m_hw;
  76         struct phy      *phy;
  77 };
  78
  79 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
  80                                            bool off)
  81 {
  82         unsigned int val;
  83
  84         val = !off ? phy->base->pdata->phy_pw_on : phy->base->pdata->phy_pw_off;
  85         return regmap_write(phy->base->reg_base, phy->reg_offset, val);
  86 }
  87
  88 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
  89                                                 unsigned long parent_rate)
  90 {
  91         return 480000000;
  92 }
  93
  94 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
  95 {
  96         struct rockchip_usb_phy *phy = container_of(hw,
  97                                                     struct rockchip_usb_phy,
  98                                                     clk480m_hw);
  99
 100         /* Power down usb phy analog blocks by set siddq 1 */
 101         if (phy->base->pdata->siddq_ctl)
 102                 rockchip_usb_phy_power(phy, 1);
 103 }
 104
 105 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
 106 {
 107         int ret = 0;
 108         struct rockchip_usb_phy *phy = container_of(hw,
 109                                                     struct rockchip_usb_phy,
 110                                                     clk480m_hw);
 111
 112         /* Power up usb phy analog blocks by set siddq 0 */
 113         if (phy->base->pdata->siddq_ctl)
 114                 ret = rockchip_usb_phy_power(phy, 0);
 115
 116         return ret;
 117 }
 118
 119 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
 120 {
 121         struct rockchip_usb_phy *phy = container_of(hw,
 122                                                     struct rockchip_usb_phy,
 123                                                     clk480m_hw);
 124         int ret = 1;
 125         u32 val;
 126
 127         if (phy->base->pdata->siddq_ctl) {
 128                 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
 129                 if (ret < 0)
 130                         return ret;
 131
 132                 ret = (val & SIDDQ_ON) ? 0 : 1;
 133         }
 134
 135         return ret;
 136 }
 137
 138 static const struct clk_ops rockchip_usb_phy480m_ops = {
 139         .enable = rockchip_usb_phy480m_enable,
 140         .disable = rockchip_usb_phy480m_disable,
 141         .is_enabled = rockchip_usb_phy480m_is_enabled,
 142         .recalc_rate = rockchip_usb_phy480m_recalc_rate,
 143 };
 144
 145 static int rockchip_usb_phy_power_off(struct phy *_phy)
 146 {
 147         int ret = 0;
 148         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 149
 150         if (!phy->base->pdata->siddq_ctl) {
 151                 ret = rockchip_usb_phy_power(phy, 1);
 152                 if (ret)
 153                         return ret;
 154         }
 155
 156         clk_disable_unprepare(phy->clk480m);
 157         return 0;
 158 }
 159
 160 static int rockchip_usb_phy_power_on(struct phy *_phy)
 161 {
 162         int ret = 0;
 163         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 164
 165         ret = clk_prepare_enable(phy->clk480m);
 166         if (ret)
 167                 return ret;
 168
 169         if (!phy->base->pdata->siddq_ctl)
 170                 ret = rockchip_usb_phy_power(phy, 0);
 171
 172         return ret;
 173 }
 174
 175 static const struct phy_ops ops = {
 176         .power_on       = rockchip_usb_phy_power_on,
 177         .power_off      = rockchip_usb_phy_power_off,
 178         .owner          = THIS_MODULE,
 179 };
 180
 181 static void rockchip_usb_phy_action(void *data)
 182 {
 183         struct rockchip_usb_phy *rk_phy = data;
 184
 185         of_clk_del_provider(rk_phy->np);
 186         clk_unregister(rk_phy->clk480m);
 187
 188         if (rk_phy->clk)
 189                 clk_put(rk_phy->clk);
 190 }
 191
 192 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 193                                  struct device_node *child)
 194 {
 195         struct rockchip_usb_phy *rk_phy;
 196         unsigned int reg_offset;
 197         const char *clk_name;
 198         struct clk_init_data init;
 199         int err, i;
 200
 201         rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
 202         if (!rk_phy)
 203                 return -ENOMEM;
 204
 205         rk_phy->base = base;
 206         rk_phy->np = child;
 207
 208         if (of_property_read_u32(child, "reg", &reg_offset)) {
 209                 dev_err(base->dev, "missing reg property in node %s\n",
 210                         child->name);
 211                 return -EINVAL;
 212         }
 213
 214         rk_phy->reg_offset = reg_offset;
 215
 216         rk_phy->clk = of_clk_get_by_name(child, "phyclk");
 217         if (IS_ERR(rk_phy->clk))
 218                 rk_phy->clk = NULL;
 219
 220         i = 0;
 221         init.name = NULL;
 222         while (base->pdata->phys[i].reg) {
 223                 if (base->pdata->phys[i].reg == reg_offset) {
 224                         init.name = base->pdata->phys[i].pll_name;
 225                         break;
 226                 }
 227                 i++;
 228         }
 229
 230         if (!init.name) {
 231                 dev_err(base->dev, "phy data not found\n");
 232                 return -EINVAL;
 233         }
 234
 235         if (rk_phy->clk) {
 236                 clk_name = __clk_get_name(rk_phy->clk);
 237                 init.flags = 0;
 238                 init.parent_names = &clk_name;
 239                 init.num_parents = 1;
 240         } else {
 241                 init.flags = CLK_IS_ROOT;
 242                 init.parent_names = NULL;
 243                 init.num_parents = 0;
 244         }
 245
 246         init.ops = &rockchip_usb_phy480m_ops;
 247         rk_phy->clk480m_hw.init = &init;
 248
 249         rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
 250         if (IS_ERR(rk_phy->clk480m)) {
 251                 err = PTR_ERR(rk_phy->clk480m);
 252                 goto err_clk;
 253         }
 254
 255         err = of_clk_add_provider(child, of_clk_src_simple_get,
 256                                   rk_phy->clk480m);
 257         if (err < 0)
 258                 goto err_clk_prov;
 259
 260         err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
 261         if (err)
 262                 goto err_devm_action;
 263
 264         rk_phy->phy = devm_phy_create(base->dev, child, &ops);
 265         if (IS_ERR(rk_phy->phy)) {
 266                 dev_err(base->dev, "failed to create PHY\n");
 267                 return PTR_ERR(rk_phy->phy);
 268         }
 269         phy_set_drvdata(rk_phy->phy, rk_phy);
 270
 271         /* only power up usb phy when it use, so disable it when init*/
 272         return rockchip_usb_phy_power(rk_phy, 1);
 273
 274 err_devm_action:
 275         of_clk_del_provider(child);
 276 err_clk_prov:
 277         clk_unregister(rk_phy->clk480m);
 278 err_clk:
 279         if (rk_phy->clk)
 280                 clk_put(rk_phy->clk);
 281         return err;
 282 }
 283
 284 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
 285         .phys = (struct rockchip_usb_phys[]){
 286                 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
 287                 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
 288                 { /* sentinel */ }
 289         },
 290         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 291         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 292         .siddq_ctl  = true,
 293 };
 294
 295 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
 296         .phys = (struct rockchip_usb_phys[]){
 297                 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
 298                 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
 299                 { /* sentinel */ }
 300         },
 301         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 302         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 303         .siddq_ctl  = true,
 304 };
 305
 306 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
 307         .phys = (struct rockchip_usb_phys[]){
 308                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
 309                 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
 310                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
 311                 { /* sentinel */ }
 312         },
 313         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 314         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 315         .siddq_ctl  = true,
 316 };
 317
 318 static const struct rockchip_usb_phy_pdata rk336x_pdata = {
 319         .phys = (struct rockchip_usb_phys[]){
 320                 { .reg = 0x700, .pll_name = "sclk_otgphy0_480m" },
 321                 { .reg = 0x728, .pll_name = "sclk_otgphy1_480m" },
 322                 { /* sentinel */ }
 323         },
 324         .phy_pw_on  = USB2_PHY_WRITE_ENA | USB2_PHY_RESUME,
 325         .phy_pw_off = USB2_PHY_WRITE_ENA | USB2_PHY_SUSPEND,
 326         .siddq_ctl  = false,
 327 };
 328
 329 static const struct rockchip_usb_phy_pdata rk3399_pdata = {
 330         .phys = (struct rockchip_usb_phys[]){
 331                 { .reg = 0xe458, .pll_name = "sclk_otgphy0_480m" },
 332                 { .reg = 0xe468, .pll_name = "sclk_otgphy1_480m" },
 333                 { /* sentinel */ }
 334         },
 335         .phy_pw_on  = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_RESUME,
 336         .phy_pw_off = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_SUSPEND,
 337         .siddq_ctl  = false,
 338 };
 339
 340 static int rockchip_usb_phy_probe(struct platform_device *pdev)
 341 {
 342         struct device *dev = &pdev->dev;
 343         struct rockchip_usb_phy_base *phy_base;
 344         struct phy_provider *phy_provider;
 345         const struct of_device_id *match;
 346         struct device_node *child;
 347         int err;
 348
 349         phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
 350         if (!phy_base)
 351                 return -ENOMEM;
 352
 353         match = of_match_device(dev->driver->of_match_table, dev);
 354         if (!match || !match->data) {
 355                 dev_err(dev, "missing phy data\n");
 356                 return -EINVAL;
 357         }
 358
 359         phy_base->pdata = match->data;
 360
 361         phy_base->dev = dev;
 362         phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
 363                                                              "rockchip,grf");
 364         if (IS_ERR(phy_base->reg_base)) {
 365                 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
 366                 return PTR_ERR(phy_base->reg_base);
 367         }
 368
 369         /* Request the vbus_drv GPIO asserted */
 370         phy_base->vbus_drv_gpio =
 371                 devm_gpiod_get_optional(dev, "vbus_drv", GPIOD_OUT_HIGH);
 372         if (!phy_base->vbus_drv_gpio)
 373                 dev_info(&pdev->dev, "vbus_drv is not assigned!\n");
 374         else if (IS_ERR(phy_base->vbus_drv_gpio))
 375                 return PTR_ERR(phy_base->vbus_drv_gpio);
 376
 377         for_each_available_child_of_node(dev->of_node, child) {
 378                 err = rockchip_usb_phy_init(phy_base, child);
 379                 if (err) {
 380                         of_node_put(child);
 381                         return err;
 382                 }
 383         }
 384
 385         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 386         return PTR_ERR_OR_ZERO(phy_provider);
 387 }
 388
 389 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
 390         { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
 391         { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
 392         { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
 393         {}
 394 };
 395
 396 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
 397
 398 static struct platform_driver rockchip_usb_driver = {
 399         .probe          = rockchip_usb_phy_probe,
 400         .driver         = {
 401                 .name   = "rockchip-usb-phy",
 402                 .of_match_table = rockchip_usb_phy_dt_ids,
 403         },
 404 };
 405
 406 module_platform_driver(rockchip_usb_driver);
 407
 408 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 409 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 410 MODULE_LICENSE("GPL v2");