drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/wakelock.h>
  40
  41 #define BIT_WRITEABLE_SHIFT     16
  42 #define SCHEDULE_DELAY          (60 * HZ)
  43 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  44
  45 struct rockchip_usb2phy;
  46
  47 enum rockchip_usb2phy_port_id {
  48         USB2PHY_PORT_OTG,
  49         USB2PHY_PORT_HOST,
  50         USB2PHY_NUM_PORTS,
  51 };
  52
  53 enum rockchip_usb2phy_host_state {
  54         PHY_STATE_HS_ONLINE     = 0,
  55         PHY_STATE_DISCONNECT    = 1,
  56         PHY_STATE_CONNECT       = 2,
  57         PHY_STATE_FS_LS_ONLINE  = 4,
  58 };
  59
  60 /**
  61  * Different states involved in USB charger detection.
  62  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  63  *                              process is not yet started.
  64  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  65  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  66  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  67  *                              between SDP and DCP/CDP).
  68  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  69  *                              between DCP and CDP).
  70  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  71  */
  72 enum usb_chg_state {
  73         USB_CHG_STATE_UNDEFINED = 0,
  74         USB_CHG_STATE_WAIT_FOR_DCD,
  75         USB_CHG_STATE_DCD_DONE,
  76         USB_CHG_STATE_PRIMARY_DONE,
  77         USB_CHG_STATE_SECONDARY_DONE,
  78         USB_CHG_STATE_DETECTED,
  79 };
  80
  81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  82         EXTCON_USB,
  83         EXTCON_USB_HOST,
  84         EXTCON_USB_VBUS_EN,
  85         EXTCON_CHG_USB_SDP,
  86         EXTCON_CHG_USB_CDP,
  87         EXTCON_CHG_USB_DCP,
  88         EXTCON_CHG_USB_SLOW,
  89         EXTCON_NONE,
  90 };
  91
  92 struct usb2phy_reg {
  93         unsigned int    offset;
  94         unsigned int    bitend;
  95         unsigned int    bitstart;
  96         unsigned int    disable;
  97         unsigned int    enable;
  98 };
  99
 100 /**
 101  * struct rockchip_chg_det_reg: usb charger detect registers
 102  * @cp_det: charging port detected successfully.
 103  * @dcp_det: dedicated charging port detected successfully.
 104  * @dp_det: assert data pin connect successfully.
 105  * @idm_sink_en: open dm sink curren.
 106  * @idp_sink_en: open dp sink current.
 107  * @idp_src_en: open dm source current.
 108  * @rdm_pdwn_en: open dm pull down resistor.
 109  * @vdm_src_en: open dm voltage source.
 110  * @vdp_src_en: open dp voltage source.
 111  * @opmode: utmi operational mode.
 112  */
 113 struct rockchip_chg_det_reg {
 114         struct usb2phy_reg      cp_det;
 115         struct usb2phy_reg      dcp_det;
 116         struct usb2phy_reg      dp_det;
 117         struct usb2phy_reg      idm_sink_en;
 118         struct usb2phy_reg      idp_sink_en;
 119         struct usb2phy_reg      idp_src_en;
 120         struct usb2phy_reg      rdm_pdwn_en;
 121         struct usb2phy_reg      vdm_src_en;
 122         struct usb2phy_reg      vdp_src_en;
 123         struct usb2phy_reg      opmode;
 124 };
 125
 126 /**
 127  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 128  * @phy_sus: phy suspend register.
 129  * @bvalid_det_en: vbus valid rise detection enable register.
 130  * @bvalid_det_st: vbus valid rise detection status register.
 131  * @bvalid_det_clr: vbus valid rise detection clear register.
 132  * @ls_det_en: linestate detection enable register.
 133  * @ls_det_st: linestate detection state register.
 134  * @ls_det_clr: linestate detection clear register.
 135  * @idfall_det_en: id fall detection enable register.
 136  * @idfall_det_st: id fall detection state register.
 137  * @idfall_det_clr: id fall detection clear register.
 138  * @idrise_det_en: id rise detection enable register.
 139  * @idrise_det_st: id rise detection state register.
 140  * @idrise_det_clr: id rise detection clear register.
 141  * @utmi_avalid: utmi vbus avalid status register.
 142  * @utmi_bvalid: utmi vbus bvalid status register.
 143  * @utmi_iddig: otg port id pin status register.
 144  * @utmi_ls: utmi linestate state register.
 145  * @utmi_hstdet: utmi host disconnect register.
 146  * @vbus_det_en: vbus detect function power down register.
 147  */
 148 struct rockchip_usb2phy_port_cfg {
 149         struct usb2phy_reg      phy_sus;
 150         struct usb2phy_reg      bvalid_det_en;
 151         struct usb2phy_reg      bvalid_det_st;
 152         struct usb2phy_reg      bvalid_det_clr;
 153         struct usb2phy_reg      ls_det_en;
 154         struct usb2phy_reg      ls_det_st;
 155         struct usb2phy_reg      ls_det_clr;
 156         struct usb2phy_reg      idfall_det_en;
 157         struct usb2phy_reg      idfall_det_st;
 158         struct usb2phy_reg      idfall_det_clr;
 159         struct usb2phy_reg      idrise_det_en;
 160         struct usb2phy_reg      idrise_det_st;
 161         struct usb2phy_reg      idrise_det_clr;
 162         struct usb2phy_reg      utmi_avalid;
 163         struct usb2phy_reg      utmi_bvalid;
 164         struct usb2phy_reg      utmi_iddig;
 165         struct usb2phy_reg      utmi_ls;
 166         struct usb2phy_reg      utmi_hstdet;
 167         struct usb2phy_reg      vbus_det_en;
 168 };
 169
 170 /**
 171  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 172  * @reg: the address offset of grf for usb-phy config.
 173  * @num_ports: specify how many ports that the phy has.
 174  * @phy_tuning: phy default parameters tunning.
 175  * @clkout_ctl: keep on/turn off output clk of phy.
 176  * @chg_det: charger detection registers.
 177  */
 178 struct rockchip_usb2phy_cfg {
 179         unsigned int    reg;
 180         unsigned int    num_ports;
 181         int (*phy_tuning)(struct rockchip_usb2phy *);
 182         struct usb2phy_reg      clkout_ctl;
 183         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 184         const struct rockchip_chg_det_reg       chg_det;
 185 };
 186
 187 /**
 188  * struct rockchip_usb2phy_port: usb-phy port data.
 189  * @port_id: flag for otg port or host port.
 190  * @perip_connected: flag for periphyeral connect status.
 191  * @suspended: phy suspended flag.
 192  * @utmi_avalid: utmi avalid status usage flag.
 193  *      true    - use avalid to get vbus status
 194  *      flase   - use bvalid to get vbus status
 195  * @vbus_attached: otg device vbus status.
 196  * @vbus_always_on: otg vbus is always powered on.
 197  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 198  * @vbus_drv_gpio: gpio description for vbus control.
 199  * @ls_irq: IRQ number assigned for linestate detection.
 200  * @id_irq: IRQ number assigned for id fall or rise detection.
 201  * @mutex: for register updating in sm_work.
 202  * @chg_work: charge detect work.
 203  * @otg_sm_work: OTG state machine work.
 204  * @sm_work: HOST state machine work.
 205  * @phy_cfg: port register configuration, assigned by driver data.
 206  * @event_nb: hold event notification callback.
 207  * @wakelock: wake lock struct to prevent system suspend
 208  *            when USB is active.
 209  * @state: define OTG enumeration states before device reset.
 210  * @mode: the dr_mode of the controller.
 211  */
 212 struct rockchip_usb2phy_port {
 213         struct phy      *phy;
 214         unsigned int    port_id;
 215         bool            perip_connected;
 216         bool            suspended;
 217         bool            utmi_avalid;
 218         bool            vbus_attached;
 219         bool            vbus_always_on;
 220         int             bvalid_irq;
 221         int             ls_irq;
 222         int             id_irq;
 223         struct mutex    mutex;
 224         struct          delayed_work chg_work;
 225         struct          delayed_work otg_sm_work;
 226         struct          delayed_work sm_work;
 227         struct          gpio_desc *vbus_drv_gpio;
 228         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 229         struct notifier_block   event_nb;
 230         struct wake_lock        wakelock;
 231         enum usb_otg_state      state;
 232         enum usb_dr_mode        mode;
 233 };
 234
 235 /**
 236  * struct rockchip_usb2phy: usb2.0 phy driver data.
 237  * @grf: General Register Files regmap.
 238  * @clk: clock struct of phy input clk.
 239  * @clk480m: clock struct of phy output clk.
 240  * @clk_hw: clock struct of phy output clk management.
 241  * @chg_state: states involved in USB charger detection.
 242  * @chg_type: USB charger types.
 243  * @dcd_retries: The retry count used to track Data contact
 244  *               detection process.
 245  * @edev_self: represent the source of extcon.
 246  * @edev: extcon device for notification registration
 247  * @phy_cfg: phy register configuration, assigned by driver data.
 248  * @ports: phy port instance.
 249  */
 250 struct rockchip_usb2phy {
 251         struct device   *dev;
 252         struct regmap   *grf;
 253         struct clk      *clk;
 254         struct clk      *clk480m;
 255         struct clk_hw   clk480m_hw;
 256         enum usb_chg_state      chg_state;
 257         enum power_supply_type  chg_type;
 258         u8                      dcd_retries;
 259         u8                      primary_retries;
 260         bool                    edev_self;
 261         struct extcon_dev       *edev;
 262         const struct rockchip_usb2phy_cfg       *phy_cfg;
 263         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 264 };
 265
 266 static inline int property_enable(struct rockchip_usb2phy *rphy,
 267                                   const struct usb2phy_reg *reg, bool en)
 268 {
 269         unsigned int val, mask, tmp;
 270
 271         tmp = en ? reg->enable : reg->disable;
 272         mask = GENMASK(reg->bitend, reg->bitstart);
 273         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 274
 275         return regmap_write(rphy->grf, reg->offset, val);
 276 }
 277
 278 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 279                                     const struct usb2phy_reg *reg)
 280 {
 281         int ret;
 282         unsigned int tmp, orig;
 283         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 284
 285         ret = regmap_read(rphy->grf, reg->offset, &orig);
 286         if (ret)
 287                 return false;
 288
 289         tmp = (orig & mask) >> reg->bitstart;
 290         return tmp == reg->enable;
 291 }
 292
 293 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 294 {
 295         struct rockchip_usb2phy *rphy =
 296                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 297         int ret;
 298
 299         /* turn on 480m clk output if it is off */
 300         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 301                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 302                 if (ret)
 303                         return ret;
 304
 305                 /* waiting for the clk become stable */
 306                 usleep_range(1200, 1300);
 307         }
 308
 309         return 0;
 310 }
 311
 312 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 313 {
 314         struct rockchip_usb2phy *rphy =
 315                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 316
 317         /* turn off 480m clk output */
 318         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 319 }
 320
 321 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 322 {
 323         struct rockchip_usb2phy *rphy =
 324                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 325
 326         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 327 }
 328
 329 static unsigned long
 330 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 331                                      unsigned long parent_rate)
 332 {
 333         return 480000000;
 334 }
 335
 336 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 337         .prepare = rockchip_usb2phy_clk480m_prepare,
 338         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 339         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 340         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 341 };
 342
 343 static void rockchip_usb2phy_clk480m_unregister(void *data)
 344 {
 345         struct rockchip_usb2phy *rphy = data;
 346
 347         of_clk_del_provider(rphy->dev->of_node);
 348         clk_unregister(rphy->clk480m);
 349 }
 350
 351 static int
 352 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 353 {
 354         struct device_node *node = rphy->dev->of_node;
 355         struct clk_init_data init;
 356         const char *clk_name;
 357         int ret;
 358
 359         init.flags = 0;
 360         init.name = "clk_usbphy_480m";
 361         init.ops = &rockchip_usb2phy_clkout_ops;
 362
 363         /* optional override of the clockname */
 364         of_property_read_string(node, "clock-output-names", &init.name);
 365
 366         if (rphy->clk) {
 367                 clk_name = __clk_get_name(rphy->clk);
 368                 init.parent_names = &clk_name;
 369                 init.num_parents = 1;
 370         } else {
 371                 init.parent_names = NULL;
 372                 init.num_parents = 0;
 373         }
 374
 375         rphy->clk480m_hw.init = &init;
 376
 377         /* register the clock */
 378         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 379         if (IS_ERR(rphy->clk480m)) {
 380                 ret = PTR_ERR(rphy->clk480m);
 381                 goto err_ret;
 382         }
 383
 384         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 385         if (ret < 0)
 386                 goto err_clk_provider;
 387
 388         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 389                               rphy);
 390         if (ret < 0)
 391                 goto err_unreg_action;
 392
 393         return 0;
 394
 395 err_unreg_action:
 396         of_clk_del_provider(node);
 397 err_clk_provider:
 398         clk_unregister(rphy->clk480m);
 399 err_ret:
 400         return ret;
 401 }
 402
 403 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 404 {
 405         int ret;
 406         struct device_node *node = rphy->dev->of_node;
 407         struct extcon_dev *edev;
 408
 409         if (of_property_read_bool(node, "extcon")) {
 410                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 411                 if (IS_ERR(edev)) {
 412                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 413                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 414                         return PTR_ERR(edev);
 415                 }
 416         } else {
 417                 /* Initialize extcon device */
 418                 edev = devm_extcon_dev_allocate(rphy->dev,
 419                                                 rockchip_usb2phy_extcon_cable);
 420
 421                 if (IS_ERR(edev))
 422                         return -ENOMEM;
 423
 424                 ret = devm_extcon_dev_register(rphy->dev, edev);
 425                 if (ret) {
 426                         dev_err(rphy->dev, "failed to register extcon device\n");
 427                         return ret;
 428                 }
 429
 430                 rphy->edev_self = true;
 431         }
 432
 433         rphy->edev = edev;
 434
 435         return 0;
 436 }
 437
 438 static int rockchip_usb2phy_init(struct phy *phy)
 439 {
 440         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 441         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 442         int ret = 0;
 443
 444         mutex_lock(&rport->mutex);
 445
 446         if (rport->port_id == USB2PHY_PORT_OTG) {
 447                 if (rport->mode != USB_DR_MODE_HOST &&
 448                     !rport->vbus_always_on) {
 449                         /* clear bvalid status and enable bvalid detect irq */
 450                         ret = property_enable(rphy,
 451                                               &rport->port_cfg->
 452                                               bvalid_det_clr,
 453                                               true);
 454                         if (ret)
 455                                 goto out;
 456
 457                         ret = property_enable(rphy,
 458                                               &rport->port_cfg->
 459                                               bvalid_det_en,
 460                                               true);
 461                         if (ret)
 462                                 goto out;
 463
 464                         if (rphy->edev_self) {
 465                                 ret = property_enable(rphy,
 466                                                       &rport->port_cfg->
 467                                                       idfall_det_clr,
 468                                                       true);
 469                                 if (ret)
 470                                         goto out;
 471
 472                                 ret = property_enable(rphy,
 473                                                       &rport->port_cfg->
 474                                                       idfall_det_en,
 475                                                       true);
 476                                 if (ret)
 477                                         goto out;
 478
 479                                 ret = property_enable(rphy,
 480                                                       &rport->port_cfg->
 481                                                       idrise_det_clr,
 482                                                       true);
 483                                 if (ret)
 484                                         goto out;
 485
 486                                 ret = property_enable(rphy,
 487                                                       &rport->port_cfg->
 488                                                       idrise_det_en,
 489                                                       true);
 490                                 if (ret)
 491                                         goto out;
 492                         }
 493
 494                         schedule_delayed_work(&rport->otg_sm_work,
 495                                               OTG_SCHEDULE_DELAY);
 496                 } else {
 497                         /* If OTG works in host only mode, do nothing. */
 498                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 499                 }
 500         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 501                 /* clear linestate and enable linestate detect irq */
 502                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 503                 if (ret)
 504                         goto out;
 505
 506                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 507                 if (ret)
 508                         goto out;
 509
 510                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 511         }
 512
 513 out:
 514         mutex_unlock(&rport->mutex);
 515         return ret;
 516 }
 517
 518 static int rockchip_usb2phy_power_on(struct phy *phy)
 519 {
 520         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 521         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 522         int ret;
 523
 524         dev_dbg(&rport->phy->dev, "port power on\n");
 525
 526         if (!rport->suspended)
 527                 return 0;
 528
 529         ret = clk_prepare_enable(rphy->clk480m);
 530         if (ret)
 531                 return ret;
 532
 533         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 534         if (ret)
 535                 return ret;
 536
 537         rport->suspended = false;
 538         return 0;
 539 }
 540
 541 static int rockchip_usb2phy_power_off(struct phy *phy)
 542 {
 543         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 544         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 545         int ret;
 546
 547         dev_dbg(&rport->phy->dev, "port power off\n");
 548
 549         if (rport->suspended)
 550                 return 0;
 551
 552         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 553         if (ret)
 554                 return ret;
 555
 556         rport->suspended = true;
 557         clk_disable_unprepare(rphy->clk480m);
 558
 559         return 0;
 560 }
 561
 562 static int rockchip_usb2phy_exit(struct phy *phy)
 563 {
 564         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 565
 566         if (rport->port_id == USB2PHY_PORT_OTG &&
 567             rport->mode != USB_DR_MODE_HOST &&
 568             !rport->vbus_always_on)
 569                 cancel_delayed_work_sync(&rport->chg_work);
 570         else if (rport->port_id == USB2PHY_PORT_HOST)
 571                 cancel_delayed_work_sync(&rport->sm_work);
 572
 573         return 0;
 574 }
 575
 576 static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
 577 {
 578         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 579         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 580         bool vbus_det_en;
 581         int ret = 0;
 582
 583         if (rport->port_id != USB2PHY_PORT_OTG ||
 584             !rport->vbus_always_on)
 585                 return ret;
 586
 587         switch (mode) {
 588         case PHY_MODE_USB_OTG:
 589                 /*
 590                  * In case of using vbus to detect connect state by u2phy,
 591                  * enable vbus detect on otg mode.
 592                  *
 593                  * fallthrough
 594                  */
 595         case PHY_MODE_USB_DEVICE:
 596                 vbus_det_en = true;
 597                 break;
 598         case PHY_MODE_USB_HOST:
 599                 /* fallthrough */
 600         case PHY_MODE_INVALID:
 601                 vbus_det_en = false;
 602                 break;
 603         default:
 604                 dev_info(&rport->phy->dev, "illegal mode\n");
 605                 return ret;
 606         }
 607
 608         ret = property_enable(rphy, &rport->port_cfg->vbus_det_en, vbus_det_en);
 609
 610         return ret;
 611 }
 612 static const struct phy_ops rockchip_usb2phy_ops = {
 613         .init           = rockchip_usb2phy_init,
 614         .exit           = rockchip_usb2phy_exit,
 615         .power_on       = rockchip_usb2phy_power_on,
 616         .power_off      = rockchip_usb2phy_power_off,
 617         .set_mode       = rockchip_usb2phy_set_mode,
 618         .owner          = THIS_MODULE,
 619 };
 620
 621 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 622 {
 623         struct rockchip_usb2phy_port *rport =
 624                 container_of(work, struct rockchip_usb2phy_port,
 625                              otg_sm_work.work);
 626         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 627         static unsigned int cable;
 628         unsigned long delay;
 629         bool sch_work;
 630
 631         if (rport->utmi_avalid)
 632                 rport->vbus_attached =
 633                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 634         else
 635                 rport->vbus_attached =
 636                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 637
 638         sch_work = false;
 639         delay = OTG_SCHEDULE_DELAY;
 640
 641         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 642                 usb_otg_state_string(rport->state));
 643
 644         switch (rport->state) {
 645         case OTG_STATE_UNDEFINED:
 646                 rport->state = OTG_STATE_B_IDLE;
 647                 if (!rport->vbus_attached)
 648                         rockchip_usb2phy_power_off(rport->phy);
 649                 /* fall through */
 650         case OTG_STATE_B_IDLE:
 651                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
 652                     extcon_get_cable_state_(rphy->edev,
 653                                             EXTCON_USB_VBUS_EN) > 0) {
 654                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 655                         rport->state = OTG_STATE_A_HOST;
 656                         rockchip_usb2phy_power_on(rport->phy);
 657                         return;
 658                 } else if (rport->vbus_attached) {
 659                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 660                         switch (rphy->chg_state) {
 661                         case USB_CHG_STATE_UNDEFINED:
 662                                 schedule_delayed_work(&rport->chg_work, 0);
 663                                 return;
 664                         case USB_CHG_STATE_DETECTED:
 665                                 switch (rphy->chg_type) {
 666                                 case POWER_SUPPLY_TYPE_USB:
 667                                         dev_dbg(&rport->phy->dev,
 668                                                 "sdp cable is connecetd\n");
 669                                         wake_lock(&rport->wakelock);
 670                                         cable = EXTCON_CHG_USB_SDP;
 671                                         rockchip_usb2phy_power_on(rport->phy);
 672                                         rport->state = OTG_STATE_B_PERIPHERAL;
 673                                         rport->perip_connected = true;
 674                                         sch_work = true;
 675                                         break;
 676                                 case POWER_SUPPLY_TYPE_USB_DCP:
 677                                         dev_dbg(&rport->phy->dev,
 678                                                 "dcp cable is connecetd\n");
 679                                         cable = EXTCON_CHG_USB_DCP;
 680                                         rockchip_usb2phy_power_off(rport->phy);
 681                                         sch_work = true;
 682                                         break;
 683                                 case POWER_SUPPLY_TYPE_USB_CDP:
 684                                         dev_dbg(&rport->phy->dev,
 685                                                 "cdp cable is connecetd\n");
 686                                         wake_lock(&rport->wakelock);
 687                                         cable = EXTCON_CHG_USB_CDP;
 688                                         rockchip_usb2phy_power_on(rport->phy);
 689                                         rport->state = OTG_STATE_B_PERIPHERAL;
 690                                         rport->perip_connected = true;
 691                                         sch_work = true;
 692                                         break;
 693                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 694                                         dev_dbg(&rport->phy->dev,
 695                                                 "floating cable is connecetd\n");
 696                                         cable = EXTCON_CHG_USB_DCP;
 697                                         rockchip_usb2phy_power_off(rport->phy);
 698                                         sch_work = true;
 699                                         break;
 700                                 default:
 701                                         break;
 702                                 }
 703                                 break;
 704                         default:
 705                                 break;
 706                         }
 707                 } else {
 708                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 709                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 710                 }
 711                 break;
 712         case OTG_STATE_B_PERIPHERAL:
 713                 if (!rport->vbus_attached) {
 714                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 715                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 716                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 717                         rport->state = OTG_STATE_B_IDLE;
 718                         rport->perip_connected = false;
 719                         delay = 0;
 720                         rockchip_usb2phy_power_off(rport->phy);
 721                         wake_unlock(&rport->wakelock);
 722                 } else {
 723                         sch_work = true;
 724                 }
 725                 break;
 726         case OTG_STATE_A_HOST:
 727                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 728                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 729                         rport->state = OTG_STATE_B_IDLE;
 730                         rockchip_usb2phy_power_off(rport->phy);
 731                 }
 732                 return;
 733         default:
 734                 return;
 735         }
 736
 737         if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
 738                 extcon_set_cable_state_(rphy->edev,
 739                                         cable, rport->vbus_attached);
 740
 741         if (rphy->edev_self &&
 742             (extcon_get_state(rphy->edev, EXTCON_USB) !=
 743              rport->perip_connected))
 744                 extcon_set_cable_state_(rphy->edev,
 745                                         EXTCON_USB,
 746                                         rport->perip_connected);
 747
 748         if (sch_work)
 749                 schedule_delayed_work(&rport->otg_sm_work, delay);
 750 }
 751
 752 static const char *chg_to_string(enum power_supply_type chg_type)
 753 {
 754         switch (chg_type) {
 755         case POWER_SUPPLY_TYPE_USB:
 756                 return "USB_SDP_CHARGER";
 757         case POWER_SUPPLY_TYPE_USB_DCP:
 758                 return "USB_DCP_CHARGER";
 759         case POWER_SUPPLY_TYPE_USB_CDP:
 760                 return "USB_CDP_CHARGER";
 761         case POWER_SUPPLY_TYPE_USB_FLOATING:
 762                 return "USB_FLOATING_CHARGER";
 763         default:
 764                 return "INVALID_CHARGER";
 765         }
 766 }
 767
 768 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 769                                     bool en)
 770 {
 771         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 772         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 773 }
 774
 775 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 776                                             bool en)
 777 {
 778         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 779         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 780 }
 781
 782 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 783                                               bool en)
 784 {
 785         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 786         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 787 }
 788
 789 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 790 #define CHG_DCD_MAX_RETRIES     6
 791 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 792 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 793 static void rockchip_chg_detect_work(struct work_struct *work)
 794 {
 795         struct rockchip_usb2phy_port *rport =
 796                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 797         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 798         bool is_dcd, tmout, vout;
 799         unsigned long delay;
 800
 801         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 802                 rphy->chg_state);
 803         switch (rphy->chg_state) {
 804         case USB_CHG_STATE_UNDEFINED:
 805                 if (!rport->suspended)
 806                         rockchip_usb2phy_power_off(rport->phy);
 807                 /* put the controller in non-driving mode */
 808                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 809                 /* Start DCD processing stage 1 */
 810                 rockchip_chg_enable_dcd(rphy, true);
 811                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 812                 rphy->dcd_retries = 0;
 813                 rphy->primary_retries = 0;
 814                 delay = CHG_DCD_POLL_TIME;
 815                 break;
 816         case USB_CHG_STATE_WAIT_FOR_DCD:
 817                 /* get data contact detection status */
 818                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 819                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 820                 /* stage 2 */
 821                 if (is_dcd || tmout) {
 822                         /* stage 4 */
 823                         /* Turn off DCD circuitry */
 824                         rockchip_chg_enable_dcd(rphy, false);
 825                         /* Voltage Source on DP, Probe on DM */
 826                         rockchip_chg_enable_primary_det(rphy, true);
 827                         delay = CHG_PRIMARY_DET_TIME;
 828                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 829                 } else {
 830                         /* stage 3 */
 831                         delay = CHG_DCD_POLL_TIME;
 832                 }
 833                 break;
 834         case USB_CHG_STATE_DCD_DONE:
 835                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 836                 rockchip_chg_enable_primary_det(rphy, false);
 837                 if (vout) {
 838                         /* Voltage Source on DM, Probe on DP  */
 839                         rockchip_chg_enable_secondary_det(rphy, true);
 840                         delay = CHG_SECONDARY_DET_TIME;
 841                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 842                 } else {
 843                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 844                                 /* floating charger found */
 845                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 846                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 847                                 delay = 0;
 848                         } else {
 849                                 if (rphy->primary_retries < 2) {
 850                                         /* Turn off DCD circuitry */
 851                                         rockchip_chg_enable_dcd(rphy, false);
 852                                         /* Voltage Source on DP, Probe on DM */
 853                                         rockchip_chg_enable_primary_det(rphy,
 854                                                                         true);
 855                                         delay = CHG_PRIMARY_DET_TIME;
 856                                         rphy->chg_state =
 857                                                 USB_CHG_STATE_DCD_DONE;
 858                                         rphy->primary_retries++;
 859                                         /* break USB_CHG_STATE_DCD_DONE */
 860                                         break;
 861                                 }
 862                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 863                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 864                                 delay = 0;
 865                         }
 866                 }
 867                 break;
 868         case USB_CHG_STATE_PRIMARY_DONE:
 869                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 870                 /* Turn off voltage source */
 871                 rockchip_chg_enable_secondary_det(rphy, false);
 872                 if (vout)
 873                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 874                 else
 875                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 876                 /* fall through */
 877         case USB_CHG_STATE_SECONDARY_DONE:
 878                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 879                 delay = 0;
 880                 /* fall through */
 881         case USB_CHG_STATE_DETECTED:
 882                 /* put the controller in normal mode */
 883                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 884                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 885                 dev_info(&rport->phy->dev, "charger = %s\n",
 886                          chg_to_string(rphy->chg_type));
 887                 return;
 888         default:
 889                 return;
 890         }
 891
 892         schedule_delayed_work(&rport->chg_work, delay);
 893 }
 894
 895 /*
 896  * The function manage host-phy port state and suspend/resume phy port
 897  * to save power.
 898  *
 899  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 900  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 901  * disconnected or HS disconnected, actually, we just only need get the
 902  * device is disconnected at last through rearm the delayed work,
 903  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 904  *
 905  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 906  * some clk related APIs, so do not invoke it from interrupt context directly.
 907  */
 908 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 909 {
 910         struct rockchip_usb2phy_port *rport =
 911                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 912         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 913         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 914                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 915         unsigned int ul, uhd, state;
 916         unsigned int ul_mask, uhd_mask;
 917         int ret;
 918
 919         mutex_lock(&rport->mutex);
 920
 921         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 922         if (ret < 0)
 923                 goto next_schedule;
 924
 925         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 926                           &uhd);
 927         if (ret < 0)
 928                 goto next_schedule;
 929
 930         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 931                            rport->port_cfg->utmi_hstdet.bitstart);
 932         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 933                           rport->port_cfg->utmi_ls.bitstart);
 934
 935         /* stitch on utmi_ls and utmi_hstdet as phy state */
 936         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 937                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 938
 939         switch (state) {
 940         case PHY_STATE_HS_ONLINE:
 941                 dev_dbg(&rport->phy->dev, "HS online\n");
 942                 break;
 943         case PHY_STATE_FS_LS_ONLINE:
 944                 /*
 945                  * For FS/LS device, the online state share with connect state
 946                  * from utmi_ls and utmi_hstdet register, so we distinguish
 947                  * them via suspended flag.
 948                  *
 949                  * Plus, there are two cases, one is D- Line pull-up, and D+
 950                  * line pull-down, the state is 4; another is D+ line pull-up,
 951                  * and D- line pull-down, the state is 2.
 952                  */
 953                 if (!rport->suspended) {
 954                         /* D- line pull-up, D+ line pull-down */
 955                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 956                         break;
 957                 }
 958                 /* fall through */
 959         case PHY_STATE_CONNECT:
 960                 if (rport->suspended) {
 961                         dev_dbg(&rport->phy->dev, "Connected\n");
 962                         rockchip_usb2phy_power_on(rport->phy);
 963                         rport->suspended = false;
 964                 } else {
 965                         /* D+ line pull-up, D- line pull-down */
 966                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 967                 }
 968                 break;
 969         case PHY_STATE_DISCONNECT:
 970                 if (!rport->suspended) {
 971                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 972                         rockchip_usb2phy_power_off(rport->phy);
 973                         rport->suspended = true;
 974                 }
 975
 976                 /*
 977                  * activate the linestate detection to get the next device
 978                  * plug-in irq.
 979                  */
 980                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 981                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 982
 983                 /*
 984                  * we don't need to rearm the delayed work when the phy port
 985                  * is suspended.
 986                  */
 987                 mutex_unlock(&rport->mutex);
 988                 return;
 989         default:
 990                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 991                 break;
 992         }
 993
 994 next_schedule:
 995         mutex_unlock(&rport->mutex);
 996         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 997 }
 998
 999 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
1000 {
1001         struct rockchip_usb2phy_port *rport = data;
1002         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1003
1004         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
1005                 return IRQ_NONE;
1006
1007         dev_dbg(&rport->phy->dev, "linestate interrupt\n");
1008
1009         mutex_lock(&rport->mutex);
1010
1011         /* disable linestate detect irq and clear its status */
1012         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
1013         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1014
1015         mutex_unlock(&rport->mutex);
1016
1017         /*
1018          * In this case for host phy port, a new device is plugged in,
1019          * meanwhile, if the phy port is suspended, we need rearm the work to
1020          * resume it and mange its states; otherwise, we do nothing about that.
1021          */
1022         if (rport->suspended) {
1023                 if (rport->port_id == USB2PHY_PORT_HOST)
1024                         rockchip_usb2phy_sm_work(&rport->sm_work.work);
1025                 else
1026                         rockchip_usb2phy_power_on(rport->phy);
1027         }
1028
1029         return IRQ_HANDLED;
1030 }
1031
1032 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1033 {
1034         struct rockchip_usb2phy_port *rport = data;
1035         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1036
1037         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
1038                 return IRQ_NONE;
1039
1040         mutex_lock(&rport->mutex);
1041
1042         /* clear bvalid detect irq pending status */
1043         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
1044
1045         mutex_unlock(&rport->mutex);
1046
1047         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1048
1049         return IRQ_HANDLED;
1050 }
1051
1052 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1053 {
1054         struct rockchip_usb2phy_port *rport = data;
1055         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1056         bool cable_vbus_state;
1057
1058         if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1059             !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1060                 return IRQ_NONE;
1061
1062         mutex_lock(&rport->mutex);
1063
1064         /* clear id fall or rise detect irq pending status */
1065         if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1066                 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1067                                 true);
1068                 cable_vbus_state = true;
1069         } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1070                 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1071                                 true);
1072                 cable_vbus_state = false;
1073         }
1074
1075         extcon_set_state(rphy->edev, EXTCON_USB_HOST, cable_vbus_state);
1076         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, cable_vbus_state);
1077
1078         extcon_sync(rphy->edev, EXTCON_USB_HOST);
1079         extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1080         gpiod_set_value_cansleep(rport->vbus_drv_gpio,
1081                                  cable_vbus_state ? 1 : 0);
1082
1083         mutex_unlock(&rport->mutex);
1084
1085         return IRQ_HANDLED;
1086 }
1087
1088 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1089                                            struct rockchip_usb2phy_port *rport,
1090                                            struct device_node *child_np)
1091 {
1092         int ret;
1093
1094         rport->port_id = USB2PHY_PORT_HOST;
1095         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1096         rport->suspended = true;
1097
1098         mutex_init(&rport->mutex);
1099         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1100
1101         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1102         if (rport->ls_irq < 0) {
1103                 dev_err(rphy->dev, "no linestate irq provided\n");
1104                 return rport->ls_irq;
1105         }
1106
1107         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1108                                         rockchip_usb2phy_linestate_irq,
1109                                         IRQF_ONESHOT,
1110                                         "rockchip_usb2phy", rport);
1111         if (ret) {
1112                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1113                 return ret;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static int rockchip_otg_event(struct notifier_block *nb,
1120                               unsigned long event, void *ptr)
1121 {
1122         struct rockchip_usb2phy_port *rport =
1123                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1124
1125         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1126
1127         return NOTIFY_DONE;
1128 }
1129
1130 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1131                                           struct rockchip_usb2phy_port *rport,
1132                                           struct device_node *child_np)
1133 {
1134         int ret;
1135         int iddig;
1136
1137         rport->port_id = USB2PHY_PORT_OTG;
1138         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1139         rport->state = OTG_STATE_UNDEFINED;
1140
1141         /*
1142          * set suspended flag to true, but actually don't
1143          * put phy in suspend mode, it aims to enable usb
1144          * phy and clock in power_on() called by usb controller
1145          * driver during probe.
1146          */
1147         rport->suspended = true;
1148         rport->vbus_attached = false;
1149         rport->perip_connected = false;
1150
1151         mutex_init(&rport->mutex);
1152
1153         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1154         if (rport->ls_irq < 0) {
1155                 dev_err(rphy->dev, "no linestate irq provided\n");
1156                 return rport->ls_irq;
1157         }
1158
1159         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1160                                         rockchip_usb2phy_linestate_irq,
1161                                         IRQF_ONESHOT,
1162                                         "rockchip_usb2phy", rport);
1163         if (ret) {
1164                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1165                 return ret;
1166         }
1167
1168         rport->vbus_drv_gpio = devm_gpiod_get_optional(rphy->dev, "otg-vbus",
1169                                                        GPIOD_OUT_LOW);
1170         if (!rport->vbus_drv_gpio) {
1171                 dev_warn(rphy->dev, "vbus_drv is not assigned\n");
1172         } else if (IS_ERR(rport->vbus_drv_gpio)) {
1173                 dev_err(rphy->dev, "failed to get vbus_drv\n");
1174                 return PTR_ERR(rport->vbus_drv_gpio);
1175         }
1176
1177         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1178         if (rport->mode == USB_DR_MODE_HOST) {
1179                 if (rphy->edev_self) {
1180                         extcon_set_state(rphy->edev, EXTCON_USB, false);
1181                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1182                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1183                         gpiod_set_value_cansleep(rport->vbus_drv_gpio, 1);
1184                 }
1185                 return 0;
1186         }
1187
1188         rport->vbus_always_on =
1189                 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1190         if (rport->vbus_always_on)
1191                 return 0;
1192
1193         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1194         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1195         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1196
1197         rport->utmi_avalid =
1198                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1199
1200         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1201         if (rport->bvalid_irq < 0) {
1202                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1203                 return rport->bvalid_irq;
1204         }
1205
1206         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1207                                         rockchip_usb2phy_bvalid_irq,
1208                                         IRQF_ONESHOT,
1209                                         "rockchip_usb2phy_bvalid", rport);
1210         if (ret) {
1211                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1212                 return ret;
1213         }
1214
1215         if (rphy->edev_self) {
1216                 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1217                 if (rport->id_irq < 0) {
1218                         dev_err(rphy->dev, "no otg id irq provided\n");
1219                         return rport->id_irq;
1220                 }
1221
1222                 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1223                                                 rockchip_usb2phy_id_irq,
1224                                                 IRQF_ONESHOT,
1225                                                 "rockchip_usb2phy_id", rport);
1226                 if (ret) {
1227                         dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1228                         return ret;
1229                 }
1230
1231                 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1232                 if (!iddig) {
1233                         extcon_set_state(rphy->edev, EXTCON_USB, false);
1234                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1235                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1236                         gpiod_set_value_cansleep(rport->vbus_drv_gpio, 1);
1237                 } else {
1238                         extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1239                         extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1240                         gpiod_set_value_cansleep(rport->vbus_drv_gpio, 0);
1241                 }
1242         }
1243
1244         if (!IS_ERR(rphy->edev)) {
1245                 rport->event_nb.notifier_call = rockchip_otg_event;
1246
1247                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1248                                                &rport->event_nb);
1249                 if (ret < 0) {
1250                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1251                         return ret;
1252                 }
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1259 {
1260         struct device *dev = &pdev->dev;
1261         struct device_node *np = dev->of_node;
1262         struct device_node *child_np;
1263         struct phy_provider *provider;
1264         struct rockchip_usb2phy *rphy;
1265         const struct rockchip_usb2phy_cfg *phy_cfgs;
1266         const struct of_device_id *match;
1267         unsigned int reg;
1268         int index, ret;
1269
1270         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1271         if (!rphy)
1272                 return -ENOMEM;
1273
1274         match = of_match_device(dev->driver->of_match_table, dev);
1275         if (!match || !match->data) {
1276                 dev_err(dev, "phy configs are not assigned!\n");
1277                 return -EINVAL;
1278         }
1279
1280         if (!dev->parent || !dev->parent->of_node)
1281                 return -EINVAL;
1282
1283         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1284         if (IS_ERR(rphy->grf))
1285                 return PTR_ERR(rphy->grf);
1286
1287         if (of_property_read_u32(np, "reg", &reg)) {
1288                 dev_err(dev, "the reg property is not assigned in %s node\n",
1289                         np->name);
1290                 return -EINVAL;
1291         }
1292
1293         rphy->dev = dev;
1294         phy_cfgs = match->data;
1295         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1296         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1297         rphy->edev_self = false;
1298         platform_set_drvdata(pdev, rphy);
1299
1300         ret = rockchip_usb2phy_extcon_register(rphy);
1301         if (ret)
1302                 return ret;
1303
1304         /* find out a proper config which can be matched with dt. */
1305         index = 0;
1306         while (phy_cfgs[index].reg) {
1307                 if (phy_cfgs[index].reg == reg) {
1308                         rphy->phy_cfg = &phy_cfgs[index];
1309                         break;
1310                 }
1311
1312                 ++index;
1313         }
1314
1315         if (!rphy->phy_cfg) {
1316                 dev_err(dev, "no phy-config can be matched with %s node\n",
1317                         np->name);
1318                 return -EINVAL;
1319         }
1320
1321         rphy->clk = of_clk_get_by_name(np, "phyclk");
1322         if (!IS_ERR(rphy->clk)) {
1323                 clk_prepare_enable(rphy->clk);
1324         } else {
1325                 dev_info(&pdev->dev, "no phyclk specified\n");
1326                 rphy->clk = NULL;
1327         }
1328
1329         ret = rockchip_usb2phy_clk480m_register(rphy);
1330         if (ret) {
1331                 dev_err(dev, "failed to register 480m output clock\n");
1332                 goto disable_clks;
1333         }
1334
1335         if (rphy->phy_cfg->phy_tuning) {
1336                 ret = rphy->phy_cfg->phy_tuning(rphy);
1337                 if (ret)
1338                         goto disable_clks;
1339         }
1340
1341         index = 0;
1342         for_each_available_child_of_node(np, child_np) {
1343                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1344                 struct phy *phy;
1345
1346                 /* This driver aims to support both otg-port and host-port */
1347                 if (of_node_cmp(child_np->name, "host-port") &&
1348                     of_node_cmp(child_np->name, "otg-port"))
1349                         goto next_child;
1350
1351                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1352                 if (IS_ERR(phy)) {
1353                         dev_err(dev, "failed to create phy\n");
1354                         ret = PTR_ERR(phy);
1355                         goto put_child;
1356                 }
1357
1358                 rport->phy = phy;
1359                 phy_set_drvdata(rport->phy, rport);
1360
1361                 /* initialize otg/host port separately */
1362                 if (!of_node_cmp(child_np->name, "host-port")) {
1363                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1364                                                               child_np);
1365                         if (ret)
1366                                 goto put_child;
1367                 } else {
1368                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1369                                                              child_np);
1370                         if (ret)
1371                                 goto put_child;
1372                 }
1373
1374 next_child:
1375                 /* to prevent out of boundary */
1376                 if (++index >= rphy->phy_cfg->num_ports)
1377                         break;
1378         }
1379
1380         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1381         return PTR_ERR_OR_ZERO(provider);
1382
1383 put_child:
1384         of_node_put(child_np);
1385 disable_clks:
1386         if (rphy->clk) {
1387                 clk_disable_unprepare(rphy->clk);
1388                 clk_put(rphy->clk);
1389         }
1390         return ret;
1391 }
1392
1393 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1394 {
1395         int ret;
1396
1397         /* Open debug mode for tuning */
1398         ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
1399         if (ret)
1400                 return ret;
1401
1402         /*
1403          * Open HS pre-emphasize function to increase
1404          * HS slew rate for host port
1405          */
1406         ret = regmap_write(rphy->grf, 0x30, 0xffff851d);
1407         if (ret)
1408                 return ret;
1409
1410         return 0;
1411 }
1412
1413 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1414 {
1415         unsigned int open_pre_emphasize = 0xffff851f;
1416         unsigned int eye_height_tuning = 0xffff68c8;
1417         unsigned int compensation_tuning = 0xffff026e;
1418         int ret = 0;
1419
1420         /* open HS pre-emphasize to expand HS slew rate for each port. */
1421         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1422         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1423         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1424         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1425
1426         /* compensate default tuning reference relate to ODT and etc. */
1427         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1428
1429         return ret;
1430 }
1431
1432 static int rk3399_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1433 {
1434         struct device_node *node = rphy->dev->of_node;
1435         int ret = 0;
1436
1437         if (!of_property_read_bool(node, "rockchip,u2phy-tuning"))
1438                 return ret;
1439
1440         if (rphy->phy_cfg->reg == 0xe450) {
1441                 /*
1442                  * Set max ODT compensation voltage and
1443                  * current tuning reference for PHY0.
1444                  */
1445                 ret |= regmap_write(rphy->grf, 0x448c,
1446                                     GENMASK(23, 16) | 0xe3);
1447
1448                 /* Set max pre-emphasis level for PHY0 */
1449                 ret |= regmap_write(rphy->grf, 0x44b0,
1450                                     GENMASK(18, 16) | 0x07);
1451
1452                 /*
1453                  * Disable the pre-emphasize in eop state
1454                  * and chirp state to avoid mis-trigger the
1455                  * disconnect detection and also avoid hs
1456                  * handshake fail for PHY0.
1457                  */
1458                 ret |= regmap_write(rphy->grf, 0x4480,
1459                                     GENMASK(17, 16) | 0x0);
1460                 ret |= regmap_write(rphy->grf, 0x44b4,
1461                                     GENMASK(17, 16) | 0x0);
1462         } else {
1463                 /*
1464                  * Set max ODT compensation voltage and
1465                  * current tuning reference for PHY1.
1466                  */
1467                 ret |= regmap_write(rphy->grf, 0x450c,
1468                                     GENMASK(23, 16) | 0xe3);
1469
1470                 /* Set max pre-emphasis level for PHY1 */
1471                 ret |= regmap_write(rphy->grf, 0x4530,
1472                                     GENMASK(18, 16) | 0x07);
1473
1474                 /*
1475                  * Disable the pre-emphasize in eop state
1476                  * and chirp state to avoid mis-trigger the
1477                  * disconnect detection and also avoid hs
1478                  * handshake fail for PHY1.
1479                  */
1480                 ret |= regmap_write(rphy->grf, 0x4500,
1481                                     GENMASK(17, 16) | 0x0);
1482                 ret |= regmap_write(rphy->grf, 0x4534,
1483                                     GENMASK(17, 16) | 0x0);
1484         }
1485
1486         return ret;
1487 }
1488
1489 #ifdef CONFIG_PM_SLEEP
1490 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1491 {
1492         struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1493         struct rockchip_usb2phy_port *rport;
1494         int index;
1495
1496         for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1497                 rport = &rphy->ports[index];
1498                 if (!rport->phy)
1499                         continue;
1500
1501                 /* activate the linestate to detect the next interrupt. */
1502                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1503                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int rockchip_usb2phy_pm_resume(struct device *dev)
1510 {
1511         return 0;
1512 }
1513
1514 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1515         SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1516                                 rockchip_usb2phy_pm_resume)
1517 };
1518
1519 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1520 #else
1521 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1522 #endif /* CONFIG_PM_SLEEP */
1523
1524 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1525         {
1526                 .reg = 0x100,
1527                 .num_ports      = 2,
1528                 .phy_tuning     = rk3328_usb2phy_tuning,
1529                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1530                 .port_cfgs      = {
1531                         [USB2PHY_PORT_HOST] = {
1532                                 .phy_sus        = { 0x104, 15, 0, 0, 0x1d1 },
1533                                 .ls_det_en      = { 0x110, 1, 1, 0, 1 },
1534                                 .ls_det_st      = { 0x114, 1, 1, 0, 1 },
1535                                 .ls_det_clr     = { 0x118, 1, 1, 0, 1 },
1536                                 .utmi_ls        = { 0x120, 17, 16, 0, 1 },
1537                                 .utmi_hstdet    = { 0x120, 19, 19, 0, 1 }
1538                         }
1539                 },
1540         },
1541         { /* sentinel */ }
1542 };
1543
1544 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1545         {
1546                 .reg = 0x700,
1547                 .num_ports      = 2,
1548                 .phy_tuning     = rk3366_usb2phy_tuning,
1549                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1550                 .port_cfgs      = {
1551                         [USB2PHY_PORT_HOST] = {
1552                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1553                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1554                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1555                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1556                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1557                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1558                         }
1559                 },
1560         },
1561         { /* sentinel */ }
1562 };
1563
1564 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1565         {
1566                 .reg            = 0xe450,
1567                 .num_ports      = 2,
1568                 .phy_tuning     = rk3399_usb2phy_tuning,
1569                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1570                 .port_cfgs      = {
1571                         [USB2PHY_PORT_OTG] = {
1572                                 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1573                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1574                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1575                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1576                                 .idfall_det_en  = { 0xe3c0, 5, 5, 0, 1 },
1577                                 .idfall_det_st  = { 0xe3e0, 5, 5, 0, 1 },
1578                                 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1579                                 .idrise_det_en  = { 0xe3c0, 4, 4, 0, 1 },
1580                                 .idrise_det_st  = { 0xe3e0, 4, 4, 0, 1 },
1581                                 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1582                                 .ls_det_en      = { 0xe3c0, 2, 2, 0, 1 },
1583                                 .ls_det_st      = { 0xe3e0, 2, 2, 0, 1 },
1584                                 .ls_det_clr     = { 0xe3d0, 2, 2, 0, 1 },
1585                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1586                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1587                                 .utmi_iddig     = { 0xe2ac, 8, 8, 0, 1 },
1588                                 .utmi_ls        = { 0xe2ac, 14, 13, 0, 1 },
1589                                 .vbus_det_en    = { 0x449c, 15, 15, 1, 0 },
1590                         },
1591                         [USB2PHY_PORT_HOST] = {
1592                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1593                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1594                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1595                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1596                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1597                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1598                         }
1599                 },
1600                 .chg_det = {
1601                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1602                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1603                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1604                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1605                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1606                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1607                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1608                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1609                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1610                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1611                 },
1612         },
1613         {
1614                 .reg            = 0xe460,
1615                 .num_ports      = 2,
1616                 .phy_tuning     = rk3399_usb2phy_tuning,
1617                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1618                 .port_cfgs      = {
1619                         [USB2PHY_PORT_OTG] = {
1620                                 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1621                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1622                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1623                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1624                                 .idfall_det_en  = { 0xe3c0, 10, 10, 0, 1 },
1625                                 .idfall_det_st  = { 0xe3e0, 10, 10, 0, 1 },
1626                                 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1627                                 .idrise_det_en  = { 0xe3c0, 9, 9, 0, 1 },
1628                                 .idrise_det_st  = { 0xe3e0, 9, 9, 0, 1 },
1629                                 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1630                                 .ls_det_en      = { 0xe3c0, 7, 7, 0, 1 },
1631                                 .ls_det_st      = { 0xe3e0, 7, 7, 0, 1 },
1632                                 .ls_det_clr     = { 0xe3d0, 7, 7, 0, 1 },
1633                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1634                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1635                                 .utmi_iddig     = { 0xe2ac, 11, 11, 0, 1 },
1636                                 .utmi_ls        = { 0xe2ac, 18, 17, 0, 1 },
1637                                 .vbus_det_en    = { 0x451c, 15, 15, 1, 0 },
1638                         },
1639                         [USB2PHY_PORT_HOST] = {
1640                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1641                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1642                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1643                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1644                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1645                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1646                         }
1647                 },
1648         },
1649         { /* sentinel */ }
1650 };
1651
1652 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1653         { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1654         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1655         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1656         {}
1657 };
1658 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1659
1660 static struct platform_driver rockchip_usb2phy_driver = {
1661         .probe          = rockchip_usb2phy_probe,
1662         .driver         = {
1663                 .name   = "rockchip-usb2phy",
1664                 .pm     = ROCKCHIP_USB2PHY_DEV_PM,
1665                 .of_match_table = rockchip_usb2phy_dt_match,
1666         },
1667 };
1668 module_platform_driver(rockchip_usb2phy_driver);
1669
1670 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1671 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1672 MODULE_LICENSE("GPL v2");