drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/wakelock.h>
  39
  40 #define BIT_WRITEABLE_SHIFT     16
  41 #define SCHEDULE_DELAY          (60 * HZ)
  42 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  43
  44 struct rockchip_usb2phy;
  45
  46 enum rockchip_usb2phy_port_id {
  47         USB2PHY_PORT_OTG,
  48         USB2PHY_PORT_HOST,
  49         USB2PHY_NUM_PORTS,
  50 };
  51
  52 enum rockchip_usb2phy_host_state {
  53         PHY_STATE_HS_ONLINE     = 0,
  54         PHY_STATE_DISCONNECT    = 1,
  55         PHY_STATE_CONNECT       = 2,
  56         PHY_STATE_FS_LS_ONLINE  = 4,
  57 };
  58
  59 /**
  60  * Different states involved in USB charger detection.
  61  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  62  *                              process is not yet started.
  63  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  64  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  65  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  66  *                              between SDP and DCP/CDP).
  67  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  68  *                              between DCP and CDP).
  69  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  70  */
  71 enum usb_chg_state {
  72         USB_CHG_STATE_UNDEFINED = 0,
  73         USB_CHG_STATE_WAIT_FOR_DCD,
  74         USB_CHG_STATE_DCD_DONE,
  75         USB_CHG_STATE_PRIMARY_DONE,
  76         USB_CHG_STATE_SECONDARY_DONE,
  77         USB_CHG_STATE_DETECTED,
  78 };
  79
  80 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  81         EXTCON_USB,
  82         EXTCON_USB_HOST,
  83         EXTCON_CHG_USB_SDP,
  84         EXTCON_CHG_USB_CDP,
  85         EXTCON_CHG_USB_DCP,
  86         EXTCON_CHG_USB_SLOW,
  87         EXTCON_NONE,
  88 };
  89
  90 struct usb2phy_reg {
  91         unsigned int    offset;
  92         unsigned int    bitend;
  93         unsigned int    bitstart;
  94         unsigned int    disable;
  95         unsigned int    enable;
  96 };
  97
  98 /**
  99  * struct rockchip_chg_det_reg: usb charger detect registers
 100  * @cp_det: charging port detected successfully.
 101  * @dcp_det: dedicated charging port detected successfully.
 102  * @dp_det: assert data pin connect successfully.
 103  * @idm_sink_en: open dm sink curren.
 104  * @idp_sink_en: open dp sink current.
 105  * @idp_src_en: open dm source current.
 106  * @rdm_pdwn_en: open dm pull down resistor.
 107  * @vdm_src_en: open dm voltage source.
 108  * @vdp_src_en: open dp voltage source.
 109  * @opmode: utmi operational mode.
 110  */
 111 struct rockchip_chg_det_reg {
 112         struct usb2phy_reg      cp_det;
 113         struct usb2phy_reg      dcp_det;
 114         struct usb2phy_reg      dp_det;
 115         struct usb2phy_reg      idm_sink_en;
 116         struct usb2phy_reg      idp_sink_en;
 117         struct usb2phy_reg      idp_src_en;
 118         struct usb2phy_reg      rdm_pdwn_en;
 119         struct usb2phy_reg      vdm_src_en;
 120         struct usb2phy_reg      vdp_src_en;
 121         struct usb2phy_reg      opmode;
 122 };
 123
 124 /**
 125  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 126  * @phy_sus: phy suspend register.
 127  * @bvalid_det_en: vbus valid rise detection enable register.
 128  * @bvalid_det_st: vbus valid rise detection status register.
 129  * @bvalid_det_clr: vbus valid rise detection clear register.
 130  * @ls_det_en: linestate detection enable register.
 131  * @ls_det_st: linestate detection state register.
 132  * @ls_det_clr: linestate detection clear register.
 133  * @utmi_avalid: utmi vbus avalid status register.
 134  * @utmi_bvalid: utmi vbus bvalid status register.
 135  * @utmi_ls: utmi linestate state register.
 136  * @utmi_hstdet: utmi host disconnect register.
 137  */
 138 struct rockchip_usb2phy_port_cfg {
 139         struct usb2phy_reg      phy_sus;
 140         struct usb2phy_reg      bvalid_det_en;
 141         struct usb2phy_reg      bvalid_det_st;
 142         struct usb2phy_reg      bvalid_det_clr;
 143         struct usb2phy_reg      ls_det_en;
 144         struct usb2phy_reg      ls_det_st;
 145         struct usb2phy_reg      ls_det_clr;
 146         struct usb2phy_reg      utmi_avalid;
 147         struct usb2phy_reg      utmi_bvalid;
 148         struct usb2phy_reg      utmi_ls;
 149         struct usb2phy_reg      utmi_hstdet;
 150 };
 151
 152 /**
 153  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 154  * @reg: the address offset of grf for usb-phy config.
 155  * @num_ports: specify how many ports that the phy has.
 156  * @phy_tuning: phy default parameters tunning.
 157  * @clkout_ctl: keep on/turn off output clk of phy.
 158  * @chg_det: charger detection registers.
 159  */
 160 struct rockchip_usb2phy_cfg {
 161         unsigned int    reg;
 162         unsigned int    num_ports;
 163         int (*phy_tuning)(struct rockchip_usb2phy *);
 164         struct usb2phy_reg      clkout_ctl;
 165         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 166         const struct rockchip_chg_det_reg       chg_det;
 167 };
 168
 169 /**
 170  * struct rockchip_usb2phy_port: usb-phy port data.
 171  * @port_id: flag for otg port or host port.
 172  * @suspended: phy suspended flag.
 173  * @utmi_avalid: utmi avalid status usage flag.
 174  *      true    - use avalid to get vbus status
 175  *      flase   - use bvalid to get vbus status
 176  * @vbus_attached: otg device vbus status.
 177  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 178  * @ls_irq: IRQ number assigned for linestate detection.
 179  * @mutex: for register updating in sm_work.
 180  * @chg_work: charge detect work.
 181  * @otg_sm_work: OTG state machine work.
 182  * @sm_work: HOST state machine work.
 183  * @phy_cfg: port register configuration, assigned by driver data.
 184  * @event_nb: hold event notification callback.
 185  * @wakelock: wake lock struct to prevent system suspend
 186  *            when USB is active.
 187  * @state: define OTG enumeration states before device reset.
 188  */
 189 struct rockchip_usb2phy_port {
 190         struct phy      *phy;
 191         unsigned int    port_id;
 192         bool            suspended;
 193         bool            utmi_avalid;
 194         bool            vbus_attached;
 195         int             bvalid_irq;
 196         int             ls_irq;
 197         struct mutex    mutex;
 198         struct          delayed_work chg_work;
 199         struct          delayed_work otg_sm_work;
 200         struct          delayed_work sm_work;
 201         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 202         struct notifier_block   event_nb;
 203         struct wake_lock        wakelock;
 204         enum usb_otg_state      state;
 205 };
 206
 207 /**
 208  * struct rockchip_usb2phy: usb2.0 phy driver data.
 209  * @grf: General Register Files regmap.
 210  * @clk: clock struct of phy input clk.
 211  * @clk480m: clock struct of phy output clk.
 212  * @clk_hw: clock struct of phy output clk management.
 213  * @chg_state: states involved in USB charger detection.
 214  * @chg_type: USB charger types.
 215  * @dcd_retries: The retry count used to track Data contact
 216  *               detection process.
 217  * @edev: extcon device for notification registration
 218  * @phy_cfg: phy register configuration, assigned by driver data.
 219  * @ports: phy port instance.
 220  */
 221 struct rockchip_usb2phy {
 222         struct device   *dev;
 223         struct regmap   *grf;
 224         struct clk      *clk;
 225         struct clk      *clk480m;
 226         struct clk_hw   clk480m_hw;
 227         enum usb_chg_state      chg_state;
 228         enum power_supply_type  chg_type;
 229         u8                      dcd_retries;
 230         u8                      primary_retries;
 231         struct extcon_dev       *edev;
 232         const struct rockchip_usb2phy_cfg       *phy_cfg;
 233         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 234 };
 235
 236 static inline int property_enable(struct rockchip_usb2phy *rphy,
 237                                   const struct usb2phy_reg *reg, bool en)
 238 {
 239         unsigned int val, mask, tmp;
 240
 241         tmp = en ? reg->enable : reg->disable;
 242         mask = GENMASK(reg->bitend, reg->bitstart);
 243         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 244
 245         return regmap_write(rphy->grf, reg->offset, val);
 246 }
 247
 248 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 249                                     const struct usb2phy_reg *reg)
 250 {
 251         int ret;
 252         unsigned int tmp, orig;
 253         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 254
 255         ret = regmap_read(rphy->grf, reg->offset, &orig);
 256         if (ret)
 257                 return false;
 258
 259         tmp = (orig & mask) >> reg->bitstart;
 260         return tmp == reg->enable;
 261 }
 262
 263 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
 264 {
 265         struct rockchip_usb2phy *rphy =
 266                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 267         int ret;
 268
 269         /* turn on 480m clk output if it is off */
 270         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 271                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 272                 if (ret)
 273                         return ret;
 274
 275                 /* waitting for the clk become stable */
 276                 udelay(1200);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
 283 {
 284         struct rockchip_usb2phy *rphy =
 285                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 286
 287         /* turn off 480m clk output */
 288         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 289 }
 290
 291 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
 292 {
 293         struct rockchip_usb2phy *rphy =
 294                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 295
 296         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 297 }
 298
 299 static unsigned long
 300 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 301                                      unsigned long parent_rate)
 302 {
 303         return 480000000;
 304 }
 305
 306 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 307         .enable = rockchip_usb2phy_clk480m_enable,
 308         .disable = rockchip_usb2phy_clk480m_disable,
 309         .is_enabled = rockchip_usb2phy_clk480m_enabled,
 310         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 311 };
 312
 313 static void rockchip_usb2phy_clk480m_unregister(void *data)
 314 {
 315         struct rockchip_usb2phy *rphy = data;
 316
 317         of_clk_del_provider(rphy->dev->of_node);
 318         clk_unregister(rphy->clk480m);
 319 }
 320
 321 static int
 322 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 323 {
 324         struct device_node *node = rphy->dev->of_node;
 325         struct clk_init_data init;
 326         const char *clk_name;
 327         int ret;
 328
 329         init.flags = 0;
 330         init.name = "clk_usbphy_480m";
 331         init.ops = &rockchip_usb2phy_clkout_ops;
 332
 333         /* optional override of the clockname */
 334         of_property_read_string(node, "clock-output-names", &init.name);
 335
 336         if (rphy->clk) {
 337                 clk_name = __clk_get_name(rphy->clk);
 338                 init.parent_names = &clk_name;
 339                 init.num_parents = 1;
 340         } else {
 341                 init.parent_names = NULL;
 342                 init.num_parents = 0;
 343         }
 344
 345         rphy->clk480m_hw.init = &init;
 346
 347         /* register the clock */
 348         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 349         if (IS_ERR(rphy->clk480m)) {
 350                 ret = PTR_ERR(rphy->clk480m);
 351                 goto err_ret;
 352         }
 353
 354         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 355         if (ret < 0)
 356                 goto err_clk_provider;
 357
 358         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 359                               rphy);
 360         if (ret < 0)
 361                 goto err_unreg_action;
 362
 363         return 0;
 364
 365 err_unreg_action:
 366         of_clk_del_provider(node);
 367 err_clk_provider:
 368         clk_unregister(rphy->clk480m);
 369 err_ret:
 370         return ret;
 371 }
 372
 373 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 374 {
 375         int ret;
 376         struct device_node *node = rphy->dev->of_node;
 377         struct extcon_dev *edev;
 378
 379         if (of_property_read_bool(node, "extcon")) {
 380                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 381                 if (IS_ERR(edev)) {
 382                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 383                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 384                         return PTR_ERR(edev);
 385                 }
 386         } else {
 387                 /* Initialize extcon device */
 388                 edev = devm_extcon_dev_allocate(rphy->dev,
 389                                                 rockchip_usb2phy_extcon_cable);
 390
 391                 if (IS_ERR(edev))
 392                         return -ENOMEM;
 393
 394                 ret = devm_extcon_dev_register(rphy->dev, edev);
 395                 if (ret) {
 396                         dev_err(rphy->dev, "failed to register extcon device\n");
 397                         return ret;
 398                 }
 399         }
 400
 401         rphy->edev = edev;
 402
 403         return 0;
 404 }
 405
 406 static int rockchip_usb2phy_init(struct phy *phy)
 407 {
 408         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 409         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 410         int ret;
 411
 412         mutex_lock(&rport->mutex);
 413
 414         if (rport->port_id == USB2PHY_PORT_OTG) {
 415                 /* clear bvalid status and enable bvalid detect irq */
 416                 ret = property_enable(rphy,
 417                                       &rport->port_cfg->bvalid_det_clr, true);
 418                 if (ret) {
 419                         mutex_unlock(&rport->mutex);
 420                         return ret;
 421                 }
 422
 423                 ret = property_enable(rphy,
 424                                       &rport->port_cfg->bvalid_det_en, true);
 425                 if (ret) {
 426                         mutex_unlock(&rport->mutex);
 427                         return ret;
 428                 }
 429
 430                 mutex_unlock(&rport->mutex);
 431                 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 432
 433         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 434                 /* clear linestate and enable linestate detect irq */
 435                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 436                 if (ret) {
 437                         mutex_unlock(&rport->mutex);
 438                         return ret;
 439                 }
 440
 441                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 442                 if (ret) {
 443                         mutex_unlock(&rport->mutex);
 444                         return ret;
 445                 }
 446
 447                 mutex_unlock(&rport->mutex);
 448                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int rockchip_usb2phy_power_on(struct phy *phy)
 455 {
 456         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 457         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 458         int ret;
 459
 460         dev_dbg(&rport->phy->dev, "port power on\n");
 461
 462         if (!rport->suspended)
 463                 return 0;
 464
 465         ret = clk_prepare_enable(rphy->clk480m);
 466         if (ret)
 467                 return ret;
 468
 469         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 470         if (ret)
 471                 return ret;
 472
 473         rport->suspended = false;
 474         return 0;
 475 }
 476
 477 static int rockchip_usb2phy_power_off(struct phy *phy)
 478 {
 479         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 480         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 481         int ret;
 482
 483         dev_dbg(&rport->phy->dev, "port power off\n");
 484
 485         if (rport->suspended)
 486                 return 0;
 487
 488         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 489         if (ret)
 490                 return ret;
 491
 492         rport->suspended = true;
 493         clk_disable_unprepare(rphy->clk480m);
 494
 495         return 0;
 496 }
 497
 498 static int rockchip_usb2phy_exit(struct phy *phy)
 499 {
 500         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 501
 502         if (rport->port_id == USB2PHY_PORT_OTG) {
 503                 cancel_delayed_work_sync(&rport->chg_work);
 504         } else if (rport->port_id == USB2PHY_PORT_HOST)
 505                 cancel_delayed_work_sync(&rport->sm_work);
 506
 507         return 0;
 508 }
 509
 510 static const struct phy_ops rockchip_usb2phy_ops = {
 511         .init           = rockchip_usb2phy_init,
 512         .exit           = rockchip_usb2phy_exit,
 513         .power_on       = rockchip_usb2phy_power_on,
 514         .power_off      = rockchip_usb2phy_power_off,
 515         .owner          = THIS_MODULE,
 516 };
 517
 518 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 519 {
 520         struct rockchip_usb2phy_port *rport =
 521                 container_of(work, struct rockchip_usb2phy_port,
 522                              otg_sm_work.work);
 523         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 524         static unsigned int cable;
 525         unsigned long delay;
 526         bool vbus_attach, sch_work, notify_charger;
 527
 528         if (rport->utmi_avalid)
 529                 vbus_attach =
 530                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 531         else
 532                 vbus_attach =
 533                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 534
 535         sch_work = false;
 536         notify_charger = false;
 537         delay = OTG_SCHEDULE_DELAY;
 538         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 539                 usb_otg_state_string(rport->state));
 540
 541         switch (rport->state) {
 542         case OTG_STATE_UNDEFINED:
 543                 rport->state = OTG_STATE_B_IDLE;
 544                 if (!vbus_attach)
 545                         rockchip_usb2phy_power_off(rport->phy);
 546                 /* fall through */
 547         case OTG_STATE_B_IDLE:
 548                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
 549                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 550                         rport->state = OTG_STATE_A_HOST;
 551                         rockchip_usb2phy_power_on(rport->phy);
 552                         return;
 553                 } else if (vbus_attach) {
 554                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 555                         switch (rphy->chg_state) {
 556                         case USB_CHG_STATE_UNDEFINED:
 557                                 schedule_delayed_work(&rport->chg_work, 0);
 558                                 return;
 559                         case USB_CHG_STATE_DETECTED:
 560                                 switch (rphy->chg_type) {
 561                                 case POWER_SUPPLY_TYPE_USB:
 562                                         dev_dbg(&rport->phy->dev,
 563                                                 "sdp cable is connecetd\n");
 564                                         wake_lock(&rport->wakelock);
 565                                         rockchip_usb2phy_power_on(rport->phy);
 566                                         rport->state = OTG_STATE_B_PERIPHERAL;
 567                                         notify_charger = true;
 568                                         sch_work = true;
 569                                         cable = EXTCON_CHG_USB_SDP;
 570                                         break;
 571                                 case POWER_SUPPLY_TYPE_USB_DCP:
 572                                         dev_dbg(&rport->phy->dev,
 573                                                 "dcp cable is connecetd\n");
 574                                         rockchip_usb2phy_power_off(rport->phy);
 575                                         notify_charger = true;
 576                                         sch_work = true;
 577                                         cable = EXTCON_CHG_USB_DCP;
 578                                         break;
 579                                 case POWER_SUPPLY_TYPE_USB_CDP:
 580                                         dev_dbg(&rport->phy->dev,
 581                                                 "cdp cable is connecetd\n");
 582                                         wake_lock(&rport->wakelock);
 583                                         rockchip_usb2phy_power_on(rport->phy);
 584                                         rport->state = OTG_STATE_B_PERIPHERAL;
 585                                         notify_charger = true;
 586                                         sch_work = true;
 587                                         cable = EXTCON_CHG_USB_CDP;
 588                                         break;
 589                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 590                                         dev_dbg(&rport->phy->dev,
 591                                                 "floating cable is connecetd\n");
 592                                         rockchip_usb2phy_power_off(rport->phy);
 593                                         notify_charger = true;
 594                                         sch_work = true;
 595                                         cable = EXTCON_CHG_USB_SLOW;
 596                                         break;
 597                                 default:
 598                                         break;
 599                                 }
 600                                 break;
 601                         default:
 602                                 break;
 603                         }
 604                 } else {
 605                         notify_charger = true;
 606                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 607                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 608                 }
 609
 610                 if (rport->vbus_attached != vbus_attach) {
 611                         rport->vbus_attached = vbus_attach;
 612
 613                         if (notify_charger && rphy->edev)
 614                                 extcon_set_cable_state_(rphy->edev,
 615                                                         cable, vbus_attach);
 616                 }
 617                 break;
 618         case OTG_STATE_B_PERIPHERAL:
 619                 if (!vbus_attach) {
 620                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 621                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 622                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 623                         rport->state = OTG_STATE_B_IDLE;
 624                         delay = 0;
 625                         rockchip_usb2phy_power_off(rport->phy);
 626                         wake_unlock(&rport->wakelock);
 627                 }
 628                 sch_work = true;
 629                 break;
 630         case OTG_STATE_A_HOST:
 631                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 632                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 633                         rport->state = OTG_STATE_B_IDLE;
 634                         rockchip_usb2phy_power_off(rport->phy);
 635                 }
 636                 break;
 637         default:
 638                 break;
 639         }
 640
 641         if (sch_work)
 642                 schedule_delayed_work(&rport->otg_sm_work, delay);
 643 }
 644
 645 static const char *chg_to_string(enum power_supply_type chg_type)
 646 {
 647         switch (chg_type) {
 648         case POWER_SUPPLY_TYPE_USB:
 649                 return "USB_SDP_CHARGER";
 650         case POWER_SUPPLY_TYPE_USB_DCP:
 651                 return "USB_DCP_CHARGER";
 652         case POWER_SUPPLY_TYPE_USB_CDP:
 653                 return "USB_CDP_CHARGER";
 654         case POWER_SUPPLY_TYPE_USB_FLOATING:
 655                 return "USB_FLOATING_CHARGER";
 656         default:
 657                 return "INVALID_CHARGER";
 658         }
 659 }
 660
 661 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 662                                     bool en)
 663 {
 664         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 665         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 666 }
 667
 668 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 669                                             bool en)
 670 {
 671         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 672         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 673 }
 674
 675 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 676                                               bool en)
 677 {
 678         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 679         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 680 }
 681
 682 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 683 #define CHG_DCD_MAX_RETRIES     6
 684 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 685 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 686 static void rockchip_chg_detect_work(struct work_struct *work)
 687 {
 688         struct rockchip_usb2phy_port *rport =
 689                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 690         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 691         bool is_dcd, tmout, vout;
 692         unsigned long delay;
 693
 694         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 695                 rphy->chg_state);
 696         switch (rphy->chg_state) {
 697         case USB_CHG_STATE_UNDEFINED:
 698                 if (!rport->suspended)
 699                         rockchip_usb2phy_power_off(rport->phy);
 700                 /* put the controller in non-driving mode */
 701                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 702                 /* Start DCD processing stage 1 */
 703                 rockchip_chg_enable_dcd(rphy, true);
 704                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 705                 rphy->dcd_retries = 0;
 706                 rphy->primary_retries = 0;
 707                 delay = CHG_DCD_POLL_TIME;
 708                 break;
 709         case USB_CHG_STATE_WAIT_FOR_DCD:
 710                 /* get data contact detection status */
 711                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 712                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 713                 /* stage 2 */
 714                 if (is_dcd || tmout) {
 715                         /* stage 4 */
 716                         /* Turn off DCD circuitry */
 717                         rockchip_chg_enable_dcd(rphy, false);
 718                         /* Voltage Source on DP, Probe on DM */
 719                         rockchip_chg_enable_primary_det(rphy, true);
 720                         delay = CHG_PRIMARY_DET_TIME;
 721                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 722                 } else {
 723                         /* stage 3 */
 724                         delay = CHG_DCD_POLL_TIME;
 725                 }
 726                 break;
 727         case USB_CHG_STATE_DCD_DONE:
 728                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 729                 rockchip_chg_enable_primary_det(rphy, false);
 730                 if (vout) {
 731                         /* Voltage Source on DM, Probe on DP  */
 732                         rockchip_chg_enable_secondary_det(rphy, true);
 733                         delay = CHG_SECONDARY_DET_TIME;
 734                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 735                 } else {
 736                         if (tmout) {
 737                                 /* floating charger found */
 738                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 739                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 740                                 delay = 0;
 741                         } else {
 742                                 if (rphy->primary_retries < 2) {
 743                                         /* Turn off DCD circuitry */
 744                                         rockchip_chg_enable_dcd(rphy, false);
 745                                         /* Voltage Source on DP, Probe on DM */
 746                                         rockchip_chg_enable_primary_det(rphy,
 747                                                                         true);
 748                                         delay = CHG_PRIMARY_DET_TIME;
 749                                         rphy->chg_state =
 750                                                 USB_CHG_STATE_DCD_DONE;
 751                                         rphy->primary_retries++;
 752                                         /* break USB_CHG_STATE_DCD_DONE */
 753                                         break;
 754                                 }
 755                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 756                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 757                                 delay = 0;
 758                         }
 759                 }
 760                 break;
 761         case USB_CHG_STATE_PRIMARY_DONE:
 762                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 763                 /* Turn off voltage source */
 764                 rockchip_chg_enable_secondary_det(rphy, false);
 765                 if (vout)
 766                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 767                 else
 768                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 769                 /* fall through */
 770         case USB_CHG_STATE_SECONDARY_DONE:
 771                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 772                 delay = 0;
 773                 /* fall through */
 774         case USB_CHG_STATE_DETECTED:
 775                 /* put the controller in normal mode */
 776                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 777                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 778                 dev_info(&rport->phy->dev, "charger = %s\n",
 779                          chg_to_string(rphy->chg_type));
 780                 return;
 781         default:
 782                 return;
 783         }
 784
 785         schedule_delayed_work(&rport->chg_work, delay);
 786 }
 787
 788 /*
 789  * The function manage host-phy port state and suspend/resume phy port
 790  * to save power.
 791  *
 792  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 793  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 794  * disconnected or HS disconnected, actually, we just only need get the
 795  * device is disconnected at last through rearm the delayed work,
 796  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 797  *
 798  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 799  * some clk related APIs, so do not invoke it from interrupt context directly.
 800  */
 801 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 802 {
 803         struct rockchip_usb2phy_port *rport =
 804                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 805         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 806         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 807                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 808         unsigned int ul, uhd, state;
 809         unsigned int ul_mask, uhd_mask;
 810         int ret;
 811
 812         mutex_lock(&rport->mutex);
 813
 814         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 815         if (ret < 0)
 816                 goto next_schedule;
 817
 818         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 819                           &uhd);
 820         if (ret < 0)
 821                 goto next_schedule;
 822
 823         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 824                            rport->port_cfg->utmi_hstdet.bitstart);
 825         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 826                           rport->port_cfg->utmi_ls.bitstart);
 827
 828         /* stitch on utmi_ls and utmi_hstdet as phy state */
 829         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 830                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 831
 832         switch (state) {
 833         case PHY_STATE_HS_ONLINE:
 834                 dev_dbg(&rport->phy->dev, "HS online\n");
 835                 break;
 836         case PHY_STATE_FS_LS_ONLINE:
 837                 /*
 838                  * For FS/LS device, the online state share with connect state
 839                  * from utmi_ls and utmi_hstdet register, so we distinguish
 840                  * them via suspended flag.
 841                  *
 842                  * Plus, there are two cases, one is D- Line pull-up, and D+
 843                  * line pull-down, the state is 4; another is D+ line pull-up,
 844                  * and D- line pull-down, the state is 2.
 845                  */
 846                 if (!rport->suspended) {
 847                         /* D- line pull-up, D+ line pull-down */
 848                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 849                         break;
 850                 }
 851                 /* fall through */
 852         case PHY_STATE_CONNECT:
 853                 if (rport->suspended) {
 854                         dev_dbg(&rport->phy->dev, "Connected\n");
 855                         rockchip_usb2phy_power_on(rport->phy);
 856                         rport->suspended = false;
 857                 } else {
 858                         /* D+ line pull-up, D- line pull-down */
 859                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 860                 }
 861                 break;
 862         case PHY_STATE_DISCONNECT:
 863                 if (!rport->suspended) {
 864                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 865                         rockchip_usb2phy_power_off(rport->phy);
 866                         rport->suspended = true;
 867                 }
 868
 869                 /*
 870                  * activate the linestate detection to get the next device
 871                  * plug-in irq.
 872                  */
 873                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 874                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 875
 876                 /*
 877                  * we don't need to rearm the delayed work when the phy port
 878                  * is suspended.
 879                  */
 880                 mutex_unlock(&rport->mutex);
 881                 return;
 882         default:
 883                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 884                 break;
 885         }
 886
 887 next_schedule:
 888         mutex_unlock(&rport->mutex);
 889         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 890 }
 891
 892 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 893 {
 894         struct rockchip_usb2phy_port *rport = data;
 895         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 896
 897         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 898                 return IRQ_NONE;
 899
 900         mutex_lock(&rport->mutex);
 901
 902         /* disable linestate detect irq and clear its status */
 903         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 904         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 905
 906         mutex_unlock(&rport->mutex);
 907
 908         /*
 909          * In this case for host phy port, a new device is plugged in,
 910          * meanwhile, if the phy port is suspended, we need rearm the work to
 911          * resume it and mange its states; otherwise, we do nothing about that.
 912          */
 913         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 914                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 915
 916         return IRQ_HANDLED;
 917 }
 918
 919 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 920 {
 921         struct rockchip_usb2phy_port *rport = data;
 922         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 923
 924         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 925                 return IRQ_NONE;
 926
 927         mutex_lock(&rport->mutex);
 928
 929         /* clear bvalid detect irq pending status */
 930         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 931
 932         mutex_unlock(&rport->mutex);
 933
 934         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 935
 936         return IRQ_HANDLED;
 937 }
 938
 939 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
 940                                            struct rockchip_usb2phy_port *rport,
 941                                            struct device_node *child_np)
 942 {
 943         int ret;
 944
 945         rport->port_id = USB2PHY_PORT_HOST;
 946         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
 947         rport->suspended = true;
 948
 949         mutex_init(&rport->mutex);
 950         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
 951
 952         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 953         if (rport->ls_irq < 0) {
 954                 dev_err(rphy->dev, "no linestate irq provided\n");
 955                 return rport->ls_irq;
 956         }
 957
 958         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 959                                         rockchip_usb2phy_linestate_irq,
 960                                         IRQF_ONESHOT,
 961                                         "rockchip_usb2phy", rport);
 962         if (ret) {
 963                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
 964                 return ret;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int rockchip_otg_event(struct notifier_block *nb,
 971                               unsigned long event, void *ptr)
 972 {
 973         struct rockchip_usb2phy_port *rport =
 974                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
 975
 976         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 977
 978         return NOTIFY_DONE;
 979 }
 980
 981 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 982                                           struct rockchip_usb2phy_port *rport,
 983                                           struct device_node *child_np)
 984 {
 985         int ret;
 986
 987         rport->port_id = USB2PHY_PORT_OTG;
 988         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
 989         rport->state = OTG_STATE_UNDEFINED;
 990         /*
 991          * set suspended flag to true, but actually don't
 992          * put phy in suspend mode, it aims to enable usb
 993          * phy and clock in power_on() called by usb controller
 994          * driver during probe.
 995          */
 996         rport->suspended = true;
 997         rport->vbus_attached = false;
 998
 999         mutex_init(&rport->mutex);
1000         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1001         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1002         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1003
1004         rport->utmi_avalid =
1005                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1006
1007         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1008         if (rport->bvalid_irq < 0) {
1009                 dev_err(rphy->dev, "no vbus valid irq provided\n");
1010                 return rport->bvalid_irq;
1011         }
1012
1013         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1014                                         rockchip_usb2phy_bvalid_irq,
1015                                         IRQF_ONESHOT,
1016                                         "rockchip_usb2phy_bvalid", rport);
1017         if (ret) {
1018                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1019                 return ret;
1020         }
1021
1022         if (!IS_ERR(rphy->edev)) {
1023                 rport->event_nb.notifier_call = rockchip_otg_event;
1024
1025                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1026                                                &rport->event_nb);
1027                 if (ret < 0) {
1028                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1029                         return ret;
1030                 }
1031         }
1032
1033         return 0;
1034 }
1035
1036 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1037 {
1038         struct device *dev = &pdev->dev;
1039         struct device_node *np = dev->of_node;
1040         struct device_node *child_np;
1041         struct phy_provider *provider;
1042         struct rockchip_usb2phy *rphy;
1043         const struct rockchip_usb2phy_cfg *phy_cfgs;
1044         const struct of_device_id *match;
1045         unsigned int reg;
1046         int index, ret;
1047
1048         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1049         if (!rphy)
1050                 return -ENOMEM;
1051
1052         match = of_match_device(dev->driver->of_match_table, dev);
1053         if (!match || !match->data) {
1054                 dev_err(dev, "phy configs are not assigned!\n");
1055                 return -EINVAL;
1056         }
1057
1058         if (!dev->parent || !dev->parent->of_node)
1059                 return -EINVAL;
1060
1061         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1062         if (IS_ERR(rphy->grf))
1063                 return PTR_ERR(rphy->grf);
1064
1065         if (of_property_read_u32(np, "reg", &reg)) {
1066                 dev_err(dev, "the reg property is not assigned in %s node\n",
1067                         np->name);
1068                 return -EINVAL;
1069         }
1070
1071         rphy->dev = dev;
1072         phy_cfgs = match->data;
1073         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1074         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1075         platform_set_drvdata(pdev, rphy);
1076
1077         ret = rockchip_usb2phy_extcon_register(rphy);
1078         if (ret)
1079                 return ret;
1080
1081         /* find out a proper config which can be matched with dt. */
1082         index = 0;
1083         while (phy_cfgs[index].reg) {
1084                 if (phy_cfgs[index].reg == reg) {
1085                         rphy->phy_cfg = &phy_cfgs[index];
1086                         break;
1087                 }
1088
1089                 ++index;
1090         }
1091
1092         if (!rphy->phy_cfg) {
1093                 dev_err(dev, "no phy-config can be matched with %s node\n",
1094                         np->name);
1095                 return -EINVAL;
1096         }
1097
1098         rphy->clk = of_clk_get_by_name(np, "phyclk");
1099         if (!IS_ERR(rphy->clk)) {
1100                 clk_prepare_enable(rphy->clk);
1101         } else {
1102                 dev_info(&pdev->dev, "no phyclk specified\n");
1103                 rphy->clk = NULL;
1104         }
1105
1106         ret = rockchip_usb2phy_clk480m_register(rphy);
1107         if (ret) {
1108                 dev_err(dev, "failed to register 480m output clock\n");
1109                 goto disable_clks;
1110         }
1111
1112         if (rphy->phy_cfg->phy_tuning) {
1113                 ret = rphy->phy_cfg->phy_tuning(rphy);
1114                 if (ret)
1115                         goto disable_clks;
1116         }
1117
1118         index = 0;
1119         for_each_available_child_of_node(np, child_np) {
1120                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1121                 struct phy *phy;
1122
1123                 /* This driver aims to support both otg-port and host-port */
1124                 if (of_node_cmp(child_np->name, "host-port") &&
1125                     of_node_cmp(child_np->name, "otg-port"))
1126                         goto next_child;
1127
1128                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1129                 if (IS_ERR(phy)) {
1130                         dev_err(dev, "failed to create phy\n");
1131                         ret = PTR_ERR(phy);
1132                         goto put_child;
1133                 }
1134
1135                 rport->phy = phy;
1136                 phy_set_drvdata(rport->phy, rport);
1137
1138                 /* initialize otg/host port separately */
1139                 if (!of_node_cmp(child_np->name, "host-port")) {
1140                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1141                                                               child_np);
1142                         if (ret)
1143                                 goto put_child;
1144                 } else {
1145                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1146                                                              child_np);
1147                         if (ret)
1148                                 goto put_child;
1149                 }
1150
1151 next_child:
1152                 /* to prevent out of boundary */
1153                 if (++index >= rphy->phy_cfg->num_ports)
1154                         break;
1155         }
1156
1157         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1158         return PTR_ERR_OR_ZERO(provider);
1159
1160 put_child:
1161         of_node_put(child_np);
1162 disable_clks:
1163         if (rphy->clk) {
1164                 clk_disable_unprepare(rphy->clk);
1165                 clk_put(rphy->clk);
1166         }
1167         return ret;
1168 }
1169
1170 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1171 {
1172         unsigned int open_pre_emphasize = 0xffff851f;
1173         unsigned int eye_height_tuning = 0xffff68c8;
1174         unsigned int compensation_tuning = 0xffff026e;
1175         int ret = 0;
1176
1177         /* open HS pre-emphasize to expand HS slew rate for each port. */
1178         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1179         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1180         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1181         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1182
1183         /* compensate default tuning reference relate to ODT and etc. */
1184         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1185
1186         return ret;
1187 }
1188
1189 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1190         {
1191                 .reg = 0x700,
1192                 .num_ports      = 2,
1193                 .phy_tuning     = rk3366_usb2phy_tuning,
1194                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1195                 .port_cfgs      = {
1196                         [USB2PHY_PORT_HOST] = {
1197                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1198                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1199                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1200                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1201                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1202                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1203                         }
1204                 },
1205         },
1206         { /* sentinel */ }
1207 };
1208
1209 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1210         {
1211                 .reg            = 0xe450,
1212                 .num_ports      = 2,
1213                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1214                 .port_cfgs      = {
1215                         [USB2PHY_PORT_OTG] = {
1216                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1217                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1218                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1219                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1220                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1221                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1222                         },
1223                         [USB2PHY_PORT_HOST] = {
1224                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1225                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1226                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1227                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1228                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1229                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1230                         }
1231                 },
1232                 .chg_det = {
1233                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1234                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1235                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1236                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1237                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1238                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1239                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1240                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1241                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1242                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1243                 },
1244         },
1245         {
1246                 .reg            = 0xe460,
1247                 .num_ports      = 2,
1248                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1249                 .port_cfgs      = {
1250                         [USB2PHY_PORT_OTG] = {
1251                                 .phy_sus        = { 0xe464, 1, 0, 2, 1 },
1252                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1253                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1254                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1255                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1256                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1257                         },
1258                         [USB2PHY_PORT_HOST] = {
1259                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1260                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1261                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1262                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1263                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1264                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1265                         }
1266                 },
1267         },
1268         { /* sentinel */ }
1269 };
1270
1271 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1272         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1273         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1274         {}
1275 };
1276 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1277
1278 static struct platform_driver rockchip_usb2phy_driver = {
1279         .probe          = rockchip_usb2phy_probe,
1280         .driver         = {
1281                 .name   = "rockchip-usb2phy",
1282                 .of_match_table = rockchip_usb2phy_dt_match,
1283         },
1284 };
1285 module_platform_driver(rockchip_usb2phy_driver);
1286
1287 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1288 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1289 MODULE_LICENSE("GPL v2");