2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
57 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
58 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
59 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
60 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
61 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
62 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
63 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
64 #define PCIE_CLIENT_INTR_SHIFT 5
65 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
66 #define PCIE_CLIENT_INT_MSG BIT(14)
67 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
68 #define PCIE_CLIENT_INT_DPA BIT(12)
69 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
70 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
71 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
72 #define PCIE_CLIENT_INT_INTD BIT(8)
73 #define PCIE_CLIENT_INT_INTC BIT(7)
74 #define PCIE_CLIENT_INT_INTB BIT(6)
75 #define PCIE_CLIENT_INT_INTA BIT(5)
76 #define PCIE_CLIENT_INT_LOCAL BIT(4)
77 #define PCIE_CLIENT_INT_UDMA BIT(3)
78 #define PCIE_CLIENT_INT_PHY BIT(2)
79 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
80 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
82 #define PCIE_CLIENT_INT_LEGACY \
83 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
84 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
86 #define PCIE_CLIENT_INT_CLI \
87 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
88 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
89 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
90 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
93 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
94 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
95 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
96 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
97 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
98 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
99 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
100 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
101 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
102 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
103 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
106 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
107 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
108 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
109 #define PCIE_CORE_INT_PRFPE BIT(0)
110 #define PCIE_CORE_INT_CRFPE BIT(1)
111 #define PCIE_CORE_INT_RRPE BIT(2)
112 #define PCIE_CORE_INT_PRFO BIT(3)
113 #define PCIE_CORE_INT_CRFO BIT(4)
114 #define PCIE_CORE_INT_RT BIT(5)
115 #define PCIE_CORE_INT_RTR BIT(6)
116 #define PCIE_CORE_INT_PE BIT(7)
117 #define PCIE_CORE_INT_MTR BIT(8)
118 #define PCIE_CORE_INT_UCR BIT(9)
119 #define PCIE_CORE_INT_FCE BIT(10)
120 #define PCIE_CORE_INT_CT BIT(11)
121 #define PCIE_CORE_INT_UTC BIT(18)
122 #define PCIE_CORE_INT_MMVC BIT(19)
123 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
124 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
126 #define PCIE_CORE_INT \
127 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
128 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
129 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
130 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
131 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
132 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
135 #define PCIE_RC_CONFIG_BASE 0xa00000
136 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
137 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
138 #define PCIE_RC_CONFIG_SCC_SHIFT 16
139 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
140 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
141 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
142 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
143 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
144 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
145 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
146 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
148 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
149 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
150 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
151 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
152 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
153 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
154 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
156 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
157 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
158 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
159 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
160 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
162 /* Size of one AXI Region (not Region 0) */
163 #define AXI_REGION_SIZE BIT(20)
164 /* Size of Region 0, equal to sum of sizes of other regions */
165 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
166 #define OB_REG_SIZE_SHIFT 5
167 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
168 #define AXI_WRAPPER_IO_WRITE 0x6
169 #define AXI_WRAPPER_MEM_WRITE 0x2
171 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
172 #define MIN_AXI_ADDR_BITS_PASSED 8
173 #define ROCKCHIP_VENDOR_ID 0x1d87
174 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
175 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
176 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
177 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
178 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
179 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
180 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
182 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
183 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
184 #define RC_REGION_0_PASS_BITS (25 - 1)
185 #define MAX_AXI_WRAPPER_REGION_NUM 33
187 struct rockchip_pcie {
188 void __iomem *reg_base; /* DT axi-base */
189 void __iomem *apb_base; /* DT apb-base */
191 struct reset_control *core_rst;
192 struct reset_control *mgmt_rst;
193 struct reset_control *mgmt_sticky_rst;
194 struct reset_control *pipe_rst;
195 struct reset_control *pm_rst;
196 struct reset_control *aclk_rst;
197 struct reset_control *pclk_rst;
198 struct clk *aclk_pcie;
199 struct clk *aclk_perf_pcie;
200 struct clk *hclk_pcie;
201 struct clk *clk_pcie_pm;
202 struct regulator *vpcie3v3; /* 3.3V power supply */
203 struct regulator *vpcie1v8; /* 1.8V power supply */
204 struct regulator *vpcie0v9; /* 0.9V power supply */
205 struct gpio_desc *ep_gpio;
210 struct irq_domain *irq_domain;
213 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
215 return readl(rockchip->apb_base + reg);
218 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
221 writel(val, rockchip->apb_base + reg);
224 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
228 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
229 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
230 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
233 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
237 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
238 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
239 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
242 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
246 /* Update Tx credit maximum update interval */
247 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
248 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
249 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
250 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
253 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
254 struct pci_bus *bus, int dev)
256 /* access only one slot on each root port */
257 if (bus->number == rockchip->root_bus_nr && dev > 0)
261 * do not read more than one device on the bus directly attached
262 * to RC's downstream side.
264 if (bus->primary == rockchip->root_bus_nr && dev > 0)
270 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
271 int where, int size, u32 *val)
273 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
275 if (!IS_ALIGNED((uintptr_t)addr, size)) {
277 return PCIBIOS_BAD_REGISTER_NUMBER;
282 } else if (size == 2) {
284 } else if (size == 1) {
288 return PCIBIOS_BAD_REGISTER_NUMBER;
290 return PCIBIOS_SUCCESSFUL;
293 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
294 int where, int size, u32 val)
296 u32 mask, tmp, offset;
298 offset = where & ~0x3;
301 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
302 return PCIBIOS_SUCCESSFUL;
305 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
308 * N.B. This read/modify/write isn't safe in general because it can
309 * corrupt RW1C bits in adjacent registers. But the hardware
310 * doesn't support smaller writes.
312 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
313 tmp |= val << ((where & 0x3) * 8);
314 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
316 return PCIBIOS_SUCCESSFUL;
319 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
320 struct pci_bus *bus, u32 devfn,
321 int where, int size, u32 *val)
325 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
326 PCI_FUNC(devfn), where);
328 if (!IS_ALIGNED(busdev, size)) {
330 return PCIBIOS_BAD_REGISTER_NUMBER;
334 *val = readl(rockchip->reg_base + busdev);
335 } else if (size == 2) {
336 *val = readw(rockchip->reg_base + busdev);
337 } else if (size == 1) {
338 *val = readb(rockchip->reg_base + busdev);
341 return PCIBIOS_BAD_REGISTER_NUMBER;
343 return PCIBIOS_SUCCESSFUL;
346 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
347 struct pci_bus *bus, u32 devfn,
348 int where, int size, u32 val)
352 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
353 PCI_FUNC(devfn), where);
354 if (!IS_ALIGNED(busdev, size))
355 return PCIBIOS_BAD_REGISTER_NUMBER;
358 writel(val, rockchip->reg_base + busdev);
360 writew(val, rockchip->reg_base + busdev);
362 writeb(val, rockchip->reg_base + busdev);
364 return PCIBIOS_BAD_REGISTER_NUMBER;
366 return PCIBIOS_SUCCESSFUL;
369 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
372 struct rockchip_pcie *rockchip = bus->sysdata;
374 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
376 return PCIBIOS_DEVICE_NOT_FOUND;
379 if (bus->number == rockchip->root_bus_nr)
380 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
382 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
385 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
386 int where, int size, u32 val)
388 struct rockchip_pcie *rockchip = bus->sysdata;
390 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
391 return PCIBIOS_DEVICE_NOT_FOUND;
393 if (bus->number == rockchip->root_bus_nr)
394 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
396 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
399 static struct pci_ops rockchip_pcie_ops = {
400 .read = rockchip_pcie_rd_conf,
401 .write = rockchip_pcie_wr_conf,
404 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
406 u32 status, curr, scale, power;
408 if (IS_ERR(rockchip->vpcie3v3))
412 * Set RC's captured slot power limit and scale if
413 * vpcie3v3 available. The default values are both zero
414 * which means the software should set these two according
415 * to the actual power supply.
417 curr = regulator_get_current_limit(rockchip->vpcie3v3);
419 scale = 3; /* 0.001x */
420 curr = curr / 1000; /* convert to mA */
421 power = (curr * 3300) / 1000; /* milliwatt */
422 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
424 dev_warn(rockchip->dev, "invalid power supply\n");
431 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
432 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
433 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
434 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
439 * rockchip_pcie_init_port - Initialize hardware
440 * @rockchip: PCIe port information
442 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
444 struct device *dev = rockchip->dev;
447 unsigned long timeout;
449 gpiod_set_value(rockchip->ep_gpio, 0);
451 err = reset_control_assert(rockchip->aclk_rst);
453 dev_err(dev, "assert aclk_rst err %d\n", err);
457 err = reset_control_assert(rockchip->pclk_rst);
459 dev_err(dev, "assert pclk_rst err %d\n", err);
463 err = reset_control_assert(rockchip->pm_rst);
465 dev_err(dev, "assert pm_rst err %d\n", err);
471 err = reset_control_deassert(rockchip->pm_rst);
473 dev_err(dev, "deassert pm_rst err %d\n", err);
477 err = reset_control_deassert(rockchip->aclk_rst);
479 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
483 err = reset_control_deassert(rockchip->pclk_rst);
485 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
489 err = phy_init(rockchip->phy);
491 dev_err(dev, "fail to init phy, err %d\n", err);
495 err = reset_control_assert(rockchip->core_rst);
497 dev_err(dev, "assert core_rst err %d\n", err);
501 err = reset_control_assert(rockchip->mgmt_rst);
503 dev_err(dev, "assert mgmt_rst err %d\n", err);
507 err = reset_control_assert(rockchip->mgmt_sticky_rst);
509 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
513 err = reset_control_assert(rockchip->pipe_rst);
515 dev_err(dev, "assert pipe_rst err %d\n", err);
519 if (rockchip->link_gen == 2)
520 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
523 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
526 rockchip_pcie_write(rockchip,
527 PCIE_CLIENT_CONF_ENABLE |
528 PCIE_CLIENT_LINK_TRAIN_ENABLE |
529 PCIE_CLIENT_ARI_ENABLE |
530 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
534 err = phy_power_on(rockchip->phy);
536 dev_err(dev, "fail to power on phy, err %d\n", err);
541 * Please don't reorder the deassert sequence of the following
544 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
546 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
550 err = reset_control_deassert(rockchip->core_rst);
552 dev_err(dev, "deassert core_rst err %d\n", err);
556 err = reset_control_deassert(rockchip->mgmt_rst);
558 dev_err(dev, "deassert mgmt_rst err %d\n", err);
562 err = reset_control_deassert(rockchip->pipe_rst);
564 dev_err(dev, "deassert pipe_rst err %d\n", err);
568 /* Fix the transmitted FTS count desired to exit from L0s. */
569 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
570 status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
571 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
572 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
574 rockchip_pcie_set_power_limit(rockchip);
576 /* Set RC's clock architecture as common clock */
577 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
578 status |= PCI_EXP_LNKCTL_CCC;
579 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
581 /* Enable Gen1 training */
582 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
585 gpiod_set_value(rockchip->ep_gpio, 1);
587 /* 500ms timeout value should be enough for Gen1/2 training */
588 timeout = jiffies + msecs_to_jiffies(500);
591 status = rockchip_pcie_read(rockchip,
592 PCIE_CLIENT_BASIC_STATUS1);
593 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
594 PCIE_CLIENT_LINK_STATUS_UP) {
595 dev_dbg(dev, "PCIe link training gen1 pass!\n");
599 if (time_after(jiffies, timeout)) {
600 dev_err(dev, "PCIe link training gen1 timeout!\n");
607 if (rockchip->link_gen == 2) {
609 * Enable retrain for gen2. This should be configured only after
612 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
613 status |= PCI_EXP_LNKCTL_RL;
614 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
616 timeout = jiffies + msecs_to_jiffies(500);
618 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
619 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
620 PCIE_CORE_PL_CONF_SPEED_5G) {
621 dev_dbg(dev, "PCIe link training gen2 pass!\n");
625 if (time_after(jiffies, timeout)) {
626 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
634 /* Check the final link width from negotiated lane counter from MGMT */
635 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
636 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
637 PCIE_CORE_PL_CONF_LANE_SHIFT);
638 dev_dbg(dev, "current link width is x%d\n", status);
640 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
641 PCIE_RC_CONFIG_VENDOR);
642 rockchip_pcie_write(rockchip,
643 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
644 PCIE_RC_CONFIG_RID_CCR);
646 /* Clear THP cap's next cap pointer to remove L1 substate cap */
647 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
648 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
649 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
651 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
653 rockchip_pcie_write(rockchip,
654 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
655 PCIE_CORE_OB_REGION_ADDR0);
656 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
657 PCIE_CORE_OB_REGION_ADDR1);
658 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
659 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
664 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
666 struct rockchip_pcie *rockchip = arg;
667 struct device *dev = rockchip->dev;
671 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
672 if (reg & PCIE_CLIENT_INT_LOCAL) {
673 dev_dbg(dev, "local interrupt received\n");
674 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
675 if (sub_reg & PCIE_CORE_INT_PRFPE)
676 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
678 if (sub_reg & PCIE_CORE_INT_CRFPE)
679 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
681 if (sub_reg & PCIE_CORE_INT_RRPE)
682 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
684 if (sub_reg & PCIE_CORE_INT_PRFO)
685 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
687 if (sub_reg & PCIE_CORE_INT_CRFO)
688 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
690 if (sub_reg & PCIE_CORE_INT_RT)
691 dev_dbg(dev, "replay timer timed out\n");
693 if (sub_reg & PCIE_CORE_INT_RTR)
694 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
696 if (sub_reg & PCIE_CORE_INT_PE)
697 dev_dbg(dev, "phy error detected on receive side\n");
699 if (sub_reg & PCIE_CORE_INT_MTR)
700 dev_dbg(dev, "malformed TLP received from the link\n");
702 if (sub_reg & PCIE_CORE_INT_UCR)
703 dev_dbg(dev, "malformed TLP received from the link\n");
705 if (sub_reg & PCIE_CORE_INT_FCE)
706 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
708 if (sub_reg & PCIE_CORE_INT_CT)
709 dev_dbg(dev, "a request timed out waiting for completion\n");
711 if (sub_reg & PCIE_CORE_INT_UTC)
712 dev_dbg(dev, "unmapped TC error\n");
714 if (sub_reg & PCIE_CORE_INT_MMVC)
715 dev_dbg(dev, "MSI mask register changes\n");
717 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
718 } else if (reg & PCIE_CLIENT_INT_PHY) {
719 dev_dbg(dev, "phy link changes\n");
720 rockchip_pcie_update_txcredit_mui(rockchip);
721 rockchip_pcie_clr_bw_int(rockchip);
724 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
725 PCIE_CLIENT_INT_STATUS);
730 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
732 struct rockchip_pcie *rockchip = arg;
733 struct device *dev = rockchip->dev;
736 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
737 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
738 dev_dbg(dev, "legacy done interrupt received\n");
740 if (reg & PCIE_CLIENT_INT_MSG)
741 dev_dbg(dev, "message done interrupt received\n");
743 if (reg & PCIE_CLIENT_INT_HOT_RST)
744 dev_dbg(dev, "hot reset interrupt received\n");
746 if (reg & PCIE_CLIENT_INT_DPA)
747 dev_dbg(dev, "dpa interrupt received\n");
749 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
750 dev_dbg(dev, "fatal error interrupt received\n");
752 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
753 dev_dbg(dev, "no fatal error interrupt received\n");
755 if (reg & PCIE_CLIENT_INT_CORR_ERR)
756 dev_dbg(dev, "correctable error interrupt received\n");
758 if (reg & PCIE_CLIENT_INT_PHY)
759 dev_dbg(dev, "phy interrupt received\n");
761 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
762 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
763 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
764 PCIE_CLIENT_INT_NFATAL_ERR |
765 PCIE_CLIENT_INT_CORR_ERR |
766 PCIE_CLIENT_INT_PHY),
767 PCIE_CLIENT_INT_STATUS);
772 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
774 struct irq_chip *chip = irq_desc_get_chip(desc);
775 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
776 struct device *dev = rockchip->dev;
781 chained_irq_enter(chip, desc);
783 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
784 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
787 hwirq = ffs(reg) - 1;
790 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
792 generic_handle_irq(virq);
794 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
797 chained_irq_exit(chip, desc);
802 * rockchip_pcie_parse_dt - Parse Device Tree
803 * @rockchip: PCIe port information
805 * Return: '0' on success and error value on failure
807 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
809 struct device *dev = rockchip->dev;
810 struct platform_device *pdev = to_platform_device(dev);
811 struct device_node *node = dev->of_node;
812 struct resource *regs;
816 regs = platform_get_resource_byname(pdev,
819 rockchip->reg_base = devm_ioremap_resource(dev, regs);
820 if (IS_ERR(rockchip->reg_base))
821 return PTR_ERR(rockchip->reg_base);
823 regs = platform_get_resource_byname(pdev,
826 rockchip->apb_base = devm_ioremap_resource(dev, regs);
827 if (IS_ERR(rockchip->apb_base))
828 return PTR_ERR(rockchip->apb_base);
830 rockchip->phy = devm_phy_get(dev, "pcie-phy");
831 if (IS_ERR(rockchip->phy)) {
832 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
833 dev_err(dev, "missing phy\n");
834 return PTR_ERR(rockchip->phy);
838 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
839 if (!err && (rockchip->lanes == 0 ||
840 rockchip->lanes == 3 ||
841 rockchip->lanes > 4)) {
842 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
846 rockchip->link_gen = of_pci_get_max_link_speed(node);
847 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
848 rockchip->link_gen = 2;
850 rockchip->core_rst = devm_reset_control_get(dev, "core");
851 if (IS_ERR(rockchip->core_rst)) {
852 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
853 dev_err(dev, "missing core reset property in node\n");
854 return PTR_ERR(rockchip->core_rst);
857 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
858 if (IS_ERR(rockchip->mgmt_rst)) {
859 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
860 dev_err(dev, "missing mgmt reset property in node\n");
861 return PTR_ERR(rockchip->mgmt_rst);
864 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
865 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
866 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
867 dev_err(dev, "missing mgmt-sticky reset property in node\n");
868 return PTR_ERR(rockchip->mgmt_sticky_rst);
871 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
872 if (IS_ERR(rockchip->pipe_rst)) {
873 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
874 dev_err(dev, "missing pipe reset property in node\n");
875 return PTR_ERR(rockchip->pipe_rst);
878 rockchip->pm_rst = devm_reset_control_get(dev, "pm");
879 if (IS_ERR(rockchip->pm_rst)) {
880 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
881 dev_err(dev, "missing pm reset property in node\n");
882 return PTR_ERR(rockchip->pm_rst);
885 rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
886 if (IS_ERR(rockchip->pclk_rst)) {
887 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
888 dev_err(dev, "missing pclk reset property in node\n");
889 return PTR_ERR(rockchip->pclk_rst);
892 rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
893 if (IS_ERR(rockchip->aclk_rst)) {
894 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
895 dev_err(dev, "missing aclk reset property in node\n");
896 return PTR_ERR(rockchip->aclk_rst);
899 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
900 if (IS_ERR(rockchip->ep_gpio)) {
901 dev_err(dev, "missing ep-gpios property in node\n");
902 return PTR_ERR(rockchip->ep_gpio);
905 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
906 if (IS_ERR(rockchip->aclk_pcie)) {
907 dev_err(dev, "aclk clock not found\n");
908 return PTR_ERR(rockchip->aclk_pcie);
911 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
912 if (IS_ERR(rockchip->aclk_perf_pcie)) {
913 dev_err(dev, "aclk_perf clock not found\n");
914 return PTR_ERR(rockchip->aclk_perf_pcie);
917 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
918 if (IS_ERR(rockchip->hclk_pcie)) {
919 dev_err(dev, "hclk clock not found\n");
920 return PTR_ERR(rockchip->hclk_pcie);
923 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
924 if (IS_ERR(rockchip->clk_pcie_pm)) {
925 dev_err(dev, "pm clock not found\n");
926 return PTR_ERR(rockchip->clk_pcie_pm);
929 irq = platform_get_irq_byname(pdev, "sys");
931 dev_err(dev, "missing sys IRQ resource\n");
935 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
936 IRQF_SHARED, "pcie-sys", rockchip);
938 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
942 irq = platform_get_irq_byname(pdev, "legacy");
944 dev_err(dev, "missing legacy IRQ resource\n");
948 irq_set_chained_handler_and_data(irq,
949 rockchip_pcie_legacy_int_handler,
952 irq = platform_get_irq_byname(pdev, "client");
954 dev_err(dev, "missing client IRQ resource\n");
958 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
959 IRQF_SHARED, "pcie-client", rockchip);
961 dev_err(dev, "failed to request PCIe client IRQ\n");
965 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
966 if (IS_ERR(rockchip->vpcie3v3)) {
967 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
968 return -EPROBE_DEFER;
969 dev_info(dev, "no vpcie3v3 regulator found\n");
972 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
973 if (IS_ERR(rockchip->vpcie1v8)) {
974 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
975 return -EPROBE_DEFER;
976 dev_info(dev, "no vpcie1v8 regulator found\n");
979 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
980 if (IS_ERR(rockchip->vpcie0v9)) {
981 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
982 return -EPROBE_DEFER;
983 dev_info(dev, "no vpcie0v9 regulator found\n");
989 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
991 struct device *dev = rockchip->dev;
994 if (!IS_ERR(rockchip->vpcie3v3)) {
995 err = regulator_enable(rockchip->vpcie3v3);
997 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
1002 if (!IS_ERR(rockchip->vpcie1v8)) {
1003 err = regulator_enable(rockchip->vpcie1v8);
1005 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
1006 goto err_disable_3v3;
1010 if (!IS_ERR(rockchip->vpcie0v9)) {
1011 err = regulator_enable(rockchip->vpcie0v9);
1013 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1014 goto err_disable_1v8;
1021 if (!IS_ERR(rockchip->vpcie1v8))
1022 regulator_disable(rockchip->vpcie1v8);
1024 if (!IS_ERR(rockchip->vpcie3v3))
1025 regulator_disable(rockchip->vpcie3v3);
1030 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
1032 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
1033 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
1034 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
1035 PCIE_CORE_INT_MASK);
1037 rockchip_pcie_enable_bw_int(rockchip);
1040 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
1041 irq_hw_number_t hwirq)
1043 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
1044 irq_set_chip_data(irq, domain->host_data);
1049 static const struct irq_domain_ops intx_domain_ops = {
1050 .map = rockchip_pcie_intx_map,
1053 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1055 struct device *dev = rockchip->dev;
1056 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1059 dev_err(dev, "missing child interrupt-controller node\n");
1063 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
1064 &intx_domain_ops, rockchip);
1065 if (!rockchip->irq_domain) {
1066 dev_err(dev, "failed to get a INTx IRQ domain\n");
1073 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1074 int region_no, int type, u8 num_pass_bits,
1075 u32 lower_addr, u32 upper_addr)
1082 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1084 if (num_pass_bits + 1 < 8)
1086 if (num_pass_bits > 63)
1088 if (region_no == 0) {
1089 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1092 if (region_no != 0) {
1093 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1097 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1099 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1100 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1101 ob_addr_1 = upper_addr;
1102 ob_desc_0 = (1 << 23 | type);
1104 rockchip_pcie_write(rockchip, ob_addr_0,
1105 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1106 rockchip_pcie_write(rockchip, ob_addr_1,
1107 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1108 rockchip_pcie_write(rockchip, ob_desc_0,
1109 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1110 rockchip_pcie_write(rockchip, 0,
1111 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1116 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1117 int region_no, u8 num_pass_bits,
1118 u32 lower_addr, u32 upper_addr)
1124 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1126 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1128 if (num_pass_bits > 63)
1131 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1133 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1134 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1135 ib_addr_1 = upper_addr;
1137 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1138 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1143 static int rockchip_pcie_probe(struct platform_device *pdev)
1145 struct rockchip_pcie *rockchip;
1146 struct device *dev = &pdev->dev;
1147 struct pci_bus *bus, *child;
1148 struct resource_entry *win;
1149 resource_size_t io_base;
1150 struct resource *mem;
1151 struct resource *io;
1152 phys_addr_t io_bus_addr = 0;
1154 phys_addr_t mem_bus_addr = 0;
1165 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1169 rockchip->dev = dev;
1171 err = rockchip_pcie_parse_dt(rockchip);
1175 err = clk_prepare_enable(rockchip->aclk_pcie);
1177 dev_err(dev, "unable to enable aclk_pcie clock\n");
1181 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1183 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1184 goto err_aclk_perf_pcie;
1187 err = clk_prepare_enable(rockchip->hclk_pcie);
1189 dev_err(dev, "unable to enable hclk_pcie clock\n");
1193 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1195 dev_err(dev, "unable to enable hclk_pcie clock\n");
1199 err = rockchip_pcie_set_vpcie(rockchip);
1201 dev_err(dev, "failed to set vpcie regulator\n");
1205 err = rockchip_pcie_init_port(rockchip);
1209 platform_set_drvdata(pdev, rockchip);
1211 rockchip_pcie_enable_interrupts(rockchip);
1213 err = rockchip_pcie_init_irq_domain(rockchip);
1217 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1222 err = devm_request_pci_bus_resources(dev, &res);
1226 /* Get the I/O and memory ranges from DT */
1228 resource_list_for_each_entry(win, &res) {
1229 switch (resource_type(win->res)) {
1233 io_size = resource_size(io);
1234 io_bus_addr = io->start - win->offset;
1235 err = pci_remap_iospace(io, io_base);
1237 dev_warn(dev, "error %d: failed to map resource %pR\n",
1242 case IORESOURCE_MEM:
1245 mem_size = resource_size(mem);
1246 mem_bus_addr = mem->start - win->offset;
1248 case IORESOURCE_BUS:
1249 rockchip->root_bus_nr = win->res->start;
1257 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1258 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1259 AXI_WRAPPER_MEM_WRITE,
1265 dev_err(dev, "program RC mem outbound ATU failed\n");
1271 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1273 dev_err(dev, "program RC mem inbound ATU failed\n");
1277 offset = mem_size >> 20;
1280 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1281 err = rockchip_pcie_prog_ob_atu(rockchip,
1282 reg_no + 1 + offset,
1283 AXI_WRAPPER_IO_WRITE,
1289 dev_err(dev, "program RC io outbound ATU failed\n");
1295 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1301 pci_bus_size_bridges(bus);
1302 pci_bus_assign_resources(bus);
1303 list_for_each_entry(child, &bus->children, node)
1304 pcie_bus_configure_settings(child);
1306 pci_bus_add_devices(bus);
1308 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1313 if (!IS_ERR(rockchip->vpcie3v3))
1314 regulator_disable(rockchip->vpcie3v3);
1315 if (!IS_ERR(rockchip->vpcie1v8))
1316 regulator_disable(rockchip->vpcie1v8);
1317 if (!IS_ERR(rockchip->vpcie0v9))
1318 regulator_disable(rockchip->vpcie0v9);
1320 clk_disable_unprepare(rockchip->clk_pcie_pm);
1322 clk_disable_unprepare(rockchip->hclk_pcie);
1324 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1326 clk_disable_unprepare(rockchip->aclk_pcie);
1331 static const struct of_device_id rockchip_pcie_of_match[] = {
1332 { .compatible = "rockchip,rk3399-pcie", },
1336 static struct platform_driver rockchip_pcie_driver = {
1338 .name = "rockchip-pcie",
1339 .of_match_table = rockchip_pcie_of_match,
1341 .probe = rockchip_pcie_probe,
1344 builtin_platform_driver(rockchip_pcie_driver);