drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/rtl8703b/sdio/sdio_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _SDIO_HALINIT_C_
  21
  22 #include <rtl8703b_hal.h>
  23 #include "hal_com_h2c.h"
  24
  25 /*
  26  * Description:
  27  *      Call power on sequence to enable card
  28  *
  29  * Return:
  30  *      _SUCCESS        enable success
  31  *      _FAIL           enable fail
  32  */
  33 static u8 CardEnable(PADAPTER padapter)
  34 {
  35         u8 bMacPwrCtrlOn;
  36         u8 ret = _FAIL;
  37
  38
  39         bMacPwrCtrlOn = _FALSE;
  40         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  41         if (bMacPwrCtrlOn == _FALSE) {
  42                 /* RSV_CTRL 0x1C[7:0] = 0x00 */
  43                 /* unlock ISO/CLK/Power control register */
  44                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
  45
  46                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_enable_flow);
  47                 if (ret == _SUCCESS) {
  48                         u8 bMacPwrCtrlOn = _TRUE;
  49                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  50                 }
  51         } else
  52                 ret = _SUCCESS;
  53
  54         return ret;
  55 }
  56
  57 /* static */
  58 u32 _InitPowerOn_8703BS(PADAPTER padapter)
  59 {
  60         u8 value8;
  61         u16 value16;
  62         u32 value32;
  63         u8 ret;
  64         u8 pwron_chk_cnt = 0;
  65         /*      u8 bMacPwrCtrlOn; */
  66
  67 _init_power_on:
  68
  69 #if 1
  70         /* all of these MUST be configured before power on */
  71 #ifdef CONFIG_XTAL_26M
  72         /* Config PLL Reference CLK, */
  73         /* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
  74         /* APLL_FREF_SEL[0]=1b'1 */
  75         value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
  76         value8 |= BIT(2);
  77         rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
  78         /* APLL_FREF_SEL[2:1]=2b'10 */
  79         value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B + 1);
  80         value8 &= ~(BIT(1) | BIT(0));
  81         value8 |= BIT(1);
  82         rtw_write16(padapter, REG_AFE_CTRL_4_8703B + 1, value8);
  83         /* APLL_FREF_SEL[3]=1b'0 */
  84         value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B);
  85         value8 &= ~BIT(7);
  86         rtw_write16(padapter, REG_AFE_CTRL_4_8703B, value8);
  87 #endif /* CONFIG_XTAL_26M */
  88
  89 #ifdef CONFIG_EXT_CLK
  90         /* Use external crystal(XTAL) */
  91         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8703B + 2);
  92         value8 |=  BIT(7);
  93         rtw_write8(padapter, REG_PAD_CTRL1_8703B + 2, value8);
  94
  95         /* CLK_REQ High active or Low Active */
  96         /* Request GPIO polarity: */
  97         /* 0: low active */
  98         /* 1: high active */
  99         value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
 100         value8 |= BIT(5);
 101         rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
 102 #endif /* CONFIG_EXT_CLK */
 103 #endif /* all of these MUST be configured before power on */
 104
 105         /* only cmd52 can be used before power on(card enable) */
 106         ret = CardEnable(padapter);
 107         if (ret == _FALSE) {
 108                 return _FAIL;
 109         }
 110
 111         /* Radio-Off Pin Trigger */
 112         value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
 113         value8 |= BIT(1); /* Enable falling edge triggering interrupt */
 114         rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
 115         value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
 116         value8 |= BIT(1);
 117         rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
 118
 119         /* Enable power down and GPIO interrupt */
 120         value16 = rtw_read16(padapter, REG_APS_FSMCO);
 121         value16 |= EnPDN; /* Enable HW power down and RF on */
 122         rtw_write16(padapter, REG_APS_FSMCO, value16);
 123
 124         /* Enable CMD53 R/W Operation
 125         *       bMacPwrCtrlOn = _TRUE;
 126         *       rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
 127
 128         rtw_write8(padapter, REG_CR, 0x00);
 129         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 130         value16 = rtw_read16(padapter, REG_CR);
 131         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 132                     | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 133         rtw_write16(padapter, REG_CR, value16);
 134
 135
 136         /* PowerOnCheck() */
 137         ret = sdio_power_on_check(padapter);
 138         pwron_chk_cnt++;
 139         if (_FAIL == ret) {
 140                 if (pwron_chk_cnt > 1) {
 141                         RTW_INFO("Failed to init Power On!\n");
 142                         return _FAIL;
 143                 }
 144                 RTW_INFO("Power on Fail! do it again\n");
 145                 goto _init_power_on;
 146         }
 147
 148 #ifdef CONFIG_BT_COEXIST
 149         rtw_btcoex_PowerOnSetting(padapter);
 150
 151         /* external switch to S1 */
 152         /* 0x38[11] = 0x1 */
 153         /* 0x4c[23] = 0x1 */
 154         /* 0x64[0] = 0 */
 155         value16 = rtw_read16(padapter, REG_PWR_DATA);
 156         /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
 157         value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */
 158         rtw_write16(padapter, REG_PWR_DATA, value16);
 159         /*      RTW_INFO("%s: REG_PWR_DATA(0x%x)=0x%04X\n", __FUNCTION__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */
 160
 161         value32 = rtw_read32(padapter, REG_LEDCFG0);
 162         value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */
 163         rtw_write32(padapter, REG_LEDCFG0, value32);
 164         /*      RTW_INFO("%s: REG_LEDCFG0(0x%x)=0x%08X\n", __FUNCTION__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */
 165
 166         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8703B);
 167         value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
 168         rtw_write8(padapter, REG_PAD_CTRL1_8703B, value8);
 169         /*      RTW_INFO("%s: REG_PAD_CTRL1(0x%x)=0x%02X\n", __FUNCTION__, REG_PAD_CTRL1_8703B, rtw_read8(padapter, REG_PAD_CTRL1_8703B)); */
 170 #endif /* CONFIG_BT_COEXIST */
 171
 172         return _SUCCESS;
 173 }
 174
 175 /* Tx Page FIFO threshold */
 176 static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
 177 {
 178         u16     HQ_threshold, NQ_threshold, LQ_threshold;
 179
 180         HQ_threshold = (numPubQ + numHQ + 1) >> 1;
 181         HQ_threshold |= (HQ_threshold << 8);
 182
 183         NQ_threshold = (numPubQ + numNQ + 1) >> 1;
 184         NQ_threshold |= (NQ_threshold << 8);
 185
 186         LQ_threshold = (numPubQ + numLQ + 1) >> 1;
 187         LQ_threshold |= (LQ_threshold << 8);
 188
 189         rtw_write16(padapter, 0x218, HQ_threshold);
 190         rtw_write16(padapter, 0x21A, NQ_threshold);
 191         rtw_write16(padapter, 0x21C, LQ_threshold);
 192         RTW_INFO("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
 193 }
 194
 195 static void _InitQueueReservedPage(PADAPTER padapter)
 196 {
 197         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 198         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
 199         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 200         u32                     numHQ           = 0;
 201         u32                     numLQ           = 0;
 202         u32                     numNQ           = 0;
 203         u32                     numPubQ;
 204         u32                     value32;
 205         u8                      value8;
 206         BOOLEAN                 bWiFiConfig     = pregistrypriv->wifi_spec;
 207
 208         if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 209                 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8703B : NORMAL_PAGE_NUM_HPQ_8703B;
 210
 211         if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 212                 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8703B : NORMAL_PAGE_NUM_LPQ_8703B;
 213
 214         /* NOTE: This step shall be proceed before writting REG_RQPN. */
 215         if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 216                 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8703B : NORMAL_PAGE_NUM_NPQ_8703B;
 217
 218         numPubQ = TX_TOTAL_PAGE_NUMBER_8703B - numHQ - numLQ - numNQ;
 219
 220         value8 = (u8)_NPQ(numNQ);
 221         rtw_write8(padapter, REG_RQPN_NPQ, value8);
 222
 223         /* TX DMA */
 224         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 225         rtw_write32(padapter, REG_RQPN, value32);
 226
 227         rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
 228
 229 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
 230         _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
 231 #endif
 232 }
 233
 234 static void _InitTxBufferBoundary(PADAPTER padapter)
 235 {
 236         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 237 #ifdef CONFIG_CONCURRENT_MODE
 238         u8 val8;
 239 #endif /* CONFIG_CONCURRENT_MODE */
 240
 241         /* u16  txdmactrl; */
 242         u8      txpktbuf_bndy;
 243
 244         if (!pregistrypriv->wifi_spec)
 245                 txpktbuf_bndy = TX_PAGE_BOUNDARY_8703B;
 246         else {
 247                 /* for WMM */
 248                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8703B;
 249         }
 250
 251         rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8703B, txpktbuf_bndy);
 252         rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8703B, txpktbuf_bndy);
 253         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B, txpktbuf_bndy);
 254         rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 255         rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
 256
 257 #ifdef CONFIG_CONCURRENT_MODE
 258         val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8703B + WOWLAN_PAGE_NUM_8703B;
 259         rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
 260         rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 1, val8); /* BCN1_HEAD */
 261
 262         val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
 263         val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
 264         rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
 265 #endif /* CONFIG_CONCURRENT_MODE */
 266 }
 267
 268 static VOID
 269 _InitNormalChipRegPriority(
 270         IN      PADAPTER        Adapter,
 271         IN      u16             beQ,
 272         IN      u16             bkQ,
 273         IN      u16             viQ,
 274         IN      u16             voQ,
 275         IN      u16             mgtQ,
 276         IN      u16             hiQ
 277 )
 278 {
 279         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 280
 281         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 282                         _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 283                         _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 284
 285         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 286 }
 287
 288 static VOID
 289 _InitNormalChipOneOutEpPriority(
 290         IN      PADAPTER Adapter
 291 )
 292 {
 293         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 294
 295         u16     value = 0;
 296         switch (pHalData->OutEpQueueSel) {
 297         case TX_SELE_HQ:
 298                 value = QUEUE_HIGH;
 299                 break;
 300         case TX_SELE_LQ:
 301                 value = QUEUE_LOW;
 302                 break;
 303         case TX_SELE_NQ:
 304                 value = QUEUE_NORMAL;
 305                 break;
 306         default:
 307                 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
 308                 break;
 309         }
 310
 311         _InitNormalChipRegPriority(Adapter,
 312                                    value,
 313                                    value,
 314                                    value,
 315                                    value,
 316                                    value,
 317                                    value
 318                                   );
 319
 320 }
 321
 322 static VOID
 323 _InitNormalChipTwoOutEpPriority(
 324         IN      PADAPTER Adapter
 325 )
 326 {
 327         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 328         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 329         u16                     beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 330
 331
 332         u16     valueHi = 0;
 333         u16     valueLow = 0;
 334
 335         switch (pHalData->OutEpQueueSel) {
 336         case (TX_SELE_HQ | TX_SELE_LQ):
 337                 valueHi = QUEUE_HIGH;
 338                 valueLow = QUEUE_LOW;
 339                 break;
 340         case (TX_SELE_NQ | TX_SELE_LQ):
 341                 valueHi = QUEUE_NORMAL;
 342                 valueLow = QUEUE_LOW;
 343                 break;
 344         case (TX_SELE_HQ | TX_SELE_NQ):
 345                 valueHi = QUEUE_HIGH;
 346                 valueLow = QUEUE_NORMAL;
 347                 break;
 348         default:
 349                 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
 350                 break;
 351         }
 352
 353         if (!pregistrypriv->wifi_spec) {
 354                 beQ             = valueLow;
 355                 bkQ             = valueLow;
 356                 viQ             = valueHi;
 357                 voQ             = valueHi;
 358                 mgtQ    = valueHi;
 359                 hiQ             = valueHi;
 360         } else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 361                 beQ             = valueLow;
 362                 bkQ             = valueHi;
 363                 viQ             = valueHi;
 364                 voQ             = valueLow;
 365                 mgtQ    = valueHi;
 366                 hiQ             = valueHi;
 367         }
 368
 369         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 370
 371 }
 372
 373 static VOID
 374 _InitNormalChipThreeOutEpPriority(
 375         IN      PADAPTER padapter
 376 )
 377 {
 378         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 379         u16                     beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 380
 381         if (!pregistrypriv->wifi_spec) { /* typical setting */
 382                 beQ             = QUEUE_LOW;
 383                 bkQ             = QUEUE_LOW;
 384                 viQ             = QUEUE_NORMAL;
 385                 voQ             = QUEUE_HIGH;
 386                 mgtQ    = QUEUE_HIGH;
 387                 hiQ             = QUEUE_HIGH;
 388         } else { /* for WMM */
 389                 beQ             = QUEUE_LOW;
 390                 bkQ             = QUEUE_NORMAL;
 391                 viQ             = QUEUE_NORMAL;
 392                 voQ             = QUEUE_HIGH;
 393                 mgtQ    = QUEUE_HIGH;
 394                 hiQ             = QUEUE_HIGH;
 395         }
 396         _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 397 }
 398
 399 static VOID
 400 _InitNormalChipQueuePriority(
 401         IN      PADAPTER Adapter
 402 )
 403 {
 404         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 405
 406         switch (pHalData->OutEpNumber) {
 407         case 1:
 408                 _InitNormalChipOneOutEpPriority(Adapter);
 409                 break;
 410         case 2:
 411                 _InitNormalChipTwoOutEpPriority(Adapter);
 412                 break;
 413         case 3:
 414                 _InitNormalChipThreeOutEpPriority(Adapter);
 415                 break;
 416         default:
 417                 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
 418                 break;
 419         }
 420
 421
 422 }
 423
 424 static void _InitQueuePriority(PADAPTER padapter)
 425 {
 426         _InitNormalChipQueuePriority(padapter);
 427 }
 428
 429 static void _InitPageBoundary(PADAPTER padapter)
 430 {
 431         /* RX Page Boundary */
 432         u16 rxff_bndy = RX_DMA_BOUNDARY_8703B;
 433
 434         rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 435 }
 436
 437 static void _InitTransferPageSize(PADAPTER padapter)
 438 {
 439         /* Tx page size is always 128. */
 440
 441         u8 value8;
 442         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 443         rtw_write8(padapter, REG_PBP, value8);
 444 }
 445
 446 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
 447 {
 448         rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 449 }
 450
 451 void _InitNetworkType(PADAPTER padapter)
 452 {
 453         u32 value32;
 454
 455         value32 = rtw_read32(padapter, REG_CR);
 456
 457         /* TODO: use the other function to set network type
 458         *       value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
 459         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 460
 461         rtw_write32(padapter, REG_CR, value32);
 462 }
 463
 464 void _InitWMACSetting(PADAPTER padapter)
 465 {
 466         PHAL_DATA_TYPE pHalData;
 467         u16 value16;
 468
 469
 470         pHalData = GET_HAL_DATA(padapter);
 471
 472         pHalData->ReceiveConfig = 0;
 473         pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
 474         pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
 475         pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
 476         pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
 477 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
 478         pHalData->ReceiveConfig |= RCR_AAP;
 479         pHalData->ReceiveConfig |= RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF;
 480 #endif
 481         rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
 482
 483         /* Accept all multicast address */
 484         rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
 485         rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
 486
 487         /* Accept all data frames */
 488         value16 = 0xFFFF;
 489         rtw_write16(padapter, REG_RXFLTMAP2, value16);
 490
 491         /* 2010.09.08 hpfan */
 492         /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
 493         /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
 494         value16 = 0x400;
 495         rtw_write16(padapter, REG_RXFLTMAP1, value16);
 496
 497         /* Accept all management frames */
 498         value16 = 0xFFFF;
 499         rtw_write16(padapter, REG_RXFLTMAP0, value16);
 500 }
 501
 502 void _InitAdaptiveCtrl(PADAPTER padapter)
 503 {
 504         u16     value16;
 505         u32     value32;
 506
 507         /* Response Rate Set */
 508         value32 = rtw_read32(padapter, REG_RRSR);
 509         value32 &= ~RATE_BITMAP_ALL;
 510         value32 |= RATE_RRSR_CCK_ONLY_1M;
 511         rtw_write32(padapter, REG_RRSR, value32);
 512
 513         /* CF-END Threshold */
 514         /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
 515
 516         /* SIFS (used in NAV) */
 517         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 518         rtw_write16(padapter, REG_SPEC_SIFS, value16);
 519
 520         /* Retry Limit */
 521         value16 = _LRL(0x30) | _SRL(0x30);
 522         rtw_write16(padapter, REG_RL, value16);
 523 }
 524
 525 void _InitEDCA(PADAPTER padapter)
 526 {
 527         /* Set Spec SIFS (used in NAV) */
 528         rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
 529         rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
 530
 531         /* Set SIFS for CCK */
 532         rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
 533
 534         /* Set SIFS for OFDM */
 535         rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
 536
 537         /* TXOP */
 538         rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 539         rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 540         rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
 541         rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
 542 }
 543
 544 void _InitRateFallback(PADAPTER padapter)
 545 {
 546         /* Set Data Auto Rate Fallback Retry Count register. */
 547         rtw_write32(padapter, REG_DARFRC, 0x00000000);
 548         rtw_write32(padapter, REG_DARFRC + 4, 0x10080404);
 549         rtw_write32(padapter, REG_RARFRC, 0x04030201);
 550         rtw_write32(padapter, REG_RARFRC + 4, 0x08070605);
 551
 552 }
 553
 554 void _InitRetryFunction(PADAPTER padapter)
 555 {
 556         u8      value8;
 557
 558         value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
 559         value8 |= EN_AMPDU_RTY_NEW;
 560         rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
 561
 562         /* Set ACK timeout */
 563         rtw_write8(padapter, REG_ACKTO, 0x40);
 564 }
 565
 566 static void HalRxAggr8703BSdio(PADAPTER padapter)
 567 {
 568         struct registry_priv *pregistrypriv;
 569         u8      valueDMATimeout;
 570         u8      valueDMAPageCount;
 571
 572
 573         pregistrypriv = &padapter->registrypriv;
 574
 575         if (pregistrypriv->wifi_spec) {
 576                 /* 2010.04.27 hpfan */
 577                 /* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
 578                 /* Timeout value is calculated by 34 / (2^n) */
 579                 valueDMATimeout = 0x06;
 580                 valueDMAPageCount = 0x06;
 581         } else {
 582                 /* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
 583 #if 1
 584                 /* TX/RX Balance */
 585                 valueDMATimeout = 0x06;
 586                 valueDMAPageCount = 0x06;
 587 #endif
 588 #if 0
 589                 /* TX/RX Balance, but TCP ack may be late */
 590                 valueDMATimeout = 0x16;
 591                 valueDMAPageCount = 0x06;
 592 #endif
 593 #if 0
 594                 /* RX Best */
 595                 valueDMATimeout = 0x16;
 596                 valueDMAPageCount = 0x08;
 597 #endif
 598         }
 599
 600 #ifdef CONFIG_DONT_CARE_TP
 601         valueDMATimeout = 0x0f;
 602         valueDMAPageCount = 0x04;  /* RxAggUpthreshold = [4]*1K bytes+1.5k.  since RxAggUpthreshold+SzAmsdu(3839)<MaxRxBuffSize(8k), MaxvalueDMAPageCount=4. */
 603 #endif
 604         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
 605         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
 606 }
 607
 608 void sdio_AggSettingRxUpdate(PADAPTER padapter)
 609 {
 610         HAL_DATA_TYPE *pHalData;
 611         u8 valueDMA;
 612         u8 valueRxAggCtrl = 0;
 613         u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
 614         u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
 615
 616         pHalData = GET_HAL_DATA(padapter);
 617
 618         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 619         valueDMA |= RXDMA_AGG_EN;
 620         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 621
 622         valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 623         valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
 624         valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
 625         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
 626 }
 627
 628 void _initSdioAggregationSetting(PADAPTER padapter)
 629 {
 630         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 631
 632         /* Tx aggregation setting
 633         *       sdio_AggSettingTxUpdate(padapter); */
 634
 635         /* Rx aggregation setting */
 636         HalRxAggr8703BSdio(padapter);
 637
 638         sdio_AggSettingRxUpdate(padapter);
 639 }
 640
 641 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
 642 {
 643         PHAL_DATA_TYPE pHalData;
 644         u8 valueDMA;
 645         u8 valueRxAggCtrl;
 646
 647
 648         pHalData = GET_HAL_DATA(padapter);
 649
 650         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 651         valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8703B);
 652
 653         if (_TRUE == enable) {
 654                 valueDMA |= RXDMA_AGG_EN;
 655                 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 656         } else {
 657                 valueDMA &= ~RXDMA_AGG_EN;
 658                 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
 659         }
 660
 661         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 662         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);
 663 }
 664
 665 void _InitOperationMode(PADAPTER padapter)
 666 {
 667         PHAL_DATA_TYPE pHalData;
 668         struct mlme_ext_priv *pmlmeext;
 669         u8                              regBwOpMode = 0;
 670         u32                             regRATR = 0, regRRSR = 0;
 671         u8                              MinSpaceCfg = 0;
 672
 673
 674         pHalData = GET_HAL_DATA(padapter);
 675         pmlmeext = &padapter->mlmeextpriv;
 676
 677         /* 1 This part need to modified according to the rate set we filtered!! */
 678         /*  */
 679         /* Set RRSR, RATR, and REG_BWOPMODE registers */
 680         /*  */
 681         switch (pmlmeext->cur_wireless_mode) {
 682         case WIRELESS_MODE_B:
 683                 regBwOpMode = BW_OPMODE_20MHZ;
 684                 regRATR = RATE_ALL_CCK;
 685                 regRRSR = RATE_ALL_CCK;
 686                 break;
 687         case WIRELESS_MODE_A:
 688                 /*                      RT_ASSERT(FALSE,("Error wireless a mode\n")); */
 689 #if 0
 690                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 691                 regRATR = RATE_ALL_OFDM_AG;
 692                 regRRSR = RATE_ALL_OFDM_AG;
 693 #endif
 694                 break;
 695         case WIRELESS_MODE_G:
 696                 regBwOpMode = BW_OPMODE_20MHZ;
 697                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 698                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 699                 break;
 700         case WIRELESS_MODE_AUTO:
 701 #if 0
 702                 if (padapter->bInHctTest) {
 703                         regBwOpMode = BW_OPMODE_20MHZ;
 704                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 705                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 706                 } else
 707 #endif
 708                 {
 709                         regBwOpMode = BW_OPMODE_20MHZ;
 710                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 711                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 712                 }
 713                 break;
 714         case WIRELESS_MODE_N_24G:
 715                 /* It support CCK rate by default. */
 716                 /* CCK rate will be filtered out only when associated AP does not support it. */
 717                 regBwOpMode = BW_OPMODE_20MHZ;
 718                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 719                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 720                 break;
 721         case WIRELESS_MODE_N_5G:
 722                 /*                      RT_ASSERT(FALSE,("Error wireless mode")); */
 723 #if 0
 724                 regBwOpMode = BW_OPMODE_5G;
 725                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 726                 regRRSR = RATE_ALL_OFDM_AG;
 727 #endif
 728                 break;
 729
 730         default: /* for MacOSX compiler warning. */
 731                 break;
 732         }
 733
 734         rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
 735
 736 }
 737
 738 void _InitInterrupt(PADAPTER padapter)
 739 {
 740         /* HISR - turn all off */
 741         rtw_write32(padapter, REG_HISR, 0);
 742
 743         /* HIMR - turn all off */
 744         rtw_write32(padapter, REG_HIMR, 0);
 745
 746         /*  */
 747         /* Initialize and enable SDIO Host Interrupt. */
 748         /*  */
 749         InitInterrupt8703BSdio(padapter);
 750
 751         /*  */
 752         /* Initialize system Host Interrupt. */
 753         /*  */
 754         InitSysInterrupt8703BSdio(padapter);
 755 }
 756
 757 void _InitRDGSetting(PADAPTER padapter)
 758 {
 759         rtw_write8(padapter, REG_RD_CTRL, 0xFF);
 760         rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
 761         rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
 762 }
 763
 764 static void _InitRFType(PADAPTER padapter)
 765 {
 766         struct registry_priv *pregpriv = &padapter->registrypriv;
 767         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 768
 769 #if     DISABLE_BB_RF
 770         pHalData->rf_chip       = RF_PSEUDO_11N;
 771         return;
 772 #endif
 773         pHalData->rf_chip       = RF_6052;
 774
 775         RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
 776 }
 777
 778 /* Set CCK and OFDM Block "ON" */
 779 static void _BBTurnOnBlock(PADAPTER padapter)
 780 {
 781 #if (DISABLE_BB_RF)
 782         return;
 783 #endif
 784
 785         phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 786         phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 787 }
 788
 789 static void _RfPowerSave(PADAPTER padapter)
 790 {
 791         /* YJ,TODO */
 792 }
 793
 794 static void _InitAntenna_Selection(PADAPTER padapter)
 795 {
 796         rtw_write8(padapter, REG_LEDCFG2, 0x82);
 797 }
 798
 799 static void _InitPABias(PADAPTER padapter)
 800 {
 801         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 802         u8                      pa_setting;
 803
 804         /* FIXED PA current issue */
 805         /* efuse_one_byte_read(padapter, 0x1FA, &pa_setting); */
 806         efuse_OneByteRead(padapter, 0x1FA, &pa_setting, _FALSE);
 807
 808
 809         if (!(pa_setting & BIT0)) {
 810                 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 811                 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 812                 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 813                 phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 814         }
 815
 816         if (!(pa_setting & BIT4)) {
 817                 pa_setting = rtw_read8(padapter, 0x16);
 818                 pa_setting &= 0x0F;
 819                 rtw_write8(padapter, 0x16, pa_setting | 0x80);
 820                 rtw_write8(padapter, 0x16, pa_setting | 0x90);
 821         }
 822 }
 823
 824 VOID _InitBBRegBackup_8703BS(PADAPTER   Adapter)
 825 {
 826         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 827
 828         /* For Channel 1~11 (Default Value)*/
 829         pHalData->RegForRecover[0].offset = rCCK0_TxFilter2;
 830         pHalData->RegForRecover[0].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[0].offset, bMaskDWord);
 831
 832         pHalData->RegForRecover[1].offset = rCCK0_DebugPort;
 833         pHalData->RegForRecover[1].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[1].offset, bMaskDWord);
 834
 835         /* For 20 MHz   (Default Value)*/
 836         pHalData->RegForRecover[2].offset = rBBrx_DFIR;
 837         pHalData->RegForRecover[2].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord);
 838
 839         pHalData->RegForRecover[3].offset = rOFDM0_XATxAFE;
 840         pHalData->RegForRecover[3].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord);
 841
 842         pHalData->RegForRecover[4].offset = 0x1E;
 843         pHalData->RegForRecover[4].value = phy_query_rf_reg(Adapter, ODM_RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask);
 844 }
 845
 846 /*
 847  * 2010/08/09 MH Add for power down check.
 848  *   */
 849 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
 850 {
 851         u8 tmpvalue;
 852         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
 853         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 854
 855
 856         EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8703B, (u32 *)&tmpvalue);
 857
 858         /* 2010/08/25 MH INF priority > PDN Efuse value. */
 859         if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 860                 pHalData->pwrdown = _TRUE;
 861         else
 862                 pHalData->pwrdown = _FALSE;
 863
 864         RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
 865
 866         return pHalData->pwrdown;
 867 }       /* HalDetectPwrDownMode */
 868
 869 static u32 rtl8703bs_hal_init(PADAPTER padapter)
 870 {
 871         s32 ret;
 872         PHAL_DATA_TYPE pHalData;
 873         struct pwrctrl_priv *pwrctrlpriv;
 874         struct registry_priv *pregistrypriv;
 875         struct sreset_priv *psrtpriv;
 876         struct dvobj_priv *psdpriv = padapter->dvobj;
 877         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
 878         rt_rf_power_state eRfPowerStateToSet;
 879         u32 NavUpper = WiFiNavUpperUs;
 880         u8 u1bTmp;
 881         u16 value16;
 882         u8 typeid;
 883         u32 u4Tmp;
 884
 885         pHalData = GET_HAL_DATA(padapter);
 886         psrtpriv = &pHalData->srestpriv;
 887         pwrctrlpriv = adapter_to_pwrctl(padapter);
 888         pregistrypriv = &padapter->registrypriv;
 889
 890 #ifdef CONFIG_SWLPS_IN_IPS
 891         if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
 892                 u8 val8, bMacPwrCtrlOn = _TRUE;
 893
 894                 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
 895
 896                 /* ser rpwm */
 897                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 898                 val8 &= 0x80;
 899                 val8 += 0x80;
 900                 val8 |= BIT(6);
 901                 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 902
 903                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 904
 905                 rtw_mdelay_os(5); /* wait set rpwm already */
 906
 907                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_leave_swlps_flow);
 908                 if (ret == _FALSE) {
 909                         RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
 910                         return _FAIL;
 911                 }
 912
 913                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 914
 915                 pHalData->LastHMEBoxNum = 0;
 916
 917 #ifdef CONFIG_BT_COEXIST
 918                 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
 919 #else
 920                 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
 921 #endif /* CONFIG_BT_COEXIST */
 922
 923                 return _SUCCESS;
 924         }
 925 #elif defined(CONFIG_FWLPS_IN_IPS)
 926         if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
 927             && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
 928                 u32 start_time;
 929                 u8 cpwm_orig, cpwm_now;
 930                 u8 val8, bMacPwrCtrlOn = _TRUE;
 931
 932                 RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
 933
 934                 /* for polling cpwm */
 935                 cpwm_orig = 0;
 936                 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
 937
 938                 /* ser rpwm */
 939                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 940                 val8 &= 0x80;
 941                 val8 += 0x80;
 942                 val8 |= BIT(6);
 943                 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 944                 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
 945                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 946
 947                 /* do polling cpwm */
 948                 start_time = rtw_get_current_time();
 949                 do {
 950
 951                         rtw_mdelay_os(1);
 952
 953                         rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
 954                         if ((cpwm_orig ^ cpwm_now) & 0x80) {
 955 #ifdef DBG_CHECK_FW_PS_STATE
 956                                 RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
 957                                         , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
 958 #endif /* DBG_CHECK_FW_PS_STATE */
 959                                 break;
 960                         }
 961
 962                         if (rtw_get_passing_time_ms(start_time) > 100) {
 963                                 RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
 964                                 break;
 965                         }
 966                 } while (1);
 967
 968                 rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0);
 969
 970                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 971
 972 #ifdef CONFIG_BT_COEXIST
 973                 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
 974 #else
 975                 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
 976 #endif /* CONFIG_BT_COEXIST */
 977
 978 #ifdef DBG_CHECK_FW_PS_STATE
 979                 if (rtw_fw_ps_state(padapter) == _FAIL) {
 980                         RTW_INFO("after hal init, fw ps state in 32k\n");
 981                         pdbgpriv->dbg_ips_drvopen_fail_cnt++;
 982                 }
 983 #endif /* DBG_CHECK_FW_PS_STATE */
 984                 return _SUCCESS;
 985         }
 986 #endif /* CONFIG_SWLPS_IN_IPS */
 987
 988         /* Disable Interrupt first.
 989         *       rtw_hal_disable_interrupt(padapter); */
 990
 991         if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
 992                 RTW_INFO("FW exist before power on!!\n");
 993         else
 994                 RTW_INFO("FW does not exist before power on!!\n");
 995
 996         if (rtw_fw_ps_state(padapter) == _FAIL) {
 997                 RTW_INFO("check fw_ps_state fail before PowerOn!\n");
 998                 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
 999         }
1000
1001         ret = rtw_hal_power_on(padapter);
1002         if (_FAIL == ret) {
1003                 return _FAIL;
1004         }
1005         RTW_INFO("Power on ok!\n");
1006
1007         if (rtw_fw_ps_state(padapter) == _FAIL) {
1008                 RTW_INFO("check fw_ps_state fail after PowerOn!\n");
1009                 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
1010         }
1011
1012
1013         rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
1014
1015         if (padapter->registrypriv.mp_mode == 0) {
1016                 ret = rtl8703b_FirmwareDownload(padapter, _FALSE);
1017                 if (ret != _SUCCESS) {
1018                         padapter->bFWReady = _FALSE;
1019                         pHalData->fw_ractrl = _FALSE;
1020                         return ret;
1021                 } else {
1022                         padapter->bFWReady = _TRUE;
1023                         pHalData->fw_ractrl = _TRUE;
1024                 }
1025         }
1026
1027         /*      SIC_Init(padapter); */
1028
1029         if (pwrctrlpriv->reg_rfoff == _TRUE)
1030                 pwrctrlpriv->rf_pwrstate = rf_off;
1031
1032         /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
1033         /* HW GPIO pin. Before PHY_RFConfig8192C. */
1034         HalDetectPwrDownMode(padapter);
1035
1036         /* Set RF type for BB/RF configuration */
1037         _InitRFType(padapter);
1038
1039         /* Save target channel */
1040         /* <Roger_Notes> Current Channel will be updated again later. */
1041         pHalData->current_channel = 6;
1042
1043 #if (HAL_MAC_ENABLE == 1)
1044         ret = PHY_MACConfig8703B(padapter);
1045         if (ret != _SUCCESS) {
1046                 return ret;
1047         }
1048 #endif
1049         /*  */
1050         /* d. Initialize BB related configurations. */
1051         /*  */
1052 #if (HAL_BB_ENABLE == 1)
1053         ret = PHY_BBConfig8703B(padapter);
1054         if (ret != _SUCCESS) {
1055                 return ret;
1056         }
1057
1058 #endif
1059
1060         /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
1061         /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
1062         /* if(pHalData->eRFPowerState == eRfOn) */
1063         {
1064 #if (HAL_RF_ENABLE == 1)
1065                 ret = PHY_RFConfig8703B(padapter);
1066                 if (ret != _SUCCESS) {
1067                         return ret;
1068                 }
1069 #endif
1070         }
1071
1072         _InitBBRegBackup_8703BS(padapter);
1073
1074         _InitMacAPLLSetting_8703B(padapter);
1075
1076         /*  */
1077         /* Joseph Note: Keep RfRegChnlVal for later use. */
1078         /*  */
1079         pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, (RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
1080         pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, (RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
1081
1082 #if 0
1083         /* Specially add for FWDL by Tx pkt write. Reset Tx/Rx DMA since the Tx boundary setting
1084                 is changed during FW download */
1085         rtw_write8(padapter, REG_CR, 0x00);
1086         rtw_write8(padapter, REG_CR, 0xFF);
1087 #endif
1088
1089         /* if (!pHalData->bMACFuncEnable) { */
1090         _InitQueueReservedPage(padapter);
1091         _InitTxBufferBoundary(padapter);
1092
1093         /* init LLT after tx buffer boundary is defined */
1094         ret = rtl8703b_InitLLTTable(padapter);
1095         if (_SUCCESS != ret) {
1096                 RTW_INFO("%s: Failed to init LLT Table!\n", __FUNCTION__);
1097                 return _FAIL;
1098         }
1099         /* } */
1100         _InitQueuePriority(padapter);
1101         _InitPageBoundary(padapter);
1102         _InitTransferPageSize(padapter);
1103
1104         /* Get Rx PHY status in order to report RSSI and others. */
1105         _InitDriverInfoSize(padapter, DRVINFO_SZ);
1106         _InitNetworkType(padapter);
1107         _InitWMACSetting(padapter);
1108         _InitAdaptiveCtrl(padapter);
1109         _InitEDCA(padapter);
1110         /* _InitRateFallback(padapter); */
1111         _InitRetryFunction(padapter);
1112         _initSdioAggregationSetting(padapter);
1113         _InitOperationMode(padapter);
1114         rtl8703b_InitBeaconParameters(padapter);
1115         rtl8703b_InitBeaconMaxError(padapter, _TRUE);
1116         _InitInterrupt(padapter);
1117         _InitBurstPktLen_8703BS(padapter);
1118
1119 #if 0
1120         /* 8703B new ADD */
1121         _InitLTECoex_8703BS(padapter);
1122 #endif
1123
1124         /* YJ,TODO */
1125         rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8703B, 0x3);        /* CCA */
1126         rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
1127
1128 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1129
1130 #ifdef CONFIG_CHECK_AC_LIFETIME
1131         /* Enable lifetime check for the four ACs */
1132         rtw_write8(padapter, REG_LIFETIME_CTRL, rtw_read8(padapter, REG_LIFETIME_CTRL) | 0x0F);
1133 #endif /* CONFIG_CHECK_AC_LIFETIME */
1134
1135 #ifdef CONFIG_TX_MCAST2UNI
1136         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
1137         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
1138 #else   /* CONFIG_TX_MCAST2UNI */
1139         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); /* unit: 256us. 3s */
1140         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); /* unit: 256us. 3s */
1141 #endif /* CONFIG_TX_MCAST2UNI */
1142 #endif /* CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI */
1143
1144
1145         invalidate_cam_all(padapter);
1146
1147         rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1148                 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1149
1150         rtl8703b_InitAntenna_Selection(padapter);
1151
1152         /*  */
1153         /* Disable BAR, suggested by Scott */
1154         /* 2010.04.09 add by hpfan */
1155         /*  */
1156         rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1157
1158         /* HW SEQ CTRL */
1159         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1160         rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1161
1162
1163 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1164         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
1165         u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1166         rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
1167
1168         rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1169         rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
1170         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
1171         rtw_write32(padapter, REG_CR, 0x0b0202ff);
1172 #endif
1173
1174         /*  */
1175         /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
1176         /* 2010.02.24. */
1177         /*  */
1178         rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
1179
1180         _RfPowerSave(padapter);
1181
1182
1183         rtl8703b_InitHalDm(padapter);
1184
1185         /* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
1186
1187         /* if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) */ /* The lowest Beacon Type that HW can support */
1188         /*              pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; */
1189
1190         /*  */
1191         /* Update current Tx FIFO page status. */
1192         /*  */
1193         HalQueryTxBufferStatus8703BSdio(padapter);
1194         HalQueryTxOQTBufferStatus8703BSdio(padapter);
1195         pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1196
1197         /* Enable MACTXEN/MACRXEN block */
1198         u1bTmp = rtw_read8(padapter, REG_CR);
1199         u1bTmp |= (MACTXEN | MACRXEN);
1200         rtw_write8(padapter, REG_CR, u1bTmp);
1201
1202         rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
1203
1204 #ifdef CONFIG_XMIT_ACK
1205         /* ack for xmit mgmt frames. */
1206         rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
1207 #endif /* CONFIG_XMIT_ACK        */
1208
1209         /*      pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
1210
1211 #if (MP_DRIVER == 1)
1212         if (padapter->registrypriv.mp_mode == 1) {
1213                 padapter->mppriv.channel = pHalData->current_channel;
1214                 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1215         } else
1216 #endif /* #if (MP_DRIVER == 1) */
1217         {
1218                 pwrctrlpriv->rf_pwrstate = rf_on;
1219
1220                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
1221                         struct pwrctrl_priv *pwrpriv;
1222                         u32 start_time;
1223                         u8 h2cCmdBuf;
1224
1225                         pwrpriv = adapter_to_pwrctl(padapter);
1226
1227                         phy_lc_calibrate_8703b(&pHalData->odmpriv);
1228
1229                         /* Inform WiFi FW that it is the beginning of IQK */
1230                         h2cCmdBuf = 1;
1231                         FillH2CCmd8703B(padapter, H2C_8703B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1232
1233                         start_time = rtw_get_current_time();
1234                         do {
1235                                 if (rtw_read8(padapter, 0x1e7) & 0x01)
1236                                         break;
1237
1238                                 rtw_msleep_os(50);
1239                         } while (rtw_get_passing_time_ms(start_time) <= 400);
1240
1241 #ifdef CONFIG_BT_COEXIST
1242                         rtw_btcoex_IQKNotify(padapter, _TRUE);
1243 #endif
1244                         phy_iq_calibrate_8703b(padapter, _FALSE);
1245                         pHalData->bIQKInitialized = _TRUE;
1246 #ifdef CONFIG_BT_COEXIST
1247                         rtw_btcoex_IQKNotify(padapter, _FALSE);
1248 #endif
1249
1250                         /* Inform WiFi FW that it is the finish of IQK */
1251                         h2cCmdBuf = 0;
1252                         FillH2CCmd8703B(padapter, H2C_8703B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1253
1254                         odm_txpowertracking_check(&pHalData->odmpriv);
1255                 }
1256         }
1257
1258 #ifdef CONFIG_BT_COEXIST
1259         /* Init BT hw config.*/
1260         if (padapter->registrypriv.mp_mode == 1)
1261                 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1262         else
1263                 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1264 #endif
1265
1266
1267         return _SUCCESS;
1268 }
1269
1270 static void CardDisableRTL8703BSdio(PADAPTER padapter)
1271 {
1272         u8              u1bTmp;
1273         u16             u2bTmp;
1274         u32             u4bTmp;
1275         u8              bMacPwrCtrlOn;
1276         u8              ret = _FAIL;
1277
1278         /* Run LPS WL RFOFF flow */
1279         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_lps_flow);
1280         if (ret == _FAIL)
1281                 RTW_ERR("%s: run RF OFF flow fail!\n", __func__);
1282
1283         /*      ==== Reset digital sequence   ====== */
1284
1285         u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1286         if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
1287                 rtl8703b_FirmwareSelfReset(padapter);
1288
1289         /* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
1290         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1291         u1bTmp &= ~BIT(2);      /* 0x2[10], FEN_CPUEN */
1292         rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1293
1294         /* MCUFWDL 0x80[1:0]=0 */
1295         /* reset MCU ready status */
1296         rtw_write8(padapter, REG_MCUFWDL, 0);
1297
1298         /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1299         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1300         u1bTmp &= ~BIT(0);
1301         rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1302         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1303         u1bTmp |= BIT(0);
1304         rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1305
1306         /*      ==== Reset digital sequence end ====== */
1307
1308         bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1309         ret = _FALSE;
1310         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1311         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_disable_flow);
1312         if (ret == _FALSE)
1313                 RTW_ERR("%s: run CARD DISABLE flow fail!\n", __func__);
1314
1315         padapter->bFWReady = _FALSE;
1316 }
1317
1318 static u32 rtl8703bs_hal_deinit(PADAPTER padapter)
1319 {
1320         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1321         struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1322         struct dvobj_priv *psdpriv = padapter->dvobj;
1323         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1324
1325 #ifdef CONFIG_MP_INCLUDED
1326         if (padapter->registrypriv.mp_mode == 1)
1327                 MPT_DeInitAdapter(padapter);
1328 #endif
1329
1330         if (rtw_is_hw_init_completed(padapter)) {
1331 #ifdef CONFIG_SWLPS_IN_IPS
1332                 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
1333                         u8      bMacPwrCtrlOn;
1334                         u8 ret =  _TRUE;
1335
1336                         RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
1337
1338                         rtw_write32(padapter, 0x130, 0x0);
1339                         rtw_write32(padapter, 0x138, 0x100);
1340                         rtw_write8(padapter, 0x13d, 0x1);
1341
1342
1343                         bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W     */
1344                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1345
1346                         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_swlps_flow);
1347                         if (ret == _FALSE) {
1348                                 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1349                                 return _FAIL;
1350                         }
1351                 } else
1352 #elif defined(CONFIG_FWLPS_IN_IPS)
1353                 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
1354                         if (padapter->netif_up == _TRUE) {
1355                                 int cnt = 0;
1356                                 u8 val8 = 0;
1357
1358                                 RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1359
1360                                 rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0x1);
1361                                 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
1362                                 do {
1363                                         val8 = rtw_read8(padapter, REG_HMETFR);
1364                                         cnt++;
1365                                         RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1366                                         rtw_mdelay_os(10);
1367                                 } while (cnt < 100 && (val8 != 0));
1368                                 /* H2C done, enter 32k */
1369                                 if (val8 == 0) {
1370                                         /* ser rpwm to enter 32k */
1371                                         val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1372                                         val8 += 0x80;
1373                                         val8 |= BIT(0);
1374                                         rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1375                                         RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1376                                         adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1377                                         cnt = val8 = 0;
1378                                         do {
1379                                                 val8 = rtw_read8(padapter, REG_CR);
1380                                                 cnt++;
1381                                                 RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1382                                                 rtw_mdelay_os(10);
1383                                         } while (cnt < 100 && (val8 != 0xEA));
1384 #ifdef DBG_CHECK_FW_PS_STATE
1385                                         if (val8 != 0xEA)
1386                                                 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1387                                                         , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1388 #endif /* DBG_CHECK_FW_PS_STATE */
1389                                 } else {
1390                                         RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1391                                                 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1392                                 }
1393
1394                                 RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1395                                         , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1396
1397                                 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1398
1399                         } else {
1400                                 pdbgpriv->dbg_carddisable_cnt++;
1401 #ifdef DBG_CHECK_FW_PS_STATE
1402                                 if (rtw_fw_ps_state(padapter) == _FAIL) {
1403                                         RTW_INFO("card disable should leave 32k\n");
1404                                         pdbgpriv->dbg_carddisable_error_cnt++;
1405                                 }
1406 #endif /* DBG_CHECK_FW_PS_STATE */
1407                                 rtw_hal_power_off(padapter);
1408
1409                                 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1410                         }
1411
1412                 } else
1413 #endif /* CONFIG_SWLPS_IN_IPS */
1414                 {
1415                         pdbgpriv->dbg_carddisable_cnt++;
1416 #ifdef DBG_CHECK_FW_PS_STATE
1417                         if (rtw_fw_ps_state(padapter) == _FAIL) {
1418                                 RTW_INFO("card disable should leave 32k\n");
1419                                 pdbgpriv->dbg_carddisable_error_cnt++;
1420                         }
1421 #endif /* DBG_CHECK_FW_PS_STATE */
1422                         rtw_hal_power_off(padapter);
1423                 }
1424         } else
1425                 pdbgpriv->dbg_deinit_fail_cnt++;
1426
1427         return _SUCCESS;
1428 }
1429 static void rtl8703bs_init_default_value(PADAPTER padapter)
1430 {
1431         PHAL_DATA_TYPE pHalData;
1432
1433
1434         pHalData = GET_HAL_DATA(padapter);
1435
1436         rtl8703b_init_default_value(padapter);
1437
1438         /* interface related variable */
1439         pHalData->SdioRxFIFOCnt = 0;
1440 }
1441
1442 static void rtl8703bs_interface_configure(PADAPTER padapter)
1443 {
1444         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
1445         struct dvobj_priv               *pdvobjpriv = adapter_to_dvobj(padapter);
1446         struct registry_priv    *pregistrypriv = &padapter->registrypriv;
1447         BOOLEAN         bWiFiConfig     = pregistrypriv->wifi_spec;
1448
1449
1450         pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1451         pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1452         pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1453
1454         if (bWiFiConfig)
1455                 pHalData->OutEpNumber = 2;
1456         else
1457                 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1458
1459         switch (pHalData->OutEpNumber) {
1460         case 3:
1461                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1462                 break;
1463         case 2:
1464                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1465                 break;
1466         case 1:
1467                 pHalData->OutEpQueueSel = TX_SELE_HQ;
1468                 break;
1469         default:
1470                 break;
1471         }
1472
1473         Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1474 }
1475
1476 /*
1477  *      Description:
1478  *              We should set Efuse cell selection to WiFi cell in default.
1479  *
1480  *      Assumption:
1481  *              PASSIVE_LEVEL
1482  *
1483  *      Added by Roger, 2010.11.23.
1484  *   */
1485 static void
1486 _EfuseCellSel(
1487         IN      PADAPTER        padapter
1488 )
1489 {
1490         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
1491
1492         u32                     value32;
1493
1494         /* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
1495         {
1496                 value32 = rtw_read32(padapter, EFUSE_TEST);
1497                 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1498                 rtw_write32(padapter, EFUSE_TEST, value32);
1499         }
1500 }
1501
1502 static VOID
1503 _ReadRFType(
1504         IN      PADAPTER        Adapter
1505 )
1506 {
1507         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1508
1509 #if DISABLE_BB_RF
1510         pHalData->rf_chip = RF_PSEUDO_11N;
1511 #else
1512         pHalData->rf_chip = RF_6052;
1513 #endif
1514 }
1515
1516 static VOID
1517 _ReadEfuseInfo8703BS(
1518         IN PADAPTER                     padapter
1519 )
1520 {
1521         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1522         u8                      *hwinfo = NULL;
1523
1524
1525         /*  */
1526         /* This part read and parse the eeprom/efuse content */
1527         /*  */
1528
1529         if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8703B)
1530                 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8703B!\n");
1531
1532         hwinfo = pHalData->efuse_eeprom_data;
1533
1534         Hal_InitPGData(padapter, hwinfo);
1535
1536         Hal_EfuseParseIDCode(padapter, hwinfo);
1537         Hal_EfuseParseEEPROMVer_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1538         hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1539         Hal_EfuseParseTxPowerInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1540         Hal_EfuseParseBoardType_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1541
1542         /*  */
1543         /* Read Bluetooth co-exist and initialize */
1544         /*  */
1545         Hal_EfuseParseBTCoexistInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1546         Hal_EfuseParseChnlPlan_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1547         Hal_EfuseParseXtal_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1548         Hal_EfuseParseThermalMeter_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1549         Hal_EfuseParseAntennaDiversity_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1550         Hal_EfuseParseCustomerID_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1551
1552         Hal_EfuseParseVoltage_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1553
1554 #ifdef CONFIG_WOWLAN
1555         Hal_DetectWoWMode(padapter);
1556 #endif
1557
1558         Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
1559
1560 #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
1561         hal_read_mac_hidden_rpt(padapter);
1562 #endif
1563 }
1564
1565 static void _ReadPROMContent(
1566         IN PADAPTER             padapter
1567 )
1568 {
1569         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1570         u8                      eeValue;
1571
1572         eeValue = rtw_read8(padapter, REG_9346CR);
1573         /* To check system boot selection. */
1574         pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1575         pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1576
1577
1578         /*      pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1579
1580         _ReadEfuseInfo8703BS(padapter);
1581 }
1582
1583 static VOID
1584 _InitOtherVariable(
1585         IN PADAPTER             Adapter
1586 )
1587 {
1588         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1589
1590
1591         /* if(Adapter->bInHctTest){ */
1592         /*      pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
1593         /*      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
1594         /*      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
1595         /*      pMgntInfo->keepAliveLevel = 0; */
1596         /* } */
1597
1598
1599
1600 }
1601
1602 /*
1603  *      Description:
1604  *              Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
1605  *
1606  *      Assumption:
1607  *              PASSIVE_LEVEL (SDIO interface)
1608  *
1609  *   */
1610 static u8 ReadAdapterInfo8703BS(PADAPTER padapter)
1611 {
1612         u8 val8;
1613
1614         val8 = rtw_read8(padapter, 0x4e);
1615         RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
1616         val8 |= BIT(6);
1617         rtw_write8(padapter, 0x4e, val8);
1618
1619         /* Read EEPROM size before call any EEPROM function */
1620         padapter->EepromAddressSize = GetEEPROMSize8703B(padapter);
1621
1622         _EfuseCellSel(padapter);
1623         _ReadRFType(padapter);
1624         _ReadPROMContent(padapter);
1625         _InitOtherVariable(padapter);
1626
1627 #ifdef CONFIG_PLATFORM_INTEL_BYT
1628         { /* for BT, let BT can control ANT when wifi disable */
1629                 u32 val32;
1630                 RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
1631                 val32 = rtw_read32(padapter, 0x64);
1632                 RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
1633                 val32 |= BIT(13);
1634                 rtw_write32(padapter, 0x64, val32);
1635                 RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
1636         }
1637 #endif /* CONFIG_PLATFORM_INTEL_BYT */
1638
1639         if (!rtw_is_hw_init_completed(padapter))
1640                 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */
1641
1642         return _SUCCESS;
1643 }
1644
1645 /*
1646  * If variable not handled here,
1647  * some variables will be processed in SetHwReg8703B()
1648  */
1649 void SetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
1650 {
1651         PHAL_DATA_TYPE pHalData;
1652         u8 val8;
1653
1654
1655         pHalData = GET_HAL_DATA(padapter);
1656
1657         switch (variable) {
1658         case HW_VAR_SET_RPWM:
1659                 /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
1660                 /* BIT0 value - 1: 32k, 0:40MHz. */
1661                 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1662                 /* BIT7 value - Toggle bit change. */
1663         {
1664                 val8 = *val;
1665                 val8 &= 0xC1;
1666                 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1667         }
1668         break;
1669         case HW_VAR_SET_REQ_FW_PS:
1670         /* 1. driver write 0x8f[4]=1  */ { /* request fw ps state (only can write bit4) */
1671                 u8 req_fw_ps = 0;
1672                 req_fw_ps = rtw_read8(padapter, 0x8f);
1673                 req_fw_ps |= 0x10;
1674                 rtw_write8(padapter, 0x8f, req_fw_ps);
1675         }
1676         break;
1677         case HW_VAR_RXDMA_AGG_PG_TH:
1678                 val8 = *val;
1679
1680                 /* TH=1 => invalidate RX DMA aggregation */
1681                 /* TH=0 => validate RX DMA aggregation, use init value. */
1682                 if (val8 == 0) {
1683                         /* enable RXDMA aggregation */
1684                         /* _RXAggrSwitch(padapter, _TRUE); */
1685                 } else {
1686                         /* disable RXDMA aggregation */
1687                         /* _RXAggrSwitch(padapter, _FALSE); */
1688                 }
1689                 break;
1690         case HW_VAR_DM_IN_LPS:
1691                 rtl8703b_hal_dm_in_lps(padapter);
1692                 break;
1693         default:
1694                 SetHwReg8703B(padapter, variable, val);
1695                 break;
1696         }
1697
1698 }
1699
1700 /*
1701  * If variable not handled here,
1702  * some variables will be processed in GetHwReg8703B()
1703  */
1704 void GetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
1705 {
1706         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1707
1708
1709         switch (variable) {
1710         case HW_VAR_CPWM:
1711                 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8703B);
1712                 break;
1713
1714         case HW_VAR_FW_PS_STATE: {
1715                 /* 3. read dword 0x88               */ /* driver read fw ps state */
1716                 *((u16 *)val) = rtw_read16(padapter, 0x88);
1717         }
1718         break;
1719         default:
1720                 GetHwReg8703B(padapter, variable, val);
1721                 break;
1722         }
1723
1724 }
1725
1726 /*
1727  *      Description:
1728  *              Query setting of specified variable.
1729  *   */
1730 u8
1731 GetHalDefVar8703BSDIO(
1732         IN      PADAPTER                                Adapter,
1733         IN      HAL_DEF_VARIABLE                eVariable,
1734         IN      PVOID                                   pValue
1735 )
1736 {
1737         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1738         u8                      bResult = _SUCCESS;
1739
1740         switch (eVariable) {
1741         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1742 #ifdef CONFIG_ANTENNA_DIVERSITY
1743                 *((u8 *)pValue) = _FALSE;
1744 #endif
1745                 break;
1746
1747         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1748                 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1749                 /* coding by Lucas@20130730 */
1750                 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
1751                 break;
1752         default:
1753                 bResult = GetHalDefVar8703B(Adapter, eVariable, pValue);
1754                 break;
1755         }
1756
1757         return bResult;
1758 }
1759
1760 /*
1761  *      Description:
1762  *              Change default setting of specified variable.
1763  *   */
1764 u8
1765 SetHalDefVar8703BSDIO(
1766         IN      PADAPTER                                Adapter,
1767         IN      HAL_DEF_VARIABLE                eVariable,
1768         IN      PVOID                                   pValue
1769 )
1770 {
1771         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
1772         u8                      bResult = _SUCCESS;
1773
1774         switch (eVariable) {
1775         default:
1776                 bResult = SetHalDefVar8703B(Adapter, eVariable, pValue);
1777                 break;
1778         }
1779
1780         return bResult;
1781 }
1782
1783 void rtl8703bs_set_hal_ops(PADAPTER padapter)
1784 {
1785         struct hal_ops *pHalFunc = &padapter->hal_func;
1786
1787
1788         rtl8703b_set_hal_ops(pHalFunc);
1789
1790         pHalFunc->hal_power_on = &_InitPowerOn_8703BS;
1791         pHalFunc->hal_power_off = &CardDisableRTL8703BSdio;
1792
1793
1794         pHalFunc->hal_init = &rtl8703bs_hal_init;
1795         pHalFunc->hal_deinit = &rtl8703bs_hal_deinit;
1796
1797         pHalFunc->init_xmit_priv = &rtl8703bs_init_xmit_priv;
1798         pHalFunc->free_xmit_priv = &rtl8703bs_free_xmit_priv;
1799
1800         pHalFunc->init_recv_priv = &rtl8703bs_init_recv_priv;
1801         pHalFunc->free_recv_priv = &rtl8703bs_free_recv_priv;
1802
1803         pHalFunc->InitSwLeds = &rtl8703bs_InitSwLeds;
1804         pHalFunc->DeInitSwLeds = &rtl8703bs_DeInitSwLeds;
1805
1806         pHalFunc->init_default_value = &rtl8703bs_init_default_value;
1807         pHalFunc->intf_chip_configure = &rtl8703bs_interface_configure;
1808         pHalFunc->read_adapter_info = &ReadAdapterInfo8703BS;
1809
1810         pHalFunc->enable_interrupt = &EnableInterrupt8703BSdio;
1811         pHalFunc->disable_interrupt = &DisableInterrupt8703BSdio;
1812         pHalFunc->check_ips_status = &CheckIPSStatus;
1813 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1814         pHalFunc->clear_interrupt = &ClearInterrupt8703BSdio;
1815 #endif
1816         pHalFunc->set_hw_reg_handler = &SetHwReg8703BS;
1817         pHalFunc->GetHwRegHandler = &GetHwReg8703BS;
1818         pHalFunc->get_hal_def_var_handler = &GetHalDefVar8703BSDIO;
1819         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8703BSDIO;
1820
1821         pHalFunc->hal_xmit = &rtl8703bs_hal_xmit;
1822         pHalFunc->mgnt_xmit = &rtl8703bs_mgnt_xmit;
1823         pHalFunc->hal_xmitframe_enqueue = &rtl8703bs_hal_xmitframe_enqueue;
1824
1825 #ifdef CONFIG_HOSTAPD_MLME
1826         pHalFunc->hostap_mgnt_xmit_entry = NULL;
1827 #endif
1828
1829 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
1830         pHalFunc->hal_init_checkbthang_workqueue = &rtl8703bs_init_checkbthang_workqueue;
1831         pHalFunc->hal_free_checkbthang_workqueue = &rtl8703bs_free_checkbthang_workqueue;
1832         pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8703bs_cancle_checkbthang_workqueue;
1833         pHalFunc->hal_checke_bt_hang = &rtl8703bs_hal_check_bt_hang;
1834 #endif
1835
1836 }