drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/phydm_psd.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 //============================================================\r
  22 // include files\r
  23 //============================================================\r
  24 #include "mp_precomp.h"
  25 #include "phydm_precomp.h"\r
  26 \r
  27 #if (CONFIG_PSD_TOOL == 1)\r
  28 \r
  29 u32\r
  30 phydm_get_psd_data(\r
  31         void                    *p_dm_void,\r
  32         u32                     psd_tone_idx,\r
  33         u32                     igi\r
  34         )\r
  35 {\r
  36         struct  PHY_DM_STRUCT   *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
  37         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
  38         u32             psd_report = 0;\r
  39         \r
  40         odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);\r
  41         \r
  42         odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/\r
  43         ODM_delay_us(10);\r
  44         odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/\r
  45 \r
  46         psd_report = odm_get_bb_reg(p_dm_odm, p_dm_psd_table->psd_report_reg, 0xffff);\r
  47         psd_report = odm_convert_to_db(psd_report) + igi;\r
  48 \r
  49         return psd_report;\r
  50 }\r
  51 \r
  52 u8\r
  53 phydm_psd_stop_trx(\r
  54         void            *p_dm_void\r
  55         )\r
  56 {\r
  57         struct  PHY_DM_STRUCT   *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
  58         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
  59         u32             i;\r
  60         u8              trx_idle_success = FALSE;\r
  61         u32             dbg_port_value = 0;\r
  62 \r
  63         /*[Stop TRX]---------------------------------------------------------------------*/\r
  64         if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, 0x0) == FALSE) /*set debug port to 0x0*/\r
  65                 return STOP_TRX_FAIL;\r
  66         \r
  67         for (i = 0; i<10000; i++) {\r
  68                 dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm);\r
  69                 if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ {\r
  70                         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD wait for ((%d)) times\n", i));\r
  71                         \r
  72                         trx_idle_success = TRUE;\r
  73                         break;\r
  74                 }\r
  75         }\r
  76         \r
  77         if (trx_idle_success) {\r
  78                 \r
  79                 odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/\r
  80                 \r
  81                 if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
  82                         odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0); /*disable CCK block*/\r
  83                         odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/\r
  84                 } else {\r
  85                         /*TBD*/\r
  86                         odm_set_bb_reg(p_dm_odm, 0x800, BIT(24), 0); /* disable whole CCK block */\r
  87                         odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */\r
  88                 }\r
  89                         \r
  90         } else {\r
  91                 return STOP_TRX_FAIL;\r
  92         }\r
  93 \r
  94         phydm_release_bb_dbg_port(p_dm_odm);\r
  95         \r
  96         return STOP_TRX_SUCCESS;\r
  97         \r
  98 }\r
  99 \r
 100 u8              psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127};\r
 101 u8              psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67};   \r
 102 \r
 103 void\r
 104 phydm_psd(\r
 105         void            *p_dm_void,\r
 106         u32             igi,\r
 107         u16             start_point,\r
 108         u16             stop_point\r
 109         )\r
 110 {\r
 111         struct  PHY_DM_STRUCT   *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
 112         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
 113         u32             i = 0, mod_tone_idx;\r
 114         u32             t = 0;\r
 115         u16             fft_max_half_bw;\r
 116         u32             psd_igi_a_reg;\r
 117         u32             psd_igi_b_reg;\r
 118         u16             psd_fc_channel = p_dm_psd_table->psd_fc_channel;\r
 119         u8              ag_rf_mode_reg = 0;\r
 120         u8              rf_reg18_9_8 = 0;\r
 121         u32             psd_result_tmp = 0;\r
 122         u8              psd_result = 0;\r
 123         u8              psd_result_cali_tone[7] = {0};\r
 124         u8              psd_result_cali_val[7] = {0};\r
 125         u8              noise_table_idx = 0;\r
 126         u8              psd_result_cali_tmp = 0;\r
 127 \r
 128         if (p_dm_odm->support_ic_type == ODM_RTL8821) {\r
 129                 odm_move_memory(p_dm_odm, psd_result_cali_tone, psd_result_cali_tone_8821, 7);\r
 130                 odm_move_memory(p_dm_odm, psd_result_cali_val, psd_result_cali_val_8821, 7);\r
 131         }\r
 132         \r
 133         p_dm_psd_table->psd_in_progress = 1;\r
 134 \r
 135         /*[Stop DIG]*/\r
 136         p_dm_odm->support_ability &= ~(ODM_BB_DIG);\r
 137         p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT);\r
 138 \r
 139 \r
 140 \r
 141         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD Start =>\n"));\r
 142 \r
 143         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
 144                 psd_igi_a_reg = 0xc50;\r
 145                 psd_igi_b_reg = 0xe50;\r
 146         } else {\r
 147                 psd_igi_a_reg = 0xc50;\r
 148                 psd_igi_b_reg = 0xc58;\r
 149         }\r
 150         \r
 151         /*[back up IGI]*/\r
 152         p_dm_psd_table->initial_gain_backup = odm_get_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff); \r
 153         odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/\r
 154         odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/\r
 155         ODM_delay_us(10);\r
 156         \r
 157         if (phydm_psd_stop_trx(p_dm_odm) == STOP_TRX_FAIL) {\r
 158                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("STOP_TRX_FAIL\n"));\r
 159                 return;\r
 160         }\r
 161 \r
 162         /*[Set IGI]*/\r
 163         odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, igi);\r
 164         odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, igi);\r
 165         \r
 166         /*[Backup RF Reg]*/\r
 167         p_dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);\r
 168 \r
 169         if (psd_fc_channel > 14) {\r
 170                 \r
 171                 rf_reg18_9_8 = 1;\r
 172                 \r
 173                 if (36 <= psd_fc_channel && psd_fc_channel <= 64) \r
 174                         ag_rf_mode_reg = 0x1;\r
 175                 else if (100 <= psd_fc_channel && psd_fc_channel <= 140) \r
 176                         ag_rf_mode_reg = 0x3; \r
 177                 else if (140 < psd_fc_channel) \r
 178                         ag_rf_mode_reg = 0x5; \r
 179         }\r
 180 \r
 181         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel);     /* Set RF fc*/\r
 182         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8);\r
 183         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xc00, p_dm_psd_table->psd_bw_rf_reg);     /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\r
 184         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg);     /* Set RF ag fc mode*/\r
 185 \r
 186         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("0xc50=((0x%x))\n", odm_get_bb_reg(p_dm_odm, 0xc50, MASKDWORD)));\r
 187         /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x0=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK)));*/\r
 188         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x18=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK)));\r
 189         \r
 190         /*[Stop 3-wires]*/\r
 191         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
 192                 odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x4);/*    hardware 3-wire off */\r
 193                 odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x4);/*    hardware 3-wire off */\r
 194         } else {\r
 195                 odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable    88c[23:20]=0xf */\r
 196         }\r
 197         ODM_delay_us(10);\r
 198 \r
 199         if (stop_point > (p_dm_psd_table->fft_smp_point-1))\r
 200                 stop_point = (p_dm_psd_table->fft_smp_point-1); \r
 201 \r
 202         if (start_point > (p_dm_psd_table->fft_smp_point-1))\r
 203                 start_point = (p_dm_psd_table->fft_smp_point-1);\r
 204 \r
 205         if (start_point > stop_point)\r
 206                 stop_point = start_point;\r
 207 \r
 208 \r
 209         for (i = start_point; i <= stop_point; i++ ) {\r
 210 \r
 211                 fft_max_half_bw = (p_dm_psd_table->fft_smp_point)>>1;\r
 212 \r
 213                 if (i < fft_max_half_bw) {\r
 214                         mod_tone_idx = i + fft_max_half_bw;\r
 215                 } else {\r
 216                         mod_tone_idx = i - fft_max_half_bw;\r
 217                 }\r
 218                 \r
 219                 psd_result_tmp = 0;\r
 220                 for (t = 0; t < p_dm_psd_table->sw_avg_time; t++) {\r
 221                         psd_result_tmp += phydm_get_psd_data(p_dm_odm, mod_tone_idx, igi);\r
 222                         /**/\r
 223                 }\r
 224                 psd_result = (u8)((psd_result_tmp/p_dm_psd_table->sw_avg_time)) - p_dm_psd_table->psd_pwr_common_offset;\r
 225 \r
 226                 if( p_dm_psd_table->fft_smp_point == 128) {\r
 227 \r
 228                         if (p_dm_psd_table->noise_k_en) {\r
 229                                 if (i > psd_result_cali_tone[noise_table_idx]) {\r
 230                                         noise_table_idx ++;\r
 231                                 }\r
 232 \r
 233                                 if (noise_table_idx > 6)\r
 234                                         noise_table_idx = 6;\r
 235 \r
 236                                 if (psd_result >= psd_result_cali_val[noise_table_idx])\r
 237                                         psd_result = psd_result - psd_result_cali_val[noise_table_idx];\r
 238                                 else\r
 239                                         psd_result = 0;\r
 240                         }\r
 241 \r
 242                         p_dm_psd_table->psd_result[i] = psd_result;\r
 243                 }\r
 244                 \r
 245                 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx],  psd_result));\r
 246 \r
 247         }\r
 248 \r
 249         /*[Start 3-wires]*/\r
 250         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
 251                 odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x7);/*    hardware 3-wire on */\r
 252                 odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x7);/*    hardware 3-wire on */\r
 253         } else {\r
 254                 odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0x0); /* 3 wire enable    88c[23:20]=0x0 */\r
 255         }\r
 256         ODM_delay_us(10);\r
 257 \r
 258         /*[Revert Reg]*/\r
 259         odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0x0); /*start all TX queue*/\r
 260         odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 1); /*enable CCK block*/\r
 261         odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/\r
 262         \r
 263         odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, p_dm_psd_table->initial_gain_backup);\r
 264         odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, p_dm_psd_table->initial_gain_backup);\r
 265         \r
 266         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, p_dm_psd_table->rf_0x18_bkp);\r
 267         \r
 268         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD finished\n\n"));\r
 269         \r
 270         p_dm_odm->support_ability |= ODM_BB_DIG;\r
 271         p_dm_odm->support_ability |= ODM_BB_FA_CNT;\r
 272         p_dm_psd_table->psd_in_progress = 0;\r
 273         \r
 274 \r
 275 }\r
 276 \r
 277 void\r
 278 phydm_psd_para_setting(\r
 279         void            *p_dm_void,\r
 280         u8              sw_avg_time,\r
 281         u8              hw_avg_time,    \r
 282         u8              i_q_setting,\r
 283         u16             fft_smp_point,\r
 284         u8              ant_sel,\r
 285         u8              psd_input,\r
 286         u8              channel,\r
 287         u8              noise_k_en\r
 288         )\r
 289 {\r
 290         struct  PHY_DM_STRUCT   *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
 291         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
 292         u32             avg_temp;\r
 293         u8              fft_smp_point_idx = 0;\r
 294 \r
 295         p_dm_psd_table->fft_smp_point = fft_smp_point;\r
 296 \r
 297         if (sw_avg_time == 0)\r
 298                 sw_avg_time = 1;\r
 299         \r
 300         p_dm_psd_table->sw_avg_time = sw_avg_time;\r
 301         p_dm_psd_table->psd_fc_channel = channel;\r
 302         p_dm_psd_table->noise_k_en = noise_k_en;\r
 303                 \r
 304         if (fft_smp_point == 128)\r
 305                 fft_smp_point_idx = 0;\r
 306         else if (fft_smp_point == 256)\r
 307                 fft_smp_point_idx = 1;\r
 308         else if (fft_smp_point == 512)\r
 309                 fft_smp_point_idx = 2;\r
 310         else if (fft_smp_point == 1024)\r
 311                 fft_smp_point_idx = 3;\r
 312                 \r
 313         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
 314                 \r
 315                 odm_set_bb_reg(p_dm_odm, 0x910, BIT(11) | BIT(10), i_q_setting);\r
 316                 odm_set_bb_reg(p_dm_odm, 0x910, BIT(13) | BIT(12), hw_avg_time);\r
 317                 odm_set_bb_reg(p_dm_odm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx);\r
 318                 odm_set_bb_reg(p_dm_odm, 0x910, BIT(17) | BIT(16), ant_sel);\r
 319                 odm_set_bb_reg(p_dm_odm, 0x910, BIT(23), psd_input);\r
 320 \r
 321         } else {\r
 322 \r
 323         }\r
 324 \r
 325         /*bw = (*p_dm_odm->p_band_width); //ODM_BW20M */\r
 326         /*channel = *(p_dm_odm->p_channel);*/\r
 327         \r
 328         \r
 329 \r
 330 \r
 331 }\r
 332 \r
 333 void\r
 334 phydm_psd_init(\r
 335         void            *p_dm_void\r
 336         )\r
 337 {\r
 338         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
 339         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
 340 \r
 341         ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD para init\n"));\r
 342 \r
 343         p_dm_psd_table->psd_in_progress = FALSE;\r
 344         \r
 345         if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {\r
 346                 \r
 347                 p_dm_psd_table->psd_reg = 0x910;\r
 348                 p_dm_psd_table->psd_report_reg = 0xF44;\r
 349 \r
 350                 if (ODM_IC_11AC_2_SERIES)\r
 351                         p_dm_psd_table->psd_bw_rf_reg = 1;      /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\r
 352                 else\r
 353                         p_dm_psd_table->psd_bw_rf_reg = 2;      /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\r
 354                 \r
 355         } else {\r
 356         \r
 357                 p_dm_psd_table->psd_reg = 0x808;\r
 358                 p_dm_psd_table->psd_report_reg = 0x8B4;\r
 359                 p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */\r
 360         }\r
 361 \r
 362         if (p_dm_odm->support_ic_type == ODM_RTL8812)\r
 363                 p_dm_psd_table->psd_pwr_common_offset = 0;\r
 364         else if (p_dm_odm->support_ic_type == ODM_RTL8821)\r
 365                 p_dm_psd_table->psd_pwr_common_offset = 0;\r
 366         else\r
 367                 p_dm_psd_table->psd_pwr_common_offset = 0;\r
 368         \r
 369         phydm_psd_para_setting(p_dm_odm, 1, 2, 3, 128, 0, 0, 7, 0);\r
 370         /*phydm_psd(p_dm_odm, 0x3c, 0, 127);*/                  /* target at -50dBm */\r
 371 \r
 372 \r
 373 }\r
 374 \r
 375 void
 376 phydm_psd_debug(\r
 377         void            *p_dm_void,
 378         char            input[][16],\r
 379         u32             *_used,
 380         char            *output,\r
 381         u32             *_out_len,
 382         u32             input_num
 383 )
 384 {
 385         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 386         char            help[] = "-h";\r
 387         u32             var1[10] = {0};\r
 388         u32             used = *_used;\r
 389         u32             out_len = *_out_len;\r
 390         u8              i;\r
 391 \r
 392         if ((strcmp(input[1], help) == 0)) {\r
 393                 PHYDM_SNPRINTF((output + used, out_len - used, "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n"));\r
 394                 PHYDM_SNPRINTF((output + used, out_len - used, "{1} {IGI(hex)} {start_point} {stop_point}\n"));\r
 395 \r
 396         } else {\r
 397         \r
 398 \r
 399                 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);\r
 400 \r
 401                 if (var1[0] == 0) {\r
 402 \r
 403                         for (i = 1; i < 10; i++) {\r
 404                                 if (input[i + 1]) {\r
 405                                         PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);\r
 406                                 }\r
 407                         }\r
 408                         \r
 409                         PHYDM_SNPRINTF((output + used, out_len - used, "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", \r
 410                                 var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8]));\r
 411                         phydm_psd_para_setting(p_dm_odm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]);\r
 412                         \r
 413                 } else if (var1[0] == 1) {\r
 414 \r
 415                         PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);\r
 416                         PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);\r
 417                         PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);\r
 418                         PHYDM_SNPRINTF((output + used, out_len - used, "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", var1[1], var1[2], var1[3]));\r
 419                         p_dm_odm->debug_components |= ODM_COMP_API;\r
 420                         phydm_psd(p_dm_odm, var1[1], (u16)var1[2], (u16)var1[3]);\r
 421                         p_dm_odm->debug_components &= (~ODM_COMP_API);\r
 422                 }\r
 423 \r
 424         }\r
 425 \r
 426 \r
 427         \r
 428 }\r
 429 \r
 430 u8\r
 431 phydm_get_psd_result_table(\r
 432         void            *p_dm_void,\r
 433         int             index\r
 434         )\r
 435 {\r
 436         struct  PHY_DM_STRUCT   *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;\r
 437         struct  _PHYDM_PSD_     *p_dm_psd_table = &(p_dm_odm->dm_psd_table);\r
 438         u8              temp_result = 0;\r
 439 \r
 440         if(index<128)\r
 441                 temp_result = p_dm_psd_table->psd_result[index];\r
 442 \r
 443         return temp_result;\r
 444         \r
 445 }\r
 446 \r
 447 #endif\r
 448 \r