1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 /* ************************************************************
23 * ************************************************************ */
25 #include "mp_precomp.h"
26 #include "phydm_precomp.h"
28 const u16 db_invert_table[12][8] = {
29 { 1, 1, 1, 2, 2, 2, 2, 3},
30 { 3, 3, 4, 4, 4, 5, 6, 6},
31 { 7, 8, 9, 10, 11, 13, 14, 16},
32 { 18, 20, 22, 25, 28, 32, 35, 40},
33 { 45, 50, 56, 63, 71, 79, 89, 100},
34 { 112, 126, 141, 158, 178, 200, 224, 251},
35 { 282, 316, 355, 398, 447, 501, 562, 631},
36 { 708, 794, 891, 1000, 1122, 1259, 1413, 1585},
37 { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
38 { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
39 { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
40 { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
44 /* ************************************************************
45 * Local Function predefine.
46 * ************************************************************ */
48 /* START------------COMMON INFO RELATED--------------- */
51 odm_global_adapter_check(
55 /* move to odm_PowerTacking.h by YuChen */
60 odm_update_power_training_state(
61 struct PHY_DM_STRUCT *p_dm_odm
64 /* ************************************************************
66 * ************************************************************ */
76 s32 Y, integer = 0, decimal = 0;
80 X = 1; /* log2(x), x can't be 0 */
82 for (i = (total_bit - 1); i > 0; i--) {
86 decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */
91 Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
102 if (value & BIT(total_bit - 1))
103 value -= BIT(total_bit);
116 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
119 u32 tmp_idx_a, tmp_idx_b;
121 for (i = 0; i < seq_length; i++) {
126 for (i = 0; i < (seq_length - 1); i++) {
128 for (j = 0; j < (seq_length - 1 - i); j++) {
131 tmp_b = p_value[j + 1];
133 tmp_idx_a = rank_idx[j];
134 tmp_idx_b = rank_idx[j + 1];
138 p_value[j + 1] = tmp_a;
140 rank_idx[j] = tmp_idx_b;
141 rank_idx[j + 1] = tmp_idx_a;
146 for (i = 0; i < seq_length; i++) {
147 p_idx_out[rank_idx[i]] = i + 1;
156 odm_init_mp_driver_status(
157 struct PHY_DM_STRUCT *p_dm_odm
160 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
162 /* Decide when compile time */
164 p_dm_odm->mp_mode = true;
166 p_dm_odm->mp_mode = false;
169 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
171 struct _ADAPTER *adapter = p_dm_odm->adapter;
173 /* Update information every period */
174 p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode;
178 struct rtl8192cd_priv *priv = p_dm_odm->priv;
180 p_dm_odm->mp_mode = (boolean)priv->pshare->rf_ft_var.mp_specific;
186 odm_update_mp_driver_status(
187 struct PHY_DM_STRUCT *p_dm_odm
190 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
194 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
195 struct _ADAPTER *adapter = p_dm_odm->adapter;
197 /* Update information erery period */
198 p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode;
208 phydm_init_trx_antenna_setting(
209 struct PHY_DM_STRUCT *p_dm_odm
212 /*#if (RTL8814A_SUPPORT == 1)*/
214 if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) {
215 u8 rx_ant = 0, tx_ant = 0;
217 rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm));
218 tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm));
219 p_dm_odm->tx_ant_status = (tx_ant & 0xf);
220 p_dm_odm->rx_ant_status = (rx_ant & 0xf);
221 } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */
222 p_dm_odm->tx_ant_status = 0x1;
223 p_dm_odm->rx_ant_status = 0x1;
230 phydm_traffic_load_decision(
234 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
235 struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
237 /*---TP & Trafic-load calculation---*/
239 if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast)))
240 p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast));
242 if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast)))
243 p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast));
245 p_dm_odm->cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt;
246 p_dm_odm->cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt;
247 p_dm_odm->last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast);
248 p_dm_odm->last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast);
250 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
251 p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/
252 p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/
254 p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
255 p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
257 p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp;
260 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
261 p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt));
263 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n",
264 p_dm_odm->tx_tp, p_dm_odm->rx_tp));
267 p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load;
269 if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
271 p_dm_odm->traffic_load = TRAFFIC_HIGH;
273 } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
275 p_dm_odm->traffic_load = TRAFFIC_MID;
277 } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
279 p_dm_odm->traffic_load = TRAFFIC_LOW;
283 p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW;
289 phydm_config_ofdm_tx_path(
290 struct PHY_DM_STRUCT *p_dm_odm,
294 u8 ofdm_tx_path = 0x33;
296 #if (RTL8192E_SUPPORT == 1)
297 if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
299 if (path == PHYDM_A) {
300 odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121111);
302 } else if (path == PHYDM_B) {
303 odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x82221222);
305 } else if (path == PHYDM_AB) {
306 odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333);
314 #if (RTL8812A_SUPPORT == 1)
315 if (p_dm_odm->support_ic_type & (ODM_RTL8812)) {
317 if (path == PHYDM_A) {
320 } else if (path == PHYDM_B) {
323 } else if (path == PHYDM_AB) {
328 odm_set_bb_reg(p_dm_odm, 0x80c, 0xff00, ofdm_tx_path);
334 phydm_config_ofdm_rx_path(
335 struct PHY_DM_STRUCT *p_dm_odm,
342 if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
343 #if (RTL8192E_SUPPORT == 1)
344 if (path == PHYDM_A) {
347 } else if (path == PHYDM_B) {
350 } else if (path == PHYDM_AB) {
355 odm_set_bb_reg(p_dm_odm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path));
356 odm_set_bb_reg(p_dm_odm, 0xD04, 0xf, ofdm_rx_path);
359 #if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
360 else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
362 if (path == PHYDM_A) {
365 } else if (path == PHYDM_B) {
368 } else if (path == PHYDM_AB) {
373 odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path));
379 phydm_config_cck_rx_antenna_init(
380 struct PHY_DM_STRUCT *p_dm_odm
383 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
384 if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
386 /*CCK 2R CCA parameters*/
387 odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 1); /*enable 2R Rx path*/
388 odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 1); /*enable 2R MRC*/
389 odm_set_bb_reg(p_dm_odm, 0xa84, BIT(28), 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/
390 odm_set_bb_reg(p_dm_odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/
391 odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/
392 odm_set_bb_reg(p_dm_odm, 0xa08, BIT(28), 1); /* r_cck_2nd_sel_eco*/
393 odm_set_bb_reg(p_dm_odm, 0xa14, BIT(7), 0); /* r_en_mrc_antsel*/
399 phydm_config_cck_rx_path(
400 struct PHY_DM_STRUCT *p_dm_odm,
405 u8 path_div_select = 0;
406 u8 cck_1_path = 0, cck_2_path = 0;
408 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
409 if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
411 if (path == PHYDM_A) {
415 } else if (path == PHYDM_B) {
419 } else if (path == PHYDM_AB) {
421 if (path_div_en == CCA_PATHDIV_ENABLE)
429 odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(27) | BIT(26)), cck_1_path);
430 odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(25) | BIT(24)), cck_2_path);
431 odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), path_div_select);
438 phydm_config_trx_path(
446 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
447 u32 pre_support_ability;
449 u32 out_len = *_out_len;
452 if (dm_value[0] == 0) {
454 if (dm_value[1] == 1) { /*TX*/
455 if (dm_value[2] == 1)
456 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8);
457 else if (dm_value[2] == 2)
458 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4);
459 else if (dm_value[2] == 3)
460 odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc);
461 } else if (dm_value[1] == 2) { /*RX*/
463 phydm_config_cck_rx_antenna_init(p_dm_odm);
465 if (dm_value[2] == 1)
466 phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE);
467 else if (dm_value[2] == 2)
468 phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE);
469 else if (dm_value[2] == 3) {
470 if (dm_value[3] == 1) /*enable path diversity*/
471 phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE);
473 phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE);
478 else if (dm_value[0] == 1) {
480 if (dm_value[1] == 1) { /*TX*/
481 phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]);
483 } else if (dm_value[1] == 2) { /*RX*/
484 phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]);
489 PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
490 (dm_value[0] == 1) ? "OFDM" : "CCK",
491 (dm_value[1] == 1) ? "TX" : "RX",
492 (dm_value[2] & 0x1) ? "A" : "",
493 (dm_value[2] & 0x2) ? "B" : "",
494 (dm_value[2] & 0x4) ? "C" : "",
495 (dm_value[2] & 0x8) ? "D" : ""
501 phydm_init_cck_setting(
502 struct PHY_DM_STRUCT *p_dm_odm
505 u32 value_824, value_82c;
507 p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm));
509 #if (RTL8192E_SUPPORT == 1)
510 if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) {
511 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
512 phydm_config_cck_rx_antenna_init(p_dm_odm);
513 phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE);
516 /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */
517 value_824 = odm_get_bb_reg(p_dm_odm, 0x824, BIT(9));
518 value_82c = odm_get_bb_reg(p_dm_odm, 0x82c, BIT(9));
520 if (value_824 != value_82c)
521 odm_set_bb_reg(p_dm_odm, 0x82c, BIT(9), value_824);
522 odm_set_bb_reg(p_dm_odm, 0xa80, BIT(7), value_824);
523 p_dm_odm->cck_agc_report_type = (boolean)value_824;
525 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm_odm->cck_agc_report_type, p_dm_odm->ext_lna_gain));
528 /* JJ ADD 20161014 */
529 #if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
530 if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
532 p_dm_odm->cck_agc_report_type = odm_get_bb_reg(p_dm_odm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */
534 if (p_dm_odm->cck_agc_report_type != 1) {
535 dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n");
540 /* JJ ADD 20161014 */
541 #if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
542 if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B))
543 p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/
546 p_dm_odm->cck_new_agc = false;
552 phydm_dynamicsoftmletting(
553 struct PHY_DM_STRUCT *p_dm_odm
559 #if (RTL8822B_SUPPORT == 1)
560 if (p_dm_odm->mp_mode == FALSE) {
561 if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
563 if ((!p_dm_odm->is_linked)|(p_dm_odm->bLinkedcmw500))
566 if (TRUE == p_dm_odm->bsomlenabled) {
567 ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n"));
571 ret_val = odm_get_bb_reg(p_dm_odm, 0xf8c, bMaskByte0);
572 ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",ret_val));
574 if (ret_val < 0x16) {
575 ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_LOUD,("PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",ret_val));
576 odm_set_bb_reg(p_dm_odm, 0x19a8, bMaskDWord, 0xc10a0000);
577 p_dm_odm->bsomlenabled = TRUE;
587 phydm_init_soft_ml_setting(
588 struct PHY_DM_STRUCT *p_dm_odm
591 #if (RTL8822B_SUPPORT == 1)
592 if (p_dm_odm->mp_mode == false) {
593 if (p_dm_odm->support_ic_type & ODM_RTL8822B)
594 odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xc10a0000);
600 phydm_init_hw_info_by_rfe(
601 struct PHY_DM_STRUCT *p_dm_odm
604 #if (RTL8822B_SUPPORT == 1)
605 if (p_dm_odm->support_ic_type & ODM_RTL8822B)
606 phydm_init_hw_info_by_rfe_type_8822b(p_dm_odm);
608 #if (RTL8821C_SUPPORT == 1)
609 if (p_dm_odm->support_ic_type & ODM_RTL8821C)
610 phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm);
612 #if (RTL8197F_SUPPORT == 1)
613 if (p_dm_odm->support_ic_type & ODM_RTL8197F)
614 phydm_init_hw_info_by_rfe_type_8197f(p_dm_odm);
619 odm_common_info_self_init(
620 struct PHY_DM_STRUCT *p_dm_odm
623 phydm_init_cck_setting(p_dm_odm);
624 p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm));
625 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
626 p_dm_odm->p_is_net_closed = &p_dm_odm->BOOLEAN_temp;
628 phydm_init_debug_setting(p_dm_odm);
630 odm_init_mp_driver_status(p_dm_odm);
631 phydm_init_trx_antenna_setting(p_dm_odm);
632 phydm_init_soft_ml_setting(p_dm_odm);
634 p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
635 p_dm_odm->phydm_sys_up_time = 0;
637 if (p_dm_odm->support_ic_type & ODM_IC_1SS)
638 p_dm_odm->num_rf_path = 1;
639 else if (p_dm_odm->support_ic_type & ODM_IC_2SS)
640 p_dm_odm->num_rf_path = 2;
641 else if (p_dm_odm->support_ic_type & ODM_IC_3SS)
642 p_dm_odm->num_rf_path = 3;
643 else if (p_dm_odm->support_ic_type & ODM_IC_4SS)
644 p_dm_odm->num_rf_path = 4;
646 p_dm_odm->tx_rate = 0xFF;
648 p_dm_odm->number_linked_client = 0;
649 p_dm_odm->pre_number_linked_client = 0;
650 p_dm_odm->number_active_client = 0;
651 p_dm_odm->pre_number_active_client = 0;
653 p_dm_odm->last_tx_ok_cnt = 0;
654 p_dm_odm->last_rx_ok_cnt = 0;
657 p_dm_odm->total_tp = 0;
658 p_dm_odm->traffic_load = TRAFFIC_LOW;
660 p_dm_odm->nbi_set_result = 0;
661 p_dm_odm->is_init_hw_info_by_rfe = false;
662 p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE;
667 odm_common_info_self_update(
668 struct PHY_DM_STRUCT *p_dm_odm
671 u8 entry_cnt = 0, num_active_client = 0;
672 u32 i, one_entry_macid = 0, ma_rx_tp = 0;
673 struct sta_info *p_entry;
675 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
677 struct _ADAPTER *adapter = p_dm_odm->adapter;
678 PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
680 p_entry = p_dm_odm->p_odm_sta_info[0];
681 if (p_mgnt_info->mAssoc) {
682 p_entry->bUsed = true;
683 for (i = 0; i < 6; i++)
684 p_entry->MacAddr[i] = p_mgnt_info->Bssid[i];
685 } else if (GetFirstClientPort(adapter)) {
686 struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter);
688 p_entry->bUsed = true;
689 for (i = 0; i < 6; i++)
690 p_entry->MacAddr[i] = p_client_adapter->MgntInfo.Bssid[i];
692 p_entry->bUsed = false;
693 for (i = 0; i < 6; i++)
694 p_entry->MacAddr[i] = 0;
697 /* STA mode is linked to AP */
698 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[0]) && !ACTING_AS_AP(adapter))
699 p_dm_odm->bsta_state = true;
701 p_dm_odm->bsta_state = false;
704 /* THis variable cannot be used because it is wrong*/
705 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
706 if (*(p_dm_odm->p_band_width) == ODM_BW40M) {
707 if (*(p_dm_odm->p_sec_ch_offset) == 1)
708 p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2;
709 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
710 p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2;
711 } else if (*(p_dm_odm->p_band_width) == ODM_BW80M) {
712 if (*(p_dm_odm->p_sec_ch_offset) == 1)
713 p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 6;
714 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
715 p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 6;
717 p_dm_odm->control_channel = *(p_dm_odm->p_channel);
719 if (*(p_dm_odm->p_band_width) == ODM_BW40M) {
720 if (*(p_dm_odm->p_sec_ch_offset) == 1)
721 p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2;
722 else if (*(p_dm_odm->p_sec_ch_offset) == 2)
723 p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2;
725 p_dm_odm->control_channel = *(p_dm_odm->p_channel);
728 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
729 p_entry = p_dm_odm->p_odm_sta_info[i];
730 if (IS_STA_VALID(p_entry)) {
735 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
736 ma_rx_tp = (p_entry->rx_byte_cnt_low_maw) << 3; /* low moving average RX TP ( bit /sec)*/
738 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp));
740 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
746 if (entry_cnt == 1) {
747 p_dm_odm->is_one_entry_only = true;
748 p_dm_odm->one_entry_macid = one_entry_macid;
750 p_dm_odm->is_one_entry_only = false;
752 p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client;
753 p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client;
755 p_dm_odm->number_linked_client = entry_cnt;
756 p_dm_odm->number_active_client = num_active_client;
758 /* Update MP driver status*/
759 odm_update_mp_driver_status(p_dm_odm);
761 /*Traffic load information update*/
762 phydm_traffic_load_decision(p_dm_odm);
764 p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period;
768 odm_common_info_self_reset(
769 struct PHY_DM_STRUCT *p_dm_odm
772 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
773 p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0;
779 struct PHY_DM_STRUCT *p_dm_odm,
784 void *p_struct = NULL;
786 switch (structure_type) {
787 case PHYDM_FALSEALMCNT:
788 p_struct = &false_alm_cnt;
792 p_struct = &dm_cfo_track;
795 case PHYDM_ADAPTIVITY:
796 p_struct = &(p_dm_odm->adaptivity);
804 switch (structure_type) {
805 case PHYDM_FALSEALMCNT:
806 p_struct = &(p_dm_odm->false_alm_cnt);
810 p_struct = &(p_dm_odm->dm_cfo_track);
813 case PHYDM_ADAPTIVITY:
814 p_struct = &(p_dm_odm->adaptivity);
827 struct PHY_DM_STRUCT *p_dm_odm
830 #if (RTL8821A_SUPPORT == 1)
831 if (p_dm_odm->support_ic_type & ODM_RTL8821)
832 odm_hw_setting_8821a(p_dm_odm);
835 #if (RTL8814A_SUPPORT == 1)
836 if (p_dm_odm->support_ic_type & ODM_RTL8814A)
837 phydm_hwsetting_8814a(p_dm_odm);
840 #if (RTL8822B_SUPPORT == 1)
841 if (p_dm_odm->support_ic_type & ODM_RTL8822B)
842 phydm_hwsetting_8822b(p_dm_odm);
845 #if (RTL8197F_SUPPORT == 1)
846 if (p_dm_odm->support_ic_type & ODM_RTL8197F)
847 phydm_hwsetting_8197f(p_dm_odm);
850 #if SUPPORTABLITY_PHYDMLIZE
852 phydm_supportability_init(
856 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
857 u32 support_ability = 0;
858 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
859 struct _ADAPTER *adapter = p_dm_odm->adapter;
860 PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
863 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
864 if (p_dm_odm->support_ic_type != ODM_RTL8821C)
868 switch (p_dm_odm->support_ic_type) {
870 /*---------------N Series--------------------*/
875 ODM_BB_DYNAMIC_TXPWR |
877 ODM_BB_RSSI_MONITOR |
879 ODM_RF_TX_PWR_TRACK |
880 ODM_RF_RX_GAIN_TRACK |
882 ODM_BB_CFO_TRACKING |
890 ODM_RF_TX_PWR_TRACK |
893 ODM_BB_RSSI_MONITOR |
894 ODM_BB_CFO_TRACKING |
895 /* ODM_BB_PWR_TRAIN |*/
905 ODM_BB_RSSI_MONITOR |
907 ODM_RF_TX_PWR_TRACK |
908 ODM_RF_RX_GAIN_TRACK |
910 ODM_BB_CFO_TRACKING |
911 /* ODM_BB_PWR_TRAIN |*/
920 ODM_BB_RSSI_MONITOR |
922 ODM_BB_CFO_TRACKING |
923 /* ODM_BB_PWR_TRAIN | */
925 ODM_RF_TX_PWR_TRACK |
926 /* ODM_RF_RX_GAIN_TRACK | */
935 ODM_BB_RSSI_MONITOR |
937 ODM_BB_CFO_TRACKING |
938 /* ODM_BB_PWR_TRAIN | */
941 /* ODM_RF_RX_GAIN_TRACK | */
942 /* ODM_RF_CALIBRATION | */
944 /* JJ ADD 20161014 */
950 ODM_BB_RSSI_MONITOR |
952 ODM_BB_CFO_TRACKING |
953 /* ODM_BB_PWR_TRAIN | */
956 /* ODM_RF_RX_GAIN_TRACK | */
957 /* ODM_RF_CALIBRATION | */
965 ODM_BB_RSSI_MONITOR |
967 ODM_BB_CFO_TRACKING |
969 ODM_RF_TX_PWR_TRACK |
973 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
980 ODM_BB_RSSI_MONITOR |
982 ODM_BB_CFO_TRACKING |
984 ODM_RF_TX_PWR_TRACK |
989 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
995 ODM_BB_RSSI_MONITOR |
997 ODM_BB_CFO_TRACKING |
999 ODM_RF_TX_PWR_TRACK |
1004 /*---------------AC Series-------------------*/
1012 ODM_BB_RSSI_MONITOR |
1014 ODM_RF_TX_PWR_TRACK |
1015 ODM_BB_CFO_TRACKING |
1016 /* ODM_BB_PWR_TRAIN |*/
1017 ODM_BB_DYNAMIC_TXPWR |
1026 ODM_BB_RSSI_MONITOR |
1028 ODM_RF_TX_PWR_TRACK |
1030 ODM_BB_CFO_TRACKING |
1031 ODM_BB_DYNAMIC_TXPWR |
1040 ODM_BB_CFO_TRACKING |
1041 ODM_BB_RATE_ADAPTIVE |
1042 ODM_BB_RSSI_MONITOR |
1044 ODM_RF_TX_PWR_TRACK;
1053 ODM_BB_RSSI_MONITOR |
1054 ODM_BB_RATE_ADAPTIVE |
1055 ODM_RF_TX_PWR_TRACK |
1056 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1057 ODM_MAC_EDCA_TURBO |
1059 ODM_BB_CFO_TRACKING; /* |
1060 * ODM_BB_DYNAMIC_TXPWR |
1069 ODM_BB_CFO_TRACKING |
1070 ODM_BB_RATE_ADAPTIVE |
1071 ODM_BB_RSSI_MONITOR |
1073 ODM_RF_TX_PWR_TRACK;
1075 dbg_print("[Warning] Supportability Init Warning !!!\n");
1080 if (*(p_dm_odm->p_enable_antdiv))
1081 support_ability |= ODM_BB_ANT_DIV;
1083 if (*(p_dm_odm->p_enable_adaptivity)) {
1085 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to Enabled!!!\n"));
1087 support_ability |= ODM_BB_ADAPTIVITY;
1089 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1090 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, p_mgnt_info->RegEnableCarrierSense);
1091 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DCBACKOFF, p_mgnt_info->RegDCbackoff);
1092 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, p_mgnt_info->RegDmLinkAdaptivity);
1093 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_AP_NUM_TH, p_mgnt_info->RegAPNumTH);
1094 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_L2H_INI, p_mgnt_info->RegL2HForAdaptivity);
1095 phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, p_mgnt_info->RegHLDiffForAdaptivity);
1099 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to disnabled!!!\n"));
1103 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHYDM support_ability = ((0x%x))\n", support_ability));
1104 odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability);
1109 * 2011/09/21 MH Add to describe different team necessary resource allocate??
1113 struct PHY_DM_STRUCT *p_dm_odm
1116 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1117 struct _ADAPTER *adapter = p_dm_odm->adapter;
1118 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
1121 #if SUPPORTABLITY_PHYDMLIZE
1122 phydm_supportability_init(p_dm_odm);
1124 odm_common_info_self_init(p_dm_odm);
1125 odm_dig_init(p_dm_odm);
1126 phydm_nhm_counter_statistics_init(p_dm_odm);
1127 phydm_adaptivity_init(p_dm_odm);
1128 phydm_ra_info_init(p_dm_odm);
1129 odm_rate_adaptive_mask_init(p_dm_odm);
1130 odm_cfo_tracking_init(p_dm_odm);
1131 #if PHYDM_SUPPORT_EDCA
1132 odm_edca_turbo_init(p_dm_odm);
1134 odm_rssi_monitor_init(p_dm_odm);
1135 phydm_rf_init(p_dm_odm);
1136 odm_txpowertracking_init(p_dm_odm);
1138 #if (RTL8822B_SUPPORT == 1)
1139 if (p_dm_odm->support_ic_type & ODM_RTL8822B)
1140 phydm_txcurrentcalibration(p_dm_odm);
1143 odm_antenna_diversity_init(p_dm_odm);
1144 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1145 phydm_dynamic_rx_path_init(p_dm_odm);
1147 odm_auto_channel_select_init(p_dm_odm);
1148 odm_path_diversity_init(p_dm_odm);
1149 odm_dynamic_tx_power_init(p_dm_odm);
1150 phydm_init_ra_info(p_dm_odm);
1151 #if (PHYDM_LA_MODE_SUPPORT == 1)
1152 adc_smp_init(p_dm_odm);
1155 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1156 #ifdef BEAMFORMING_VERSION_1
1157 if (p_hal_data->beamforming_version == BEAMFORMING_VERSION_1)
1160 phydm_beamforming_init(p_dm_odm);
1164 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
1165 #if (defined(CONFIG_BB_POWER_SAVING))
1166 odm_dynamic_bb_power_saving_init(p_dm_odm);
1169 #if (RTL8188E_SUPPORT == 1)
1170 if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
1171 odm_primary_cca_init(p_dm_odm);
1172 odm_ra_info_init_all(p_dm_odm);
1176 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1178 #if (RTL8723B_SUPPORT == 1)
1179 if (p_dm_odm->support_ic_type == ODM_RTL8723B)
1180 odm_sw_ant_detect_init(p_dm_odm);
1183 #if (RTL8192E_SUPPORT == 1)
1184 if (p_dm_odm->support_ic_type == ODM_RTL8192E)
1185 odm_primary_cca_check_init(p_dm_odm);
1192 #if (CONFIG_PSD_TOOL == 1)
1193 phydm_psd_init(p_dm_odm);
1200 struct PHY_DM_STRUCT *p_dm_odm
1203 struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
1205 odm_ant_div_reset(p_dm_odm);
1206 phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);
1211 phydm_support_ability_debug(
1213 u32 *const dm_value,
1219 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
1220 u32 pre_support_ability;
1222 u32 out_len = *_out_len;
1224 pre_support_ability = p_dm_odm->support_ability ;
1225 PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================"));
1226 if (dm_value[0] == 100) {
1227 PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n"));
1228 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1229 PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : ("."))));
1230 PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : ("."))));
1231 PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))));
1232 PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : ("."))));
1233 PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))));
1234 PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : ("."))));
1235 PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : ("."))));
1236 PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : ("."))));
1237 PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))));
1238 PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : ("."))));
1239 PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : ("."))));
1240 PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : ("."))));
1241 PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : ("."))));
1242 PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))));
1243 PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : ("."))));
1244 PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))));
1245 PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : ("."))));
1246 PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : ("."))));
1247 PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK) ? ("V") : ("."))));
1248 PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_RX_GAIN_TRACK) ? ("V") : ("."))));
1249 PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))RF_CALIBRATION\n", ((p_dm_odm->support_ability & ODM_RF_CALIBRATION) ? ("V") : ("."))));
1250 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1253 else if(dm_value[0] == 101)
1255 p_dm_odm->support_ability = 0 ;
1256 dbg_print("Disable all support_ability components\n");
1257 PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components"));
1262 if (dm_value[1] == 1) { /* enable */
1263 p_dm_odm->support_ability |= BIT(dm_value[0]) ;
1264 if (BIT(dm_value[0]) & ODM_BB_PATH_DIV)
1265 odm_path_diversity_init(p_dm_odm);
1266 } else if (dm_value[1] == 2) /* disable */
1267 p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ;
1269 /* dbg_print("\n[Warning!!!] 1:enable, 2:disable \n\n"); */
1270 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable"));
1273 PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%x\n", pre_support_ability));
1274 PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%x\n", p_dm_odm->support_ability));
1275 PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================"));
1278 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1280 * tmp modify for LC Only
1283 odm_dm_watchdog_lps(
1284 struct PHY_DM_STRUCT *p_dm_odm
1287 odm_common_info_self_update(p_dm_odm);
1288 odm_false_alarm_counter_statistics(p_dm_odm);
1289 odm_rssi_monitor_check(p_dm_odm);
1290 odm_dig_by_rssi_lps(p_dm_odm);
1291 odm_cck_packet_detection_thresh(p_dm_odm);
1292 odm_common_info_self_reset(p_dm_odm);
1294 if (*(p_dm_odm->p_is_power_saving) == true)
1301 struct PHY_DM_STRUCT *p_dm_odm
1304 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1305 phydm_dynamic_rx_path_caller(p_dm_odm);
1309 * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
1310 * You can not add any dummy function here, be care, you can only use DM structure
1311 * to perform any new ODM_DM.
1315 struct PHY_DM_STRUCT *p_dm_odm
1318 odm_common_info_self_update(p_dm_odm);
1319 phydm_basic_dbg_message(p_dm_odm);
1320 odm_hw_setting(p_dm_odm);
1322 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1324 struct rtl8192cd_priv *priv = p_dm_odm->priv;
1325 if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct _ACS_ running, do not do FA/CCA counter read */
1329 odm_false_alarm_counter_statistics(p_dm_odm);
1330 phydm_noisy_detection(p_dm_odm);
1332 odm_rssi_monitor_check(p_dm_odm);
1334 if (*(p_dm_odm->p_is_power_saving) == true) {
1335 odm_dig_by_rssi_lps(p_dm_odm);
1336 phydm_adaptivity(p_dm_odm);
1337 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1338 odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
1340 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n"));
1344 phydm_check_adaptivity(p_dm_odm);
1345 odm_update_power_training_state(p_dm_odm);
1347 phydm_adaptivity(p_dm_odm);
1348 odm_cck_packet_detection_thresh(p_dm_odm);
1350 phydm_ra_info_watchdog(p_dm_odm);
1351 #if PHYDM_SUPPORT_EDCA
1352 odm_edca_turbo_check(p_dm_odm);
1354 odm_path_diversity(p_dm_odm);
1355 odm_cfo_tracking(p_dm_odm);
1356 odm_dynamic_tx_power(p_dm_odm);
1357 odm_antenna_diversity(p_dm_odm);
1358 #if (CONFIG_DYNAMIC_RX_PATH == 1)
1359 phydm_dynamic_rx_path(p_dm_odm);
1362 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1363 phydm_beamforming_watchdog(p_dm_odm);
1366 phydm_rf_watchdog(p_dm_odm);
1368 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
1370 #if (RTL8188E_SUPPORT == 1)
1371 if (p_dm_odm->support_ic_type == ODM_RTL8188E)
1372 odm_dynamic_primary_cca(p_dm_odm);
1375 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1377 #if (RTL8192E_SUPPORT == 1)
1378 if (p_dm_odm->support_ic_type == ODM_RTL8192E)
1379 odm_dynamic_primary_cca_check(p_dm_odm);
1384 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1388 odm_common_info_self_reset(p_dm_odm);
1394 * Init /.. Fixed HW value. Only init time.
1398 struct PHY_DM_STRUCT *p_dm_odm,
1399 enum odm_cmninfo_e cmn_info,
1404 /* This section is used for init value */
1408 /* Fixed ODM value. */
1410 case ODM_CMNINFO_ABILITY:
1411 p_dm_odm->support_ability = (u32)value;
1414 case ODM_CMNINFO_RF_TYPE:
1415 p_dm_odm->rf_type = (u8)value;
1418 case ODM_CMNINFO_PLATFORM:
1419 p_dm_odm->support_platform = (u8)value;
1422 case ODM_CMNINFO_INTERFACE:
1423 p_dm_odm->support_interface = (u8)value;
1426 case ODM_CMNINFO_MP_TEST_CHIP:
1427 p_dm_odm->is_mp_chip = (u8)value;
1430 case ODM_CMNINFO_IC_TYPE:
1431 p_dm_odm->support_ic_type = value;
1434 case ODM_CMNINFO_CUT_VER:
1435 p_dm_odm->cut_version = (u8)value;
1438 case ODM_CMNINFO_FAB_VER:
1439 p_dm_odm->fab_version = (u8)value;
1442 case ODM_CMNINFO_RFE_TYPE:
1443 p_dm_odm->rfe_type = (u8)value;
1444 phydm_init_hw_info_by_rfe(p_dm_odm);
1447 case ODM_CMNINFO_DPK_EN:
1448 p_dm_odm->dpk_en = (u1Byte)value;
1450 case ODM_CMNINFO_RF_ANTENNA_TYPE:
1451 p_dm_odm->ant_div_type = (u8)value;
1454 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
1455 p_dm_odm->with_extenal_ant_switch = (u8)value;
1458 case ODM_CMNINFO_BE_FIX_TX_ANT:
1459 p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value;
1462 case ODM_CMNINFO_BOARD_TYPE:
1463 if (!p_dm_odm->is_init_hw_info_by_rfe)
1464 p_dm_odm->board_type = (u8)value;
1467 case ODM_CMNINFO_PACKAGE_TYPE:
1468 if (!p_dm_odm->is_init_hw_info_by_rfe)
1469 p_dm_odm->package_type = (u8)value;
1472 case ODM_CMNINFO_EXT_LNA:
1473 if (!p_dm_odm->is_init_hw_info_by_rfe)
1474 p_dm_odm->ext_lna = (u8)value;
1477 case ODM_CMNINFO_5G_EXT_LNA:
1478 if (!p_dm_odm->is_init_hw_info_by_rfe)
1479 p_dm_odm->ext_lna_5g = (u8)value;
1482 case ODM_CMNINFO_EXT_PA:
1483 if (!p_dm_odm->is_init_hw_info_by_rfe)
1484 p_dm_odm->ext_pa = (u8)value;
1487 case ODM_CMNINFO_5G_EXT_PA:
1488 if (!p_dm_odm->is_init_hw_info_by_rfe)
1489 p_dm_odm->ext_pa_5g = (u8)value;
1492 case ODM_CMNINFO_GPA:
1493 if (!p_dm_odm->is_init_hw_info_by_rfe)
1494 p_dm_odm->type_gpa = (u16)value;
1497 case ODM_CMNINFO_APA:
1498 if (!p_dm_odm->is_init_hw_info_by_rfe)
1499 p_dm_odm->type_apa = (u16)value;
1502 case ODM_CMNINFO_GLNA:
1503 if (!p_dm_odm->is_init_hw_info_by_rfe)
1504 p_dm_odm->type_glna = (u16)value;
1507 case ODM_CMNINFO_ALNA:
1508 if (!p_dm_odm->is_init_hw_info_by_rfe)
1509 p_dm_odm->type_alna = (u16)value;
1512 case ODM_CMNINFO_EXT_TRSW:
1513 if (!p_dm_odm->is_init_hw_info_by_rfe)
1514 p_dm_odm->ext_trsw = (u8)value;
1516 case ODM_CMNINFO_EXT_LNA_GAIN:
1517 p_dm_odm->ext_lna_gain = (u8)value;
1519 case ODM_CMNINFO_PATCH_ID:
1520 p_dm_odm->patch_id = (u8)value;
1522 case ODM_CMNINFO_BINHCT_TEST:
1523 p_dm_odm->is_in_hct_test = (boolean)value;
1525 case ODM_CMNINFO_BWIFI_TEST:
1526 p_dm_odm->wifi_test = (u8)value;
1528 case ODM_CMNINFO_SMART_CONCURRENT:
1529 p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value;
1531 case ODM_CMNINFO_DOMAIN_CODE_2G:
1532 p_dm_odm->odm_regulation_2_4g = (u8)value;
1534 case ODM_CMNINFO_DOMAIN_CODE_5G:
1535 p_dm_odm->odm_regulation_5g = (u8)value;
1537 case ODM_CMNINFO_CONFIG_BB_RF:
1538 p_dm_odm->config_bbrf = (boolean)value;
1540 case ODM_CMNINFO_IQKFWOFFLOAD:
1541 p_dm_odm->iqk_fw_offload = (u8)value;
1543 case ODM_CMNINFO_IQKPAOFF:
1544 p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
1546 case ODM_CMNINFO_REGRFKFREEENABLE:
1547 p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
1549 case ODM_CMNINFO_RFKFREEENABLE:
1550 p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value;
1552 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
1553 p_dm_odm->normal_rx_path = (u8)value;
1555 case ODM_CMNINFO_EFUSE0X3D8:
1556 p_dm_odm->efuse0x3d8 = (u8)value;
1558 case ODM_CMNINFO_EFUSE0X3D7:
1559 p_dm_odm->efuse0x3d7 = (u8)value;
1561 #ifdef CONFIG_PHYDM_DFS_MASTER
1562 case ODM_CMNINFO_DFS_REGION_DOMAIN:
1563 p_dm_odm->dfs_region_domain = (u8)value;
1566 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
1578 struct PHY_DM_STRUCT *p_dm_odm,
1579 enum odm_cmninfo_e cmn_info,
1584 /* Hook call by reference pointer. */
1588 /* Dynamic call by reference pointer. */
1590 case ODM_CMNINFO_MAC_PHY_MODE:
1591 p_dm_odm->p_mac_phy_mode = (u8 *)p_value;
1594 case ODM_CMNINFO_TX_UNI:
1595 p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value;
1598 case ODM_CMNINFO_RX_UNI:
1599 p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value;
1602 case ODM_CMNINFO_WM_MODE:
1603 p_dm_odm->p_wireless_mode = (u8 *)p_value;
1606 case ODM_CMNINFO_BAND:
1607 p_dm_odm->p_band_type = (u8 *)p_value;
1610 case ODM_CMNINFO_SEC_CHNL_OFFSET:
1611 p_dm_odm->p_sec_ch_offset = (u8 *)p_value;
1614 case ODM_CMNINFO_SEC_MODE:
1615 p_dm_odm->p_security = (u8 *)p_value;
1618 case ODM_CMNINFO_BW:
1619 p_dm_odm->p_band_width = (u8 *)p_value;
1622 case ODM_CMNINFO_CHNL:
1623 p_dm_odm->p_channel = (u8 *)p_value;
1626 case ODM_CMNINFO_DMSP_GET_VALUE:
1627 p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value;
1630 case ODM_CMNINFO_BUDDY_ADAPTOR:
1631 p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value;
1634 case ODM_CMNINFO_DMSP_IS_MASTER:
1635 p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value;
1638 case ODM_CMNINFO_SCAN:
1639 p_dm_odm->p_is_scan_in_process = (boolean *)p_value;
1642 case ODM_CMNINFO_POWER_SAVING:
1643 p_dm_odm->p_is_power_saving = (boolean *)p_value;
1646 case ODM_CMNINFO_ONE_PATH_CCA:
1647 p_dm_odm->p_one_path_cca = (u8 *)p_value;
1650 case ODM_CMNINFO_DRV_STOP:
1651 p_dm_odm->p_is_driver_stopped = (boolean *)p_value;
1654 case ODM_CMNINFO_PNP_IN:
1655 p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value;
1658 case ODM_CMNINFO_INIT_ON:
1659 p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value;
1662 case ODM_CMNINFO_ANT_TEST:
1663 p_dm_odm->p_antenna_test = (u8 *)p_value;
1666 case ODM_CMNINFO_NET_CLOSED:
1667 p_dm_odm->p_is_net_closed = (boolean *)p_value;
1670 case ODM_CMNINFO_FORCED_RATE:
1671 p_dm_odm->p_forced_data_rate = (u16 *)p_value;
1673 case ODM_CMNINFO_ANT_DIV:
1674 p_dm_odm->p_enable_antdiv = (u8 *)p_value;
1676 case ODM_CMNINFO_ADAPTIVITY:
1677 p_dm_odm->p_enable_adaptivity = (u8 *)p_value;
1679 case ODM_CMNINFO_FORCED_IGI_LB:
1680 p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value;
1683 case ODM_CMNINFO_P2P_LINK:
1684 p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value;
1687 case ODM_CMNINFO_IS1ANTENNA:
1688 p_dm_odm->p_is_1_antenna = (boolean *)p_value;
1691 case ODM_CMNINFO_RFDEFAULTPATH:
1692 p_dm_odm->p_rf_default_path = (u8 *)p_value;
1695 case ODM_CMNINFO_FCS_MODE:
1696 p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value;
1698 /*add by YuChen for beamforming PhyDM*/
1699 case ODM_CMNINFO_HUBUSBMODE:
1700 p_dm_odm->hub_usb_mode = (u8 *)p_value;
1702 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
1703 p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value;
1705 case ODM_CMNINFO_TX_TP:
1706 p_dm_odm->p_current_tx_tp = (u32 *)p_value;
1708 case ODM_CMNINFO_RX_TP:
1709 p_dm_odm->p_current_rx_tp = (u32 *)p_value;
1711 case ODM_CMNINFO_SOUNDING_SEQ:
1712 p_dm_odm->p_sounding_seq = (u8 *)p_value;
1714 #ifdef CONFIG_PHYDM_DFS_MASTER
1715 case ODM_CMNINFO_DFS_MASTER_ENABLE:
1716 p_dm_odm->dfs_master_enabled = (u8 *)p_value;
1719 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
1720 p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value;
1722 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
1723 p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value;
1736 odm_cmn_info_ptr_array_hook(
1737 struct PHY_DM_STRUCT *p_dm_odm,
1738 enum odm_cmninfo_e cmn_info,
1743 /*Hook call by reference pointer.*/
1745 /*Dynamic call by reference pointer. */
1746 case ODM_CMNINFO_STA_STATUS:
1747 p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value;
1749 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index]))
1750 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1751 p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->AssociatedMacId] = index; /*associated_mac_id are unique bttween different adapter*/
1752 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1753 p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->aid] = index;
1754 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1755 p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index;
1759 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
1769 * Update band/CHannel/.. The values are dynamic but non-per-packet.
1772 odm_cmn_info_update(
1773 struct PHY_DM_STRUCT *p_dm_odm,
1779 /* This init variable may be changed in run time. */
1782 case ODM_CMNINFO_LINK_IN_PROGRESS:
1783 p_dm_odm->is_link_in_process = (boolean)value;
1786 case ODM_CMNINFO_ABILITY:
1787 p_dm_odm->support_ability = (u32)value;
1790 case ODM_CMNINFO_RF_TYPE:
1791 p_dm_odm->rf_type = (u8)value;
1794 case ODM_CMNINFO_WIFI_DIRECT:
1795 p_dm_odm->is_wifi_direct = (boolean)value;
1798 case ODM_CMNINFO_WIFI_DISPLAY:
1799 p_dm_odm->is_wifi_display = (boolean)value;
1802 case ODM_CMNINFO_LINK:
1803 p_dm_odm->is_linked = (boolean)value;
1806 case ODM_CMNINFO_CMW500LINK:
1807 p_dm_odm->bLinkedcmw500 = (boolean)value;
1810 case ODM_CMNINFO_LPSPG:
1811 p_dm_odm->is_in_lps_pg = (boolean)value;
1814 case ODM_CMNINFO_STATION_STATE:
1815 p_dm_odm->bsta_state = (boolean)value;
1818 case ODM_CMNINFO_RSSI_MIN:
1819 p_dm_odm->rssi_min = (u8)value;
1822 case ODM_CMNINFO_DBG_COMP:
1823 p_dm_odm->debug_components = (u32)value;
1826 case ODM_CMNINFO_DBG_LEVEL:
1827 p_dm_odm->debug_level = (u32)value;
1829 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
1830 p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value;
1833 case ODM_CMNINFO_RA_THRESHOLD_LOW:
1834 p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value;
1836 #if defined(BT_SUPPORT) && (BT_SUPPORT == 1)
1837 /* The following is for BT HS mode and BT coexist mechanism. */
1838 case ODM_CMNINFO_BT_ENABLED:
1839 p_dm_odm->is_bt_enabled = (boolean)value;
1842 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1843 p_dm_odm->is_bt_connect_process = (boolean)value;
1846 case ODM_CMNINFO_BT_HS_RSSI:
1847 p_dm_odm->bt_hs_rssi = (u8)value;
1850 case ODM_CMNINFO_BT_OPERATION:
1851 p_dm_odm->is_bt_hs_operation = (boolean)value;
1854 case ODM_CMNINFO_BT_LIMITED_DIG:
1855 p_dm_odm->is_bt_limited_dig = (boolean)value;
1858 case ODM_CMNINFO_BT_DIG:
1859 p_dm_odm->bt_hs_dig_val = (u8)value;
1862 case ODM_CMNINFO_BT_BUSY:
1863 p_dm_odm->is_bt_busy = (boolean)value;
1866 case ODM_CMNINFO_BT_DISABLE_EDCA:
1867 p_dm_odm->is_bt_disable_edca_turbo = (boolean)value;
1871 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) /* for repeater mode add by YuChen 2014.06.23 */
1872 #ifdef UNIVERSAL_REPEATER
1873 case ODM_CMNINFO_VXD_LINK:
1874 p_dm_odm->vxd_linked = (boolean)value;
1879 case ODM_CMNINFO_AP_TOTAL_NUM:
1880 p_dm_odm->ap_total_num = (u8)value;
1883 case ODM_CMNINFO_POWER_TRAINING:
1884 p_dm_odm->is_disable_power_training = (boolean)value;
1887 #ifdef CONFIG_PHYDM_DFS_MASTER
1888 case ODM_CMNINFO_DFS_REGION_DOMAIN:
1889 p_dm_odm->dfs_region_domain = (u8)value;
1894 case ODM_CMNINFO_OP_MODE:
1895 p_dm_odm->op_mode = (u8)value;
1898 case ODM_CMNINFO_WM_MODE:
1899 p_dm_odm->wireless_mode = (u8)value;
1902 case ODM_CMNINFO_BAND:
1903 p_dm_odm->band_type = (u8)value;
1906 case ODM_CMNINFO_SEC_CHNL_OFFSET:
1907 p_dm_odm->sec_ch_offset = (u8)value;
1910 case ODM_CMNINFO_SEC_MODE:
1911 p_dm_odm->security = (u8)value;
1914 case ODM_CMNINFO_BW:
1915 p_dm_odm->band_width = (u8)value;
1918 case ODM_CMNINFO_CHNL:
1919 p_dm_odm->channel = (u8)value;
1931 phydm_cmn_info_query(
1932 struct PHY_DM_STRUCT *p_dm_odm,
1933 enum phydm_info_query_e info_type
1936 struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
1938 switch (info_type) {
1939 case PHYDM_INFO_FA_OFDM:
1940 return false_alm_cnt->cnt_ofdm_fail;
1942 case PHYDM_INFO_FA_CCK:
1943 return false_alm_cnt->cnt_cck_fail;
1945 case PHYDM_INFO_FA_TOTAL:
1946 return false_alm_cnt->cnt_all;
1948 case PHYDM_INFO_CCA_OFDM:
1949 return false_alm_cnt->cnt_ofdm_cca;
1951 case PHYDM_INFO_CCA_CCK:
1952 return false_alm_cnt->cnt_cck_cca;
1954 case PHYDM_INFO_CCA_ALL:
1955 return false_alm_cnt->cnt_cca_all;
1957 case PHYDM_INFO_CRC32_OK_VHT:
1958 return false_alm_cnt->cnt_vht_crc32_ok;
1960 case PHYDM_INFO_CRC32_OK_HT:
1961 return false_alm_cnt->cnt_ht_crc32_ok;
1963 case PHYDM_INFO_CRC32_OK_LEGACY:
1964 return false_alm_cnt->cnt_ofdm_crc32_ok;
1966 case PHYDM_INFO_CRC32_OK_CCK:
1967 return false_alm_cnt->cnt_cck_crc32_ok;
1969 case PHYDM_INFO_CRC32_ERROR_VHT:
1970 return false_alm_cnt->cnt_vht_crc32_error;
1972 case PHYDM_INFO_CRC32_ERROR_HT:
1973 return false_alm_cnt->cnt_ht_crc32_error;
1975 case PHYDM_INFO_CRC32_ERROR_LEGACY:
1976 return false_alm_cnt->cnt_ofdm_crc32_error;
1978 case PHYDM_INFO_CRC32_ERROR_CCK:
1979 return false_alm_cnt->cnt_cck_crc32_error;
1981 case PHYDM_INFO_EDCCA_FLAG:
1982 return false_alm_cnt->edcca_flag;
1984 case PHYDM_INFO_OFDM_ENABLE:
1985 return false_alm_cnt->ofdm_block_enable;
1987 case PHYDM_INFO_CCK_ENABLE:
1988 return false_alm_cnt->cck_block_enable;
1990 case PHYDM_INFO_DBG_PORT_0:
1991 return false_alm_cnt->dbg_port0;
2000 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2002 odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm)
2005 struct _ADAPTER *p_adapter = p_dm_odm->adapter;
2008 #if CONFIG_DYNAMIC_RX_PATH
2009 odm_initialize_work_item(p_dm_odm,
2010 &p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem,
2011 (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback,
2013 "DynamicRxPathWorkitem");
2016 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2017 odm_initialize_work_item(p_dm_odm,
2018 &p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2019 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2021 "AntennaSwitchWorkitem");
2023 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
2024 odm_initialize_work_item(p_dm_odm,
2025 &p_dm_odm->dm_sat_table.hl_smart_antenna_workitem,
2026 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
2028 "hl_smart_ant_workitem");
2030 odm_initialize_work_item(p_dm_odm,
2031 &p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem,
2032 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
2034 "hl_smart_ant_decision_workitem");
2037 odm_initialize_work_item(
2039 &(p_dm_odm->path_div_switch_workitem),
2040 (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback,
2044 odm_initialize_work_item(
2046 &(p_dm_odm->cck_path_diversity_workitem),
2047 (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback,
2049 "CCKTXPathDiversityWorkItem");
2051 odm_initialize_work_item(
2053 &(p_dm_odm->mpt_dig_workitem),
2054 (RT_WORKITEM_CALL_BACK)odm_mpt_dig_work_item_callback,
2056 "mpt_dig_workitem");
2058 odm_initialize_work_item(
2060 &(p_dm_odm->ra_rpt_workitem),
2061 (RT_WORKITEM_CALL_BACK)odm_update_init_rate_work_item_callback,
2065 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2066 odm_initialize_work_item(
2068 &(p_dm_odm->fast_ant_training_workitem),
2069 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
2071 "fast_ant_training_workitem");
2074 #endif /*#if USE_WORKITEM*/
2076 #if (BEAMFORMING_SUPPORT == 1)
2077 odm_initialize_work_item(
2079 &(p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item),
2080 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
2082 "txbf_enter_work_item");
2084 odm_initialize_work_item(
2086 &(p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item),
2087 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
2089 "txbf_leave_work_item");
2091 odm_initialize_work_item(
2093 &(p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item),
2094 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
2096 "txbf_fw_ndpa_work_item");
2098 odm_initialize_work_item(
2100 &(p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item),
2101 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
2103 "txbf_clk_work_item");
2105 odm_initialize_work_item(
2107 &(p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item),
2108 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
2110 "txbf_rate_work_item");
2112 odm_initialize_work_item(
2114 &(p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item),
2115 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
2117 "txbf_status_work_item");
2119 odm_initialize_work_item(
2121 &(p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item),
2122 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
2124 "txbf_reset_tx_path_work_item");
2126 odm_initialize_work_item(
2128 &(p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item),
2129 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
2131 "txbf_get_tx_rate_work_item");
2134 odm_initialize_work_item(
2136 &(p_dm_odm->adaptivity.phydm_pause_edcca_work_item),
2137 (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback,
2139 "phydm_pause_edcca_work_item");
2141 odm_initialize_work_item(
2143 &(p_dm_odm->adaptivity.phydm_resume_edcca_work_item),
2144 (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback,
2146 "phydm_resume_edcca_work_item");
2148 #if (PHYDM_LA_MODE_SUPPORT == 1)
2149 odm_initialize_work_item(
2151 &(p_dm_odm->adcsmp.adc_smp_work_item),
2152 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2154 "adc_smp_work_item");
2156 odm_initialize_work_item(
2158 &(p_dm_odm->adcsmp.adc_smp_work_item_1),
2159 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2161 "adc_smp_work_item_1");
2167 odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm)
2171 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2172 odm_free_work_item(&(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem));
2175 #if CONFIG_DYNAMIC_RX_PATH
2176 odm_free_work_item(&(p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem));
2181 #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
2182 odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_workitem));
2183 odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem));
2186 odm_free_work_item(&(p_dm_odm->path_div_switch_workitem));
2187 odm_free_work_item(&(p_dm_odm->cck_path_diversity_workitem));
2188 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2189 odm_free_work_item(&(p_dm_odm->fast_ant_training_workitem));
2191 odm_free_work_item(&(p_dm_odm->mpt_dig_workitem));
2192 odm_free_work_item(&(p_dm_odm->ra_rpt_workitem));
2193 /*odm_free_work_item((&p_dm_odm->sbdcnt_workitem));*/
2196 #if (BEAMFORMING_SUPPORT == 1)
2197 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item));
2198 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item));
2199 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
2200 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item));
2201 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item));
2202 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item));
2203 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
2204 odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
2207 odm_free_work_item((&p_dm_odm->adaptivity.phydm_pause_edcca_work_item));
2208 odm_free_work_item((&p_dm_odm->adaptivity.phydm_resume_edcca_work_item));
2210 #if (PHYDM_LA_MODE_SUPPORT == 1)
2211 odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item));
2212 odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item_1));
2216 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
2220 odm_FindMinimumRSSI(
2221 struct PHY_DM_STRUCT *p_dm_odm
2227 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2228 /* if(p_dm_odm->p_odm_sta_info[i] != NULL) */
2229 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) {
2230 if (p_dm_odm->p_odm_sta_info[i]->rssi_ave < rssi_min)
2231 rssi_min = p_dm_odm->p_odm_sta_info[i]->rssi_ave;
2235 p_dm_odm->rssi_min = rssi_min;
2241 struct PHY_DM_STRUCT *p_dm_odm
2245 boolean Linked = false;
2247 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2248 if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) {
2255 p_dm_odm->is_linked = Linked;
2260 odm_init_all_timers(
2261 struct PHY_DM_STRUCT *p_dm_odm
2264 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2265 odm_ant_div_timers(p_dm_odm, INIT_ANTDIV_TIMMER);
2268 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2269 phydm_dynamic_rx_path_timers(p_dm_odm, INIT_DRP_TIMMER);
2272 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2274 if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2275 odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer,
2276 (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer");
2278 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2279 odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer,
2280 (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer");
2283 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2284 odm_initialize_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer,
2285 (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer");
2286 odm_initialize_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer,
2287 (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer");
2288 odm_initialize_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer,
2289 (void *)phydm_sbd_callback, NULL, "SbdTimer");
2290 #if (BEAMFORMING_SUPPORT == 1)
2291 odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
2292 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer");
2296 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2297 #if (BEAMFORMING_SUPPORT == 1)
2298 odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer,
2299 (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer");
2305 odm_cancel_all_timers(
2306 struct PHY_DM_STRUCT *p_dm_odm
2309 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2311 /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */
2312 /* win7 platform. */
2314 HAL_ADAPTER_STS_CHK(p_dm_odm);
2317 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2318 odm_ant_div_timers(p_dm_odm, CANCEL_ANTDIV_TIMMER);
2321 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2322 phydm_dynamic_rx_path_timers(p_dm_odm, CANCEL_DRP_TIMMER);
2325 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2327 if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2328 odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2330 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2331 odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2334 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2335 odm_cancel_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer);
2336 odm_cancel_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer);
2337 odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2338 odm_cancel_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer);
2339 #if (BEAMFORMING_SUPPORT == 1)
2340 odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2344 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2345 #if (BEAMFORMING_SUPPORT == 1)
2346 odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer);
2354 odm_release_all_timers(
2355 struct PHY_DM_STRUCT *p_dm_odm
2358 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2359 odm_ant_div_timers(p_dm_odm, RELEASE_ANTDIV_TIMMER);
2362 #if (CONFIG_DYNAMIC_RX_PATH == 1)
2363 phydm_dynamic_rx_path_timers(p_dm_odm, RELEASE_DRP_TIMMER);
2366 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2368 if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific)
2369 odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2371 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2372 odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2375 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2376 odm_release_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer);
2377 odm_release_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer);
2378 odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer);
2379 odm_release_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer);
2380 #if (BEAMFORMING_SUPPORT == 1)
2381 odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2385 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2386 #if (BEAMFORMING_SUPPORT == 1)
2387 odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer);
2393 /* 3============================================================
2394 * 3 Tx Power Tracking
2395 * 3============================================================ */
2400 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2402 odm_init_all_threads(
2403 struct PHY_DM_STRUCT *p_dm_odm
2407 k_tpt_task_init(p_dm_odm->priv);
2412 odm_stop_all_threads(
2413 struct PHY_DM_STRUCT *p_dm_odm
2417 k_tpt_task_stop(p_dm_odm->priv);
2423 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2425 * 2011/07/26 MH Add an API for testing IQK fail case.
2428 odm_check_power_status(
2429 struct _ADAPTER *adapter)
2432 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
2433 struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
2434 RT_RF_POWER_STATE rt_state;
2435 PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
2437 /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
2438 if (p_mgnt_info->init_adpt_in_progress == true) {
2439 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return true, due to initadapter\n"));
2444 /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
2446 adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
2447 if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
2448 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
2449 adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state));
2454 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
2456 odm_check_power_status(
2457 struct _ADAPTER *adapter)
2460 /* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */
2461 struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
2462 RT_RF_POWER_STATE rt_state;
2463 PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
2465 /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
2466 if (p_mgnt_info->init_adpt_in_progress == true) {
2467 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter"));
2472 /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
2474 phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state));
2475 if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) {
2476 ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
2477 adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state));
2485 /* need to ODM CE Platform
2486 * move to here for ANT detection mechanism using */
2496 value = value & 0xFFFF;
2498 for (i = 0; i < 12; i++) {
2499 if (value <= db_invert_table[i][7])
2504 return 96; /* maximum 96 dB */
2507 for (j = 0; j < 8; j++) {
2508 if (value <= db_invert_table[i][j])
2512 dB = (i << 3) + j + 1;
2518 odm_convert_to_linear(
2527 value = value & 0xFF;
2529 i = (u8)((value - 1) >> 3);
2530 j = (u8)(value - 1) - (i << 3);
2532 linear = db_invert_table[i][j];
2538 * ODM multi-port consideration, added by Roger, 2013.10.01.
2541 odm_asoc_entry_init(
2542 struct PHY_DM_STRUCT *p_dm_odm
2545 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2546 struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_dm_odm->adapter);
2547 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_loop_adapter);
2548 struct PHY_DM_STRUCT *p_dm_out_src = &p_hal_data->DM_OutSrc;
2549 u8 total_assoc_entry_num = 0;
2551 u8 adaptercount = 0;
2553 odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, 0, &p_loop_adapter->MgntInfo.DefaultPort[0]);
2554 p_loop_adapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = total_assoc_entry_num;
2557 RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
2558 p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
2559 total_assoc_entry_num += 1;
2561 while (p_loop_adapter) {
2562 for (index = 0; index < ASSOCIATE_ENTRY_NUM; index++) {
2563 odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, total_assoc_entry_num + index, &p_loop_adapter->MgntInfo.AsocEntry[index]);
2564 p_loop_adapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = total_assoc_entry_num + index;
2567 total_assoc_entry_num += index;
2568 if (IS_HARDWARE_TYPE_8188E((p_dm_odm->adapter)))
2569 p_loop_adapter->RASupport = true;
2571 RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
2572 p_loop_adapter = GetNextExtAdapter(p_loop_adapter);
2575 RT_TRACE(COMP_INIT, DBG_LOUD, ("total_assoc_entry_num = %d\n", total_assoc_entry_num));
2576 if (total_assoc_entry_num < (ODM_ASSOCIATE_ENTRY_NUM - 1)) {
2578 RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n"));
2579 for (index = total_assoc_entry_num; index < ODM_ASSOCIATE_ENTRY_NUM; index++)
2580 odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, index, NULL);
2585 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2586 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
2587 void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm)
2589 #ifdef CONFIG_DM_RESP_TXAGC
2590 #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */
2591 #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
2593 /* RSSI vs TX power step mapping: decade TX power */
2594 static const u8 dtc_table_down[] = {
2603 /* RSSI vs TX power step mapping: increase TX power */
2604 static const u8 dtc_table_up[] = {
2607 (DTC_DWN_BASE - 10),
2608 (DTC_DWN_BASE - 15),
2609 (DTC_DWN_BASE - 15),
2610 (DTC_DWN_BASE - 20),
2611 (DTC_DWN_BASE - 20),
2612 (DTC_DWN_BASE - 25),
2613 (DTC_DWN_BASE - 25),
2614 (DTC_DWN_BASE - 30),
2624 /* As DIG is disabled, DTC is also disable */
2625 if (!(p_dm_odm->support_ability & ODM_XXXXXX))
2629 if (DTC_BASE < p_dm_odm->rssi_min) {
2630 /* need to decade the CTS TX power */
2632 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
2633 if ((dtc_table_down[i] >= p_dm_odm->rssi_min) || (dtc_steps >= 6))
2640 else if (DTC_DWN_BASE > p_dm_odm->rssi_min) {
2641 /* needs to increase the CTS TX power */
2644 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
2645 if ((dtc_table_up[i] <= p_dm_odm->rssi_min) || (dtc_steps >= 10))
2657 resp_txagc = dtc_steps | (sign << 4);
2658 resp_txagc = resp_txagc | (resp_txagc << 5);
2659 odm_write_1byte(p_dm_odm, 0x06d9, resp_txagc);
2661 ODM_RT_TRACE(p_dm_odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n",
2662 __func__, p_dm_odm->rssi_min, sign ? "minus" : "plus", dtc_steps));
2663 #endif /* CONFIG_RESP_TXAGC_ADJUST */
2666 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
2669 odm_update_power_training_state(
2670 struct PHY_DM_STRUCT *p_dm_odm
2673 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2674 struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
2675 struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
2678 if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN))
2681 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n"));
2682 p_dm_odm->is_change_state = false;
2685 if (p_dm_odm->force_power_training_state) {
2686 if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) {
2687 p_dm_odm->is_change_state = true;
2688 p_dm_odm->is_disable_power_training = true;
2689 } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) {
2690 p_dm_odm->is_change_state = true;
2691 p_dm_odm->is_disable_power_training = false;
2694 p_dm_odm->PT_score = 0;
2695 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2696 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2697 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n",
2698 p_dm_odm->force_power_training_state));
2702 if (!p_dm_odm->is_linked)
2706 if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) {
2707 p_dm_odm->PT_score = 0;
2708 p_dm_odm->is_change_state = true;
2709 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2710 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2711 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n"));
2716 if (p_dm_odm->nhm_cnt_0 >= 215)
2718 else if (p_dm_odm->nhm_cnt_0 >= 190)
2719 score = 1; /* unknow state */
2723 rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck);
2725 if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) {
2726 if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all)
2728 else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all)
2733 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n",
2734 rx_pkt_cnt, false_alm_cnt->cnt_cca_all));
2736 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
2737 (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck)));
2738 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n",
2739 p_dm_odm->nhm_cnt_0, score));
2742 p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2);
2743 score = (p_dm_odm->PT_score + 32) >> 6;
2744 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n",
2745 p_dm_odm->PT_score, score));
2749 if (p_dm_odm->is_disable_power_training) {
2750 p_dm_odm->is_change_state = true;
2751 p_dm_odm->is_disable_power_training = false;
2752 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n"));
2754 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n"));
2755 } else if (score == 0) {
2756 if (!p_dm_odm->is_disable_power_training) {
2757 p_dm_odm->is_change_state = true;
2758 p_dm_odm->is_disable_power_training = true;
2759 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n"));
2761 ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n"));
2764 p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
2765 p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0;
2771 /*===========================================================*/
2772 /* The following is for compile only*/
2773 /*===========================================================*/
2774 /*#define TARGET_CHNL_NUM_2G_5G 59*/
2775 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2777 u8 get_right_chnl_place_for_iqk(u8 chnl)
2779 u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100,
2780 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
2786 for (place = 14; place < sizeof(channel_all); place++) {
2787 if (channel_all[place] == chnl)
2796 /*===========================================================*/
2799 phydm_noisy_detection(
2800 struct PHY_DM_STRUCT *p_dm_odm
2803 u32 total_fa_cnt, total_cca_cnt;
2804 u32 score = 0, i, score_smooth;
2806 total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all;
2807 total_fa_cnt = p_dm_odm->false_alm_cnt.cnt_all;
2810 if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */
2812 else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */
2814 else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */
2816 else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */
2818 else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */
2820 else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */
2822 else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */
2824 else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */
2826 else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */
2828 else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */
2830 else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */
2833 for (i = 0; i <= 16; i++) {
2834 if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
2840 /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
2841 p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2);
2843 /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
2844 score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0;
2846 p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
2848 switch (score_smooth) {
2850 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2851 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=0%%\n"));
2854 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2855 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=6.25%%\n"));
2858 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2859 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=12.5%%\n"));
2862 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2863 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=18.75%%\n"));
2866 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2867 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=25%%\n"));
2870 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2871 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=31.25%%\n"));
2874 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2875 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=37.5%%\n"));
2878 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2879 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=43.75%%\n"));
2882 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2883 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=50%%\n"));
2886 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2887 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=56.25%%\n"));
2890 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2891 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=62.5%%\n"));
2894 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2895 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=68.75%%\n"));
2898 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2899 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=75%%\n"));
2902 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2903 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=81.25%%\n"));
2906 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2907 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=87.5%%\n"));
2910 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2911 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=93.75%%\n"));
2914 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2915 ("[NoisyDetection] total_fa_cnt/total_cca_cnt=100%%\n"));
2918 ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD,
2919 ("[NoisyDetection] Unknown value!! Need Check!!\n"));
2922 ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD,
2923 ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n",
2924 total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision));
2929 phydm_set_ext_switch(
2931 u32 *const dm_value,
2937 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2939 u32 out_len = *_out_len;
2940 u32 ext_ant_switch = dm_value[0];
2942 if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
2944 /*Output Pin Settings*/
2945 odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/
2946 odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /*by WLAN control*/
2948 odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
2949 odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
2951 if (ext_ant_switch == MAIN_ANT) {
2952 odm_set_bb_reg(p_dm_odm, 0xCB4, (BIT(29) | BIT(28)), 1);
2953 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'01 (Main)\n"));
2954 } else if (ext_ant_switch == AUX_ANT) {
2955 odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29) | BIT(28), 2);
2956 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'10 (Aux)\n"));
2962 phydm_csi_mask_enable(
2967 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2970 reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
2972 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
2974 odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value);
2975 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value));
2977 } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
2979 odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value);
2980 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value));
2986 phydm_clean_all_csi_mask(
2990 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
2992 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
2994 odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0);
2995 odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0);
2996 odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0);
2997 odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0);
2999 } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3001 odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0);
3002 odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0);
3003 odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0);
3004 odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0);
3005 odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0);
3006 odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0);
3007 odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0);
3008 odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0);
3013 phydm_set_csi_mask_reg(
3019 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3020 u8 byte_offset, bit_offset;
3024 u32 tone_num_shift = 0;
3025 u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
3027 /* calculate real tone idx*/
3028 if ((tone_idx_tmp % 10) >= 5)
3031 tone_idx_tmp = (tone_idx_tmp / 10);
3033 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3036 csi_mask_reg_p = 0xD40;
3037 csi_mask_reg_n = 0xD48;
3039 } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3042 csi_mask_reg_p = 0x880;
3043 csi_mask_reg_n = 0x890;
3046 if (tone_direction == FREQ_POSITIVE) {
3048 if (tone_idx_tmp >= (tone_num - 1))
3049 tone_idx_tmp = (tone_num - 1);
3051 byte_offset = (u8)(tone_idx_tmp >> 3);
3052 bit_offset = (u8)(tone_idx_tmp & 0x7);
3053 target_reg = csi_mask_reg_p + byte_offset;
3056 tone_num_shift = tone_num;
3058 if (tone_idx_tmp >= tone_num)
3059 tone_idx_tmp = tone_num;
3061 tone_idx_tmp = tone_num - tone_idx_tmp;
3063 byte_offset = (u8)(tone_idx_tmp >> 3);
3064 bit_offset = (u8)(tone_idx_tmp & 0x7);
3065 target_reg = csi_mask_reg_n + byte_offset;
3068 reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg);
3069 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
3070 reg_tmp_value |= BIT(bit_offset);
3071 odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value);
3072 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
3082 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3083 u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/
3084 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
3085 485, 505, 525, 555, 585, 615, 635
3088 u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/
3089 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/
3090 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/
3091 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/
3092 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/
3093 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275
3098 u8 nbi_table_idx = FFT_128_TYPE;
3100 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
3102 nbi_table_idx = FFT_128_TYPE;
3103 else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES)
3105 nbi_table_idx = FFT_256_TYPE;
3106 else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) {
3109 nbi_table_idx = FFT_256_TYPE;
3111 nbi_table_idx = FFT_128_TYPE;
3114 if (nbi_table_idx == FFT_128_TYPE) {
3116 for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
3117 if (tone_idx_tmp < nbi_table_128[i]) {
3123 } else if (nbi_table_idx == FFT_256_TYPE) {
3125 for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
3126 if (tone_idx_tmp < nbi_table_256[i]) {
3133 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3134 odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx);
3135 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx));
3138 odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx);
3139 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx));
3151 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3154 reg_value = (enable == NBI_ENABLE) ? 1 : 0;
3156 if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
3158 odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value);
3159 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value));
3161 } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
3163 odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value);
3164 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value));
3177 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3179 u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173};
3180 u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165};
3181 u32 *p_start_ch = &(start_ch_per_40m[0]);
3182 u32 num_start_channel = NUM_START_CH_40M;
3183 u32 channel_offset = 0;
3187 if (channel <= 14 && channel > 0) {
3192 fc = 2412 + (channel - 1) * 5;
3194 if (bw == 40 && (second_ch == PHYDM_ABOVE)) {
3196 if (channel >= 10) {
3197 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
3201 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
3204 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch));
3211 else if (channel >= 36 && channel <= 177) {
3216 num_start_channel = NUM_START_CH_40M;
3217 p_start_ch = &(start_ch_per_40m[0]);
3218 channel_offset = CH_OFFSET_40M;
3219 } else if (bw == 80) {
3220 num_start_channel = NUM_START_CH_80M;
3221 p_start_ch = &(start_ch_per_80m[0]);
3222 channel_offset = CH_OFFSET_80M;
3225 for (i = 0; i < num_start_channel; i++) {
3227 if (channel < p_start_ch[i + 1]) {
3228 channel = p_start_ch[i] + channel_offset;
3232 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel));
3235 fc = 5180 + (channel - 36) * 5;
3238 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel));
3249 phydm_calculate_intf_distance(
3254 u32 *p_tone_idx_tmp_in
3257 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3261 u8 set_result = SET_NO_NEED;
3263 bw_up = fc + bw / 2;
3264 bw_low = fc - bw / 2;
3266 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference));
3268 if ((f_interference >= bw_low) && (f_interference <= bw_up)) {
3270 int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc);
3271 tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */
3272 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10)));
3273 *p_tone_idx_tmp_in = tone_idx_tmp;
3274 set_result = SET_SUCCESS;
3283 phydm_csi_mask_setting(
3292 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3297 u8 set_result = SET_SUCCESS;
3299 if (enable == CSI_MASK_DISABLE) {
3300 set_result = SET_SUCCESS;
3301 phydm_clean_all_csi_mask(p_dm_odm);
3305 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3306 channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
3309 if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR)
3310 set_result = SET_ERROR;
3313 /*calculate interference distance*/
3314 if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
3316 tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE;
3317 phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction);
3318 set_result = SET_SUCCESS;
3320 set_result = SET_NO_NEED;
3324 if (set_result == SET_SUCCESS)
3325 phydm_csi_mask_enable(p_dm_odm, enable);
3327 phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE);
3342 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3346 u8 set_result = SET_SUCCESS;
3349 if (enable == NBI_DISABLE)
3350 set_result = SET_SUCCESS;
3354 ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3355 channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L")));
3358 if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR)
3359 set_result = SET_ERROR;
3362 /*calculate interference distance*/
3363 if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
3365 phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw);
3366 set_result = SET_SUCCESS;
3368 set_result = SET_NO_NEED;
3372 if (set_result == SET_SUCCESS)
3373 phydm_nbi_enable(p_dm_odm, enable);
3375 phydm_nbi_enable(p_dm_odm, NBI_DISABLE);
3384 u32 *const dm_value,
3390 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
3392 u32 out_len = *_out_len;
3393 u32 channel = dm_value[1];
3394 u32 bw = dm_value[2];
3395 u32 f_interference = dm_value[3];
3396 u32 second_ch = dm_value[4];
3400 /*-------------------------------------------------------------------------------------------------------------------------------*/
3401 if (function_map == PHYDM_API_NBI) {
3403 if (dm_value[0] == 100) {
3405 PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
3408 } else if (dm_value[0] == NBI_ENABLE) {
3410 PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3411 channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L")));
3412 set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch);
3414 } else if (dm_value[0] == NBI_DISABLE) {
3416 PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n"));
3417 set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch);
3421 set_result = SET_ERROR;
3422 PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));
3427 /*-------------------------------------------------------------------------------------------------------------------------------*/
3428 else if (function_map == PHYDM_API_CSI_MASK) {
3430 if (dm_value[0] == 100) {
3432 PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
3435 } else if (dm_value[0] == CSI_MASK_ENABLE) {
3437 PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
3438 channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L")));
3439 set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, channel, bw, f_interference, second_ch);
3441 } else if (dm_value[0] == CSI_MASK_DISABLE) {
3443 PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n"));
3444 set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch);
3448 set_result = SET_ERROR;
3449 PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));